kmsupc5.dts 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ABB PGGA SUPC5 Device Tree Source
  4. *
  5. * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
  6. *
  7. */
  8. /dts-v1/;
  9. #include "km8321.dtsi"
  10. / {
  11. model = "SUPC5";
  12. compatible = "ABB,kmpbec8321";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. aliases {
  16. ethernet0 = &enet_piggy2;
  17. serial0 = &serial0;
  18. };
  19. };
  20. &i2c0 {
  21. mux@70 {
  22. compatible = "nxp,pca9547";
  23. reg = <0x70>;
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. i2c@1 {
  27. reg = <1>;
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. /* Inventory EEPROM of the unit itself */
  31. ivm@50 {
  32. label = "MAIN_CTRL";
  33. compatible = "dummy";
  34. reg = <0x50>;
  35. };
  36. };
  37. i2c@2 {
  38. reg = <2>;
  39. #address-cells = <1>;
  40. #size-cells = <0>;
  41. /* Temperature sensors */
  42. temp@49 {
  43. label = "board";
  44. compatible = "national,lm75";
  45. reg = <0x49>;
  46. };
  47. };
  48. };
  49. };
  50. &par_io {
  51. /* UCC5 as HDLC controller for ICN */
  52. pio_ucc5: ucc_pin@04 {
  53. pio-map = <
  54. /* port pin dir open_drain assignment has_irq */
  55. 2 0 1 0 2 0 /* TxD0 */
  56. 2 8 2 0 2 0 /* RxD0 */
  57. 2 29 2 0 2 0 /* CTS */
  58. 3 30 2 0 1 0 /* ICN CLK */
  59. >;
  60. };
  61. /* UCC4 Piggy Ethernet */
  62. pio_ucc4: ucc_pin@03 {
  63. pio-map = <
  64. /* port pin dir open_drain assignment has_irq */
  65. 3 4 3 0 2 0 /* MDIO */
  66. 3 5 1 0 2 0 /* MDC */
  67. 1 18 1 0 1 0 /* TxD0 */
  68. 1 19 1 0 1 0 /* TxD1 */
  69. 1 22 2 0 1 0 /* RxD0 */
  70. 1 23 2 0 1 0 /* RxD1 */
  71. 1 26 2 0 1 0 /* RX_ER */
  72. 1 28 2 0 1 0 /* RX_DV */
  73. 1 30 1 0 1 0 /* TX_EN */
  74. 1 31 2 0 1 0 /* CRS */
  75. /* UCC4_RMII_CLK (CLK17) */
  76. 3 10 2 0 3 0
  77. >;
  78. };
  79. pio_spi: spi_pin@01 {
  80. pio-map = <
  81. /*
  82. * port pin dir open_drain assignment has_irq
  83. * SPI_MOSI (PD0, bi, f3)
  84. */
  85. 3 0 3 0 1 0
  86. /* SPI_MISO (PD1, bi, f3) */
  87. 3 1 3 0 1 0
  88. /* SPI_CLK (PD2, bi, f3) */
  89. 3 2 3 0 1 0
  90. >;
  91. };
  92. };
  93. &spi0 {
  94. pio-handle = <&pio_spi>;
  95. };
  96. &localbus {
  97. ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
  98. 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
  99. 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */
  100. flash@0,0 {
  101. compatible = "cfi-flash";
  102. reg = <0 0x00000000 0x04000000>;
  103. bank-width = <2>;
  104. #address-cells = <1>;
  105. #size-cells = <1>;
  106. partition@0 { /* 768KB */
  107. label = "u-boot";
  108. reg = <0 0xC0000>;
  109. };
  110. partition@c0000 { /* 128KB */
  111. label = "env";
  112. reg = <0xc0000 0x20000>;
  113. };
  114. partition@e0000 { /* 128KB */
  115. label = "envred";
  116. reg = <0xe0000 0x20000>;
  117. };
  118. partition@100000 { /* 64512KB */
  119. label = "ubi0";
  120. reg = <0x100000 0x3F00000>;
  121. };
  122. };
  123. };