kmopti2.dts 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ABB PGGA OPTI2 Device Tree Source
  4. *
  5. * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
  6. *
  7. */
  8. /dts-v1/;
  9. #include "km8321.dtsi"
  10. / {
  11. model = "KMOPTI2";
  12. compatible = "ABB,kmpbec8321";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. aliases {
  16. ethernet0 = &enet_piggy2;
  17. serial0 = &serial0;
  18. };
  19. };
  20. &i2c0 {
  21. mux@70 {
  22. compatible = "nxp,pca9547";
  23. reg = <0x70>;
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. i2c@1 {
  27. reg = <1>;
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. /* Inventory EEPROM of the unit itself */
  31. ivm@50 {
  32. label = "MAIN_CTRL";
  33. compatible = "dummy";
  34. reg = <0x50>;
  35. };
  36. };
  37. i2c@2 {
  38. reg = <2>;
  39. #address-cells = <1>;
  40. #size-cells = <0>;
  41. /* Temperature sensors */
  42. temp@49 {
  43. label = "board";
  44. compatible = "national,lm75";
  45. reg = <0x49>;
  46. };
  47. temp@4a {
  48. label = "power";
  49. compatible = "national,lm75";
  50. reg = <0x4a>;
  51. };
  52. };
  53. i2c@6 {
  54. reg = <6>;
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. };
  58. i2c@5 {
  59. reg = <5>;
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. };
  63. i2c@4 {
  64. reg = <4>;
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. };
  68. i2c@3 {
  69. reg = <3>;
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. };
  73. };
  74. };
  75. &par_io {
  76. /* UCC5 as HDLC controller for ICN */
  77. pio_ucc5: ucc_pin@04 {
  78. pio-map = <
  79. /* port pin dir open_drain assignment has_irq */
  80. 2 0 1 0 2 0 /* TxD0 */
  81. 2 8 2 0 2 0 /* RxD0 */
  82. 2 29 2 0 2 0 /* CTS */
  83. 3 30 2 0 1 0 /* ICN CLK */
  84. >;
  85. };
  86. /* UCC4 Piggy Ethernet */
  87. pio_ucc4: ucc_pin@03 {
  88. pio-map = <
  89. /* port pin dir open_drain assignment has_irq */
  90. 3 4 3 0 2 0 /* MDIO */
  91. 3 5 1 0 2 0 /* MDC */
  92. 1 18 1 0 1 0 /* TxD0 */
  93. 1 19 1 0 1 0 /* TxD1 */
  94. 1 22 2 0 1 0 /* RxD0 */
  95. 1 23 2 0 1 0 /* RxD1 */
  96. 1 26 2 0 1 0 /* RX_ER */
  97. 1 28 2 0 1 0 /* RX_DV */
  98. 1 30 1 0 1 0 /* TX_EN */
  99. 1 31 2 0 1 0 /* CRS */
  100. 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
  101. >;
  102. };
  103. pio_spi: spi_pin@01 {
  104. pio-map = <
  105. /* port pin dir open_drain assignment has_irq */
  106. 3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */
  107. 3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */
  108. 3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */
  109. >;
  110. };
  111. };
  112. &localbus {
  113. ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
  114. 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
  115. 2 0 0xa0000000 0x10000000 /* LB 2 PAXE */
  116. 3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */
  117. flash@0,0 {
  118. compatible = "cfi-flash";
  119. reg = <0 0x00000000 0x04000000>;
  120. bank-width = <2>;
  121. #address-cells = <1>;
  122. #size-cells = <1>;
  123. use-advanced-sector-protection;
  124. partition@0 { /* 768KB */
  125. label = "u-boot";
  126. reg = <0 0xC0000>;
  127. };
  128. partition@c0000 { /* 128KB */
  129. label = "env";
  130. reg = <0xc0000 0x20000>;
  131. };
  132. partition@e0000 { /* 128KB */
  133. label = "envred";
  134. reg = <0xe0000 0x20000>;
  135. };
  136. partition@100000 { /* 64512KB */
  137. label = "ubi0";
  138. reg = <0x100000 0x3F00000>;
  139. };
  140. };
  141. };