kmeter1.dts 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ABB PGGA KMETER1 Device Tree Source
  4. *
  5. * 2008-2011 DENX Software Engineering GmbH
  6. * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
  7. */
  8. /dts-v1/;
  9. #include "km836x.dtsi"
  10. / {
  11. model = "KMETER1";
  12. compatible = "ABB,KMETER1";
  13. aliases {
  14. ethernet0 = &enet_piggy2;
  15. ethernet1 = &enet_estar1;
  16. ethernet2 = &enet_estar2;
  17. ethernet3 = &enet_eth1;
  18. ethernet4 = &enet_eth2;
  19. ethernet5 = &enet_eth3;
  20. ethernet6 = &enet_eth4;
  21. serial0 = &serial0;
  22. };
  23. };
  24. &i2c0 {
  25. mux@70 {
  26. compatible = "nxp,pca9547";
  27. reg = <0x70>;
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. i2c@1 {
  31. reg = <1>;
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34. /* Inventory EEPROM of the unit itself */
  35. ivm@50 {
  36. label = "MAIN_CTRL";
  37. compatible = "dummy";
  38. reg = <0x50>;
  39. };
  40. };
  41. i2c@2 {
  42. reg = <2>;
  43. #address-cells = <1>;
  44. #size-cells = <0>;
  45. /* Temperature sensors */
  46. temp@48 {
  47. label = "Top";
  48. compatible = "national,lm75";
  49. reg = <0x48>;
  50. };
  51. temp@49 {
  52. label = "Control";
  53. compatible = "national,lm75";
  54. reg = <0x49>;
  55. };
  56. temp@4a {
  57. label = "Power";
  58. compatible = "national,lm75";
  59. reg = <0x4a>;
  60. };
  61. temp@4b {
  62. label = "Front";
  63. compatible = "national,lm75";
  64. reg = <0x4b>;
  65. };
  66. };
  67. };
  68. };
  69. &serial0 {
  70. status = "okay";
  71. };
  72. &par_io {
  73. pio_ucc1: ucc_pin@0 {
  74. pio-map = <
  75. /* port pin dir open_drain assignment has_irq */
  76. 0 1 3 0 2 0 /* MDIO */
  77. 0 2 1 0 1 0 /* MDC */
  78. 0 3 1 0 1 0 /* TxD0 */
  79. 0 4 1 0 1 0 /* TxD1 */
  80. 0 5 1 0 1 0 /* TxD2 */
  81. 0 6 1 0 1 0 /* TxD3 */
  82. 0 9 2 0 1 0 /* RxD0 */
  83. 0 10 2 0 1 0 /* RxD1 */
  84. 0 11 2 0 1 0 /* RxD2 */
  85. 0 12 2 0 1 0 /* RxD3 */
  86. 0 7 1 0 1 0 /* TX_EN */
  87. 0 8 1 0 1 0 /* TX_ER */
  88. 0 15 2 0 1 0 /* RX_DV */
  89. 0 16 2 0 1 0 /* RX_ER */
  90. 0 0 2 0 1 0 /* RX_CLK */
  91. 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
  92. 2 8 2 0 1 0 /* GTX125 - CLK9 */
  93. >;
  94. };
  95. pio_ucc2: ucc_pin@1 {
  96. pio-map = <
  97. /* port pin dir open_drain assignment has_irq */
  98. 0 1 3 0 2 0 /* MDIO */
  99. 0 2 1 0 1 0 /* MDC */
  100. 0 17 1 0 1 0 /* TxD0 */
  101. 0 18 1 0 1 0 /* TxD1 */
  102. 0 19 1 0 1 0 /* TxD2 */
  103. 0 20 1 0 1 0 /* TxD3 */
  104. 0 23 2 0 1 0 /* RxD0 */
  105. 0 24 2 0 1 0 /* RxD1 */
  106. 0 25 2 0 1 0 /* RxD2 */
  107. 0 26 2 0 1 0 /* RxD3 */
  108. 0 21 1 0 1 0 /* TX_EN */
  109. 0 22 1 0 1 0 /* TX_ER */
  110. 0 29 2 0 1 0 /* RX_DV */
  111. 0 30 2 0 1 0 /* RX_ER */
  112. 0 31 2 0 1 0 /* RX_CLK */
  113. 2 2 1 0 2 0 /* GTX_CLK - CLK3 */
  114. 2 3 2 0 1 0 /* GTX125 - CLK4 */
  115. >;
  116. };
  117. pio_ucc4: ucc_pin@3 {
  118. pio-map = <
  119. /* port pin dir open_drain assignment has_irq */
  120. 0 1 3 0 2 0 /* MDIO */
  121. 0 2 1 0 1 0 /* MDC */
  122. 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
  123. 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
  124. 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
  125. 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
  126. 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
  127. 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
  128. 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
  129. 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
  130. >;
  131. };
  132. pio_ucc5: ucc_pin@4 {
  133. pio-map = <
  134. /* port pin dir open_drain assignment has_irq */
  135. 0 1 3 0 2 0 /* MDIO */
  136. 0 2 1 0 1 0 /* MDC */
  137. 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
  138. 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
  139. 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
  140. 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
  141. 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
  142. 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
  143. 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
  144. >;
  145. };
  146. pio_ucc6: ucc_pin@5 {
  147. pio-map = <
  148. /* port pin dir open_drain assignment has_irq */
  149. 0 1 3 0 2 0 /* MDIO */
  150. 0 2 1 0 1 0 /* MDC */
  151. 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
  152. 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
  153. 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
  154. 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
  155. 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
  156. 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
  157. 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
  158. >;
  159. };
  160. pio_ucc7: ucc_pin@6 {
  161. pio-map = <
  162. /* port pin dir open_drain assignment has_irq */
  163. 0 1 3 0 2 0 /* MDIO */
  164. 0 2 1 0 1 0 /* MDC */
  165. 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
  166. 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
  167. 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
  168. 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
  169. 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
  170. 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
  171. 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
  172. >;
  173. };
  174. pio_ucc8: ucc_pin@7 {
  175. pio-map = <
  176. /* port pin dir open_drain assignment has_irq */
  177. 0 1 3 0 2 0 /* MDIO */
  178. 0 2 1 0 1 0 /* MDC */
  179. 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
  180. 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
  181. 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
  182. 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
  183. 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
  184. 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
  185. 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
  186. 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
  187. >;
  188. };
  189. pio_spi: spi_pin@01 {
  190. pio-map = <
  191. /* port pin dir open_drain assignment has_irq */
  192. 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */
  193. 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */
  194. >;
  195. };
  196. /* UCC3 as HDLC controller for ICN */
  197. pio5: ucc_pin@02 {
  198. pio-map = <
  199. /* port pin dir open_drain assignment has_irq */
  200. 1 0 1 0 1 0 /* TxD0 */
  201. 1 6 2 0 1 0 /* RxD0 */
  202. 1 12 2 0 1 0 /* CTS */
  203. 2 11 2 0 1 0 /* TX-CLK12 */
  204. >;
  205. };
  206. pio_tdm: tdm_pin@00 {
  207. pio-map = <
  208. /* port pin dir open_drain assignment has_irq */
  209. /* TDMa */
  210. 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
  211. 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
  212. 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
  213. 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
  214. /* TDMb */
  215. 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
  216. 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
  217. 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
  218. 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
  219. /* TDMc */
  220. 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
  221. 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
  222. 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
  223. 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
  224. /* TDMd */
  225. 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
  226. 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
  227. 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
  228. 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
  229. /* TDMe */
  230. 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
  231. 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
  232. 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
  233. 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
  234. /* TDMf */
  235. 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
  236. 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
  237. 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
  238. 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
  239. /* TDMg */
  240. 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
  241. 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
  242. 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
  243. 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
  244. /* TDMh */
  245. 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
  246. 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
  247. 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
  248. 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
  249. /* RxTxClk0/1 */
  250. 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
  251. 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
  252. /* RxTxSync0/1 */
  253. 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
  254. 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
  255. };
  256. };
  257. &qe {
  258. /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
  259. enet_estar1: ucc@2000 {
  260. device_type = "network";
  261. compatible = "ucc_geth";
  262. cell-index = <1>;
  263. reg = <0x2000 0x200>;
  264. interrupts = <32>;
  265. interrupt-parent = <&qeic>;
  266. local-mac-address = [ 00 00 00 00 00 00 ];
  267. rx-clock-name = "none";
  268. tx-clock-name = "clk9";
  269. phy-handle = <&phy_estar1>;
  270. phy-connection-type = "rgmii-id";
  271. pio-handle = <&pio_ucc1>;
  272. };
  273. /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
  274. enet_estar2: ucc@3000 {
  275. device_type = "network";
  276. compatible = "ucc_geth";
  277. cell-index = <2>;
  278. reg = <0x3000 0x200>;
  279. interrupts = <33>;
  280. interrupt-parent = <&qeic>;
  281. local-mac-address = [ 00 00 00 00 00 00 ];
  282. rx-clock-name = "none";
  283. tx-clock-name = "clk4";
  284. phy-handle = <&phy_estar2>;
  285. phy-connection-type = "rgmii-id";
  286. pio-handle = <&pio_ucc2>;
  287. };
  288. /* Piggy2 (UCC4, MDIO 0x00, RMII) */
  289. enet_piggy2: ucc@3200 {
  290. device_type = "network";
  291. compatible = "ucc_geth";
  292. cell-index = <4>;
  293. reg = <0x3200 0x200>;
  294. interrupts = <35>;
  295. interrupt-parent = <&qeic>;
  296. local-mac-address = [ 00 00 00 00 00 00 ];
  297. rx-clock-name = "none";
  298. tx-clock-name = "clk17";
  299. phy-handle = <&phy_piggy2>;
  300. phy-connection-type = "rmii";
  301. pio-handle = <&pio_ucc4>;
  302. };
  303. /* Eth-1 (UCC5, MDIO 0x08, RMII) */
  304. enet_eth1: ucc@2400 {
  305. device_type = "network";
  306. compatible = "ucc_geth";
  307. cell-index = <5>;
  308. reg = <0x2400 0x200>;
  309. interrupts = <40>;
  310. interrupt-parent = <&qeic>;
  311. local-mac-address = [ 00 00 00 00 00 00 ];
  312. rx-clock-name = "none";
  313. tx-clock-name = "clk16";
  314. phy-handle = <&phy_eth1>;
  315. phy-connection-type = "rmii";
  316. pio-handle = <&pio_ucc5>;
  317. };
  318. /* Eth-2 (UCC6, MDIO 0x09, RMII) */
  319. enet_eth2: ucc@3400 {
  320. device_type = "network";
  321. compatible = "ucc_geth";
  322. cell-index = <6>;
  323. reg = <0x3400 0x200>;
  324. interrupts = <41>;
  325. interrupt-parent = <&qeic>;
  326. local-mac-address = [ 00 00 00 00 00 00 ];
  327. rx-clock-name = "none";
  328. tx-clock-name = "clk16";
  329. phy-handle = <&phy_eth2>;
  330. phy-connection-type = "rmii";
  331. pio-handle = <&pio_ucc6>;
  332. };
  333. /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
  334. enet_eth3: ucc@2600 {
  335. device_type = "network";
  336. compatible = "ucc_geth";
  337. cell-index = <7>;
  338. reg = <0x2600 0x200>;
  339. interrupts = <42>;
  340. interrupt-parent = <&qeic>;
  341. local-mac-address = [ 00 00 00 00 00 00 ];
  342. rx-clock-name = "none";
  343. tx-clock-name = "clk16";
  344. phy-handle = <&phy_eth3>;
  345. phy-connection-type = "rmii";
  346. pio-handle = <&pio_ucc7>;
  347. };
  348. /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
  349. enet_eth4: ucc@3600 {
  350. device_type = "network";
  351. compatible = "ucc_geth";
  352. cell-index = <8>;
  353. reg = <0x3600 0x200>;
  354. interrupts = <43>;
  355. interrupt-parent = <&qeic>;
  356. local-mac-address = [ 00 00 00 00 00 00 ];
  357. rx-clock-name = "none";
  358. tx-clock-name = "clk16";
  359. phy-handle = <&phy_eth4>;
  360. phy-connection-type = "rmii";
  361. pio-handle = <&pio_ucc8>;
  362. };
  363. mdio@3320 {
  364. #address-cells = <1>;
  365. #size-cells = <0>;
  366. reg = <0x3320 0x18>;
  367. compatible = "fsl,ucc-mdio";
  368. /* Piggy2 (UCC4, MDIO 0x00, RMII) */
  369. phy_piggy2: ethernet-phy@0 {
  370. reg = <0x0>;
  371. };
  372. /* Eth-1 (UCC5, MDIO 0x08, RMII) */
  373. phy_eth1: ethernet-phy@8 {
  374. reg = <0x08>;
  375. };
  376. /* Eth-2 (UCC6, MDIO 0x09, RMII) */
  377. phy_eth2: ethernet-phy@9 {
  378. reg = <0x09>;
  379. };
  380. /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
  381. phy_eth3: ethernet-phy@a {
  382. reg = <0x0a>;
  383. };
  384. /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
  385. phy_eth4: ethernet-phy@b {
  386. reg = <0x0b>;
  387. };
  388. /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
  389. phy_estar1: ethernet-phy@10 {
  390. interrupt-parent = <&ipic>;
  391. interrupts = <17 0x8>;
  392. reg = <0x10>;
  393. };
  394. /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
  395. phy_estar2: ethernet-phy@11 {
  396. interrupt-parent = <&ipic>;
  397. interrupts = <18 0x8>;
  398. reg = <0x11>;
  399. };
  400. };
  401. };
  402. &localbus {
  403. ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
  404. 1 0 0xe8000000 0x01000000 /* LB 1 */
  405. 3 0 0xa0000000 0x10000000>; /* LB 3 */
  406. flash@0,0 {
  407. compatible = "cfi-flash";
  408. reg = <0 0 0x04000000>;
  409. #address-cells = <1>;
  410. #size-cells = <1>;
  411. bank-width = <2>;
  412. partition@0 { /* 768KB */
  413. label = "u-boot";
  414. reg = <0 0xC0000>;
  415. };
  416. partition@c0000 { /* 128KB */
  417. label = "env";
  418. reg = <0xC0000 0x20000>;
  419. };
  420. partition@e0000 { /* 128KB */
  421. label = "envred";
  422. reg = <0xE0000 0x20000>;
  423. };
  424. partition@100000 { /* 64512KB */
  425. label = "ubi0";
  426. reg = <0x100000 0x3F00000>;
  427. };
  428. };
  429. };
  430. #include "kmeter1-uboot.dtsi"