kmcoge5ne.dts 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ABB PGGA KMCOGE5ne Device Tree Source
  4. *
  5. * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
  6. *
  7. */
  8. /dts-v1/;
  9. #include "km836x.dtsi"
  10. / {
  11. model = "kmcoge5ne";
  12. compatible = "ABB,kmcoge5ne";
  13. aliases {
  14. ethernet0 = &enet_admin;
  15. ethernet1 = &enet_mate;
  16. ethernet2 = &enet_switch;
  17. serial0 = &serial0;
  18. };
  19. };
  20. &soc {
  21. /* brg for hdlc clk */
  22. brg@0 {
  23. compatible = "fsl,mpc-brg";
  24. brg-name = "brg16";
  25. brg-frequency = <20000000>; /* 20 MHz */
  26. pio-handle = <&pio_brg>;
  27. };
  28. };
  29. &i2c0 {
  30. mux@70 {
  31. compatible = "nxp,pca9547";
  32. reg = <0x70>;
  33. #address-cells = <1>;
  34. #size-cells = <0>;
  35. i2c@1 {
  36. reg = <1>;
  37. #address-cells = <1>;
  38. #size-cells = <0>;
  39. /* Inventory EEPROM of the unit itself */
  40. ivm@50 {
  41. label = "MAIN_CTRL";
  42. compatible = "dummy";
  43. reg = <0x50>;
  44. };
  45. };
  46. i2c@2 {
  47. reg = <2>;
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. /* Inventory EEPROM of the fan unit */
  51. fanu-ivm@50 {
  52. label = "FANUV";
  53. compatible = "dummy";
  54. reg = <0x50>;
  55. };
  56. /* fan unit (GPIOs and so on) */
  57. fanu@20 {
  58. label = "FANUV_CTRL";
  59. compatible = "dummy";
  60. reg = <0x20>;
  61. };
  62. };
  63. i2c@3 {
  64. reg = <3>;
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. backplane@50 {
  68. label = "BP_CTRL";
  69. compatible = "dummy";
  70. reg = <0x50>;
  71. };
  72. };
  73. };
  74. };
  75. &serial0 {
  76. status = "okay";
  77. };
  78. &par_io {
  79. pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */
  80. pio-map = <
  81. /* port pin dir open_drain assignment has_irq */
  82. 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
  83. 0 2 1 0 1 0 /* MDC (PA2, in, f1) */
  84. 0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */
  85. 0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */
  86. 0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */
  87. 0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */
  88. 0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */
  89. 0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */
  90. 0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */
  91. 0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */
  92. 0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */
  93. 0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */
  94. 0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */
  95. 2 9 1 0 3 0 /* GTX_CLK (CLK10) */
  96. 2 8 2 0 1 0 /* GTX125 (CLK9) */
  97. >;
  98. };
  99. pio_ucc4: ucc_pin@3 { /* RMII, admin front port */
  100. pio-map = <
  101. /* port pin dir open_drain assignment has_irq */
  102. 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
  103. 0 2 1 0 1 0 /* MDC (PA2, in, f1) */
  104. 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
  105. 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
  106. 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
  107. 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
  108. 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
  109. 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
  110. 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
  111. 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
  112. >;
  113. };
  114. pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */
  115. pio-map = <
  116. /* port pin dir open_drain assignment has_irq */
  117. 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
  118. 0 2 1 0 1 0 /* MDC (PA2, in, f1) */
  119. 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
  120. 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
  121. 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
  122. 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
  123. 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
  124. 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
  125. 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
  126. 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
  127. >;
  128. };
  129. pio_spi: spi_pin@01 {
  130. pio-map = <
  131. /* port pin dir open_drain assignment has_irq */
  132. 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */
  133. 4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */
  134. 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */
  135. >;
  136. };
  137. pio_brg: brg_pin@0 {
  138. pio-map = <
  139. /* port pin dir open_drain assignment has_irq */
  140. 2 25 1 0 1 0 /* BRG (PC25, out, f1) */
  141. >;
  142. };
  143. pio_tdm: tdm_pin@00 {
  144. pio-map = <
  145. /* port pin dir open_drain assignment has_irq */
  146. /* TDMa */
  147. 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
  148. 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
  149. 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
  150. 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
  151. /* TDMb */
  152. 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
  153. 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
  154. 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
  155. 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
  156. /* TDMc */
  157. 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
  158. 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
  159. 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
  160. 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
  161. /* TDMd */
  162. 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
  163. 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
  164. 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
  165. 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
  166. /* TDMe */
  167. 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
  168. 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
  169. 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
  170. 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
  171. /* TDMf */
  172. 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
  173. 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
  174. 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
  175. 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
  176. /* TDMg */
  177. 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
  178. 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
  179. 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
  180. 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
  181. /* TDMh */
  182. 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
  183. 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
  184. 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
  185. 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
  186. /* RxTxClk0/1 */
  187. 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
  188. 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
  189. /* RxTxSync0/1 */
  190. 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
  191. 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
  192. };
  193. };
  194. &qe {
  195. /* mng-switch port (UCC1, MDIO 0x10, RGMII) */
  196. enet_switch: ethernet@2000 {
  197. device_type = "network";
  198. compatible = "ucc_geth";
  199. cell-index = <1>;
  200. reg = <0x2000 0x200>;
  201. interrupts = <32>;
  202. interrupt-parent = <&qeic>;
  203. local-mac-address = [ 00 00 00 00 00 00 ];
  204. rx-clock-name = "none";
  205. tx-clock-name = "clk9";
  206. /*id=0, full-dup, 1G, no-pause, no-asym_p*/
  207. fixed-link = <0 1 1000 0 0>;
  208. phy-connection-type = "rgmii-id";
  209. pio-handle = <&pio_ucc1>;
  210. };
  211. /* admin and debug port (UCC4, MDIO 0x00, RMII) */
  212. enet_admin: ucc@3200 {
  213. device_type = "network";
  214. compatible = "ucc_geth";
  215. cell-index = <4>;
  216. reg = <0x3200 0x200>;
  217. interrupts = <35>;
  218. interrupt-parent = <&qeic>;
  219. local-mac-address = [ 00 00 00 00 00 00 ];
  220. rx-clock-name = "none";
  221. tx-clock-name = "clk17";
  222. phy-handle = <&phy_admin>;
  223. phy-connection-type = "rmii";
  224. pio-handle = <&pio_ucc4>;
  225. };
  226. /* mate backplane port (UCC5, MDIO 0x08, RMII) */
  227. enet_mate: ucc@2400 {
  228. device_type = "network";
  229. compatible = "ucc_geth";
  230. cell-index = <5>;
  231. reg = <0x2400 0x200>;
  232. interrupts = <40>;
  233. interrupt-parent = <&qeic>;
  234. local-mac-address = [ 00 00 00 00 00 00 ];
  235. rx-clock-name = "none";
  236. tx-clock-name = "clk16";
  237. phy-handle = <&phy_mate>;
  238. phy-connection-type = "rmii";
  239. pio-handle = <&pio_ucc5>;
  240. };
  241. mdio@3320 {
  242. #address-cells = <1>;
  243. #size-cells = <0>;
  244. reg = <0x3320 0x18>;
  245. compatible = "fsl,ucc-mdio";
  246. /* admin front port (UCC4, MDIO 0x00, RMII) */
  247. phy_admin: ethernet-phy@00 {
  248. reg = <0x0>;
  249. };
  250. /* mate bp port (UCC5, MDIO 0x08, RMII) */
  251. phy_mate: ethernet-phy@08 {
  252. reg = <0x08>;
  253. };
  254. };
  255. };
  256. &localbus {
  257. ranges = <0 0 0xf0000000 0x04000000
  258. 1 0 0xe8000000 0x01000000
  259. 3 0 0xa0000000 0x10000000
  260. 4 0 0xb0000000 0x10000000>;
  261. flash@0,0 {
  262. compatible = "cfi-flash";
  263. reg = <0 0 0x04000000>;
  264. nornand = "nor";
  265. #address-cells = <1>;
  266. #size-cells = <1>;
  267. bank-width = <2>;
  268. partition@0 { /* 768KB */
  269. label = "u-boot";
  270. reg = <0 0xC0000>;
  271. };
  272. partition@c0000 { /* 128KB */
  273. label = "env";
  274. reg = <0xC0000 0x20000>;
  275. };
  276. partition@e0000 { /* 128KB */
  277. label = "envred";
  278. reg = <0xE0000 0x20000>;
  279. };
  280. partition@100000 { /* 64512KB */
  281. label = "ubi0";
  282. reg = <0x100000 0x3F00000>;
  283. };
  284. };
  285. };
  286. #include "kmcoge5ne-uboot.dtsi"