km8321.dtsi 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ABB PGGA km8321 common ports Device Tree Source
  4. *
  5. * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
  6. *
  7. */
  8. /dts-v1/;
  9. / {
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. PowerPC,8321@0 {
  14. device_type = "cpu";
  15. reg = <0x0>;
  16. d-cache-line-size = <32>; // 32 bytes
  17. i-cache-line-size = <32>; // 32 bytes
  18. d-cache-size = <16384>; // L1, 16K
  19. i-cache-size = <16384>; // L1, 16K
  20. timebase-frequency = <66000000>;
  21. bus-frequency = <264000000>;
  22. clock-frequency = <528000000>;
  23. };
  24. };
  25. memory {
  26. device_type = "memory";
  27. reg = <0x00000000 0x10000000>;
  28. };
  29. soc: soc8321@e0000000 {
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. device_type = "soc";
  33. compatible = "simple-bus";
  34. ranges = <0x0 0xe0000000 0x00100000>;
  35. reg = <0xe0000000 0x00000200>;
  36. bus-frequency = <264000000>;
  37. i2c0: i2c@3000 {
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. cell-index = <0>;
  41. compatible = "fsl,mpc8313-i2c","fsl-i2c";
  42. reg = <0x3000 0x100>;
  43. interrupts = <14 0x8>;
  44. interrupt-parent = <&ipic>;
  45. clock-frequency = <100000>;
  46. };
  47. serial0: serial@4500 {
  48. cell-index = <0>;
  49. device_type = "serial";
  50. compatible = "fsl,ns16550", "ns16550";
  51. reg = <0x4500 0x100>;
  52. clock-frequency = <264000000>;
  53. interrupts = <9 0x8>;
  54. interrupt-parent = <&ipic>;
  55. };
  56. dma@82a8 {
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
  60. reg = <0x82a8 4>;
  61. ranges = <0 0x8100 0x1a8>;
  62. interrupt-parent = <&ipic>;
  63. interrupts = <71 8>;
  64. cell-index = <0>;
  65. dma-channel@0 {
  66. compatible = "fsl,mpc8321-dma-channel",
  67. "fsl,elo-dma-channel";
  68. reg = <0 0x80>;
  69. interrupt-parent = <&ipic>;
  70. interrupts = <71 8>;
  71. };
  72. dma-channel@80 {
  73. compatible = "fsl,mpc8321-dma-channel",
  74. "fsl,elo-dma-channel";
  75. reg = <0x80 0x80>;
  76. interrupt-parent = <&ipic>;
  77. interrupts = <71 8>;
  78. };
  79. dma-channel@100 {
  80. compatible = "fsl,mpc8321-dma-channel",
  81. "fsl,elo-dma-channel";
  82. reg = <0x100 0x80>;
  83. interrupt-parent = <&ipic>;
  84. interrupts = <71 8>;
  85. };
  86. dma-channel@180 {
  87. compatible = "fsl,mpc8321-dma-channel",
  88. "fsl,elo-dma-channel";
  89. reg = <0x180 0x28>;
  90. interrupt-parent = <&ipic>;
  91. interrupts = <71 8>;
  92. };
  93. };
  94. ipic: pic@700 {
  95. #address-cells = <0>;
  96. #interrupt-cells = <2>;
  97. compatible = "fsl,pq2pro-pic", "fsl,ipic";
  98. interrupt-controller;
  99. reg = <0x700 0x100>;
  100. device_type = "ipic";
  101. };
  102. par_io: par_io@1400 {
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. reg = <0x1400 0x100>;
  106. ranges;
  107. device_type = "par_io";
  108. num-ports = <7>;
  109. qe_pio_d: gpio-controller@48 {
  110. #gpio-cells = <2>;
  111. compatible = "fsl,mpc8360-qe-pario-bank",
  112. "fsl,mpc8323-qe-pario-bank";
  113. reg = <0x1448 0x18>;
  114. gpio-controller;
  115. };
  116. };
  117. };
  118. qe: qe@e0100000 {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. device_type = "qe";
  122. compatible = "fsl,qe";
  123. ranges = <0x0 0xe0100000 0x00100000>;
  124. reg = <0xe0100000 0x480>;
  125. brg-frequency = <0>;
  126. bus-frequency = <396000000>;
  127. muram@10000 {
  128. #address-cells = <1>;
  129. #size-cells = <1>;
  130. compatible = "fsl,qe-muram", "fsl,cpm-muram";
  131. ranges = <0x0 0x00010000 0x00004000>;
  132. data-only@0 {
  133. compatible = "fsl,qe-muram-data",
  134. "fsl,cpm-muram-data";
  135. reg = <0x0 0x4000>;
  136. };
  137. };
  138. /* Piggy2 (UCC4, MDIO 0x00, RMII) */
  139. enet_piggy2: ucc@3200 {
  140. device_type = "network";
  141. compatible = "ucc_geth";
  142. cell-index = <4>;
  143. reg = <0x3200 0x200>;
  144. interrupts = <35>;
  145. interrupt-parent = <&qeic>;
  146. local-mac-address = [ 00 00 00 00 00 00 ];
  147. rx-clock-name = "none";
  148. tx-clock-name = "clk17";
  149. phy-handle = <&phy_piggy2>;
  150. phy-connection-type = "rmii";
  151. pio-handle = <&pio_ucc4>;
  152. };
  153. mdio: mdio@3320 {
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. reg = <0x3320 0x18>;
  157. compatible = "fsl,ucc-mdio";
  158. /* Piggy2 (UCC4, MDIO 0x00, RMII) */
  159. phy_piggy2: ethernet-phy@00 {
  160. reg = <0x0>;
  161. device_type = "ethernet-phy";
  162. };
  163. };
  164. qeic: interrupt-controller@80 {
  165. interrupt-controller;
  166. compatible = "fsl,qe-ic";
  167. #address-cells = <0>;
  168. #interrupt-cells = <1>;
  169. reg = <0x80 0x80>;
  170. big-endian;
  171. interrupts = <32 8 33 8>;
  172. interrupt-parent = <&ipic>;
  173. };
  174. bootcount@0x13ff8 {
  175. device_type = "bootcount";
  176. compatible = "u-boot,bootcount";
  177. reg = <0x13ff8 0x08>;
  178. };
  179. spi0: spi@4c0 {
  180. cell-index = <0>;
  181. compatible = "fsl,spi";
  182. reg = <0x4c0 0x40>;
  183. interrupts = <2>;
  184. interrupt-parent = <&qeic>;
  185. mode = "qe";
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. pio-handle = <&pio_spi>;
  189. };
  190. };
  191. localbus: localbus@e0005000 {
  192. #address-cells = <2>;
  193. #size-cells = <1>;
  194. compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
  195. "simple-bus";
  196. reg = <0xe0005000 0xd8>;
  197. };
  198. };
  199. #include "km8321-uboot.dtsi"