cpu_init.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <watchdog.h>
  9. #include <mpc8xx.h>
  10. #include <asm/cpm_8xx.h>
  11. #include <asm/io.h>
  12. /*
  13. * Breath some life into the CPU...
  14. *
  15. * Set up the memory map,
  16. * initialize a bunch of registers,
  17. * initialize the UPM's
  18. */
  19. void cpu_init_f(immap_t __iomem *immr)
  20. {
  21. memctl8xx_t __iomem *memctl = &immr->im_memctl;
  22. ulong reg;
  23. /* SYPCR - contains watchdog control (11-9) */
  24. #ifndef CONFIG_HW_WATCHDOG
  25. /* deactivate watchdog if not enabled in config */
  26. out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
  27. #endif
  28. WATCHDOG_RESET();
  29. /* SIUMCR - contains debug pin configuration (11-6) */
  30. setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
  31. /* initialize timebase status and control register (11-26) */
  32. /* unlock TBSCRK */
  33. out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
  34. out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR | TBSCR_TBE);
  35. /* Unlock timebase register */
  36. out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY);
  37. /* initialize the PIT (11-31) */
  38. out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
  39. out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
  40. /* System integration timers. Don't change EBDF! (15-27) */
  41. out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
  42. clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
  43. CONFIG_SYS_SCCR);
  44. /*
  45. * MPC866/885 ERRATA GLL2
  46. * Description:
  47. * In 1:2:1 mode, when HRESET is detected at the positive edge of
  48. * EXTCLK, then there will be a loss of phase between
  49. * EXTCLK and CLKOUT.
  50. *
  51. * Workaround:
  52. * Reprogram the SCCR:
  53. * 1. Write 1'b00 to SCCR[EBDF].
  54. * 2. Write 1'b01 to SCCR[EBDF].
  55. * 3. Rewrite the desired value to the PLPRCR register.
  56. */
  57. reg = in_be32(&immr->im_clkrst.car_sccr);
  58. /* Are we in mode 1:2:1 ? */
  59. if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
  60. clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
  61. setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
  62. }
  63. /* PLL (CPU clock) settings (15-30) */
  64. out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
  65. /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
  66. * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
  67. * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
  68. * field value.
  69. *
  70. * For newer (starting MPC866) chips PLPRCR layout is different.
  71. */
  72. #ifdef CONFIG_SYS_PLPRCR
  73. if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
  74. out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
  75. else /* isolate MF-related fields and reset control bits */
  76. clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
  77. CONFIG_SYS_PLPRCR);
  78. #endif
  79. /*
  80. * Memory Controller:
  81. */
  82. /* Clear everything except Port Size bits & add the "Bank Valid" bit */
  83. clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
  84. /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
  85. * preliminary addresses - these have to be modified later
  86. * when FLASH size has been determined
  87. *
  88. * Depending on the size of the memory region defined by
  89. * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
  90. * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
  91. * map CONFIG_SYS_MONITOR_BASE.
  92. *
  93. * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
  94. * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
  95. *
  96. * If BR0 wasn't loaded with address base 0xff000000, then BR0's
  97. * base address remains as 0x00000000. However, the address mask
  98. * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
  99. * into the Bank0.
  100. *
  101. * This is why CONFIG_IVMS8 and similar boards must load BR0 with
  102. * CONFIG_SYS_BR0_PRELIM in advance.
  103. *
  104. * [Thanks to Michael Liao for this explanation.
  105. * I owe him a free beer. - wd]
  106. */
  107. #if defined(CONFIG_SYS_OR0_REMAP)
  108. out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
  109. #endif
  110. #if defined(CONFIG_SYS_OR1_REMAP)
  111. out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
  112. #endif
  113. #if defined(CONFIG_SYS_OR5_REMAP)
  114. out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
  115. #endif
  116. /* now restrict to preliminary range */
  117. out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
  118. out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
  119. #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
  120. out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
  121. out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
  122. #endif
  123. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  124. out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
  125. out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
  126. #endif
  127. #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
  128. out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
  129. out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
  130. #endif
  131. #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
  132. out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
  133. out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
  134. #endif
  135. #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
  136. out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
  137. out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
  138. #endif
  139. #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
  140. out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
  141. out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
  142. #endif
  143. #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
  144. out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
  145. out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
  146. #endif
  147. /*
  148. * Reset CPM
  149. */
  150. out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
  151. /* Spin until command processed */
  152. while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
  153. ;
  154. }
  155. /*
  156. * initialize higher level parts of CPU like timers
  157. */
  158. int cpu_init_r(void)
  159. {
  160. return 0;
  161. }