Kconfig 31 KB

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  1. menu "mpc85xx CPU"
  2. depends on MPC85xx
  3. config SYS_CPU
  4. default "mpc85xx"
  5. config CMD_ERRATA
  6. bool "Enable the 'errata' command"
  7. depends on MPC85xx
  8. default y
  9. help
  10. This enables the 'errata' command which displays a list of errata
  11. work-arounds which are enabled for the current board.
  12. choice
  13. prompt "Target select"
  14. optional
  15. config TARGET_SBC8548
  16. bool "Support sbc8548"
  17. select ARCH_MPC8548
  18. config TARGET_SOCRATES
  19. bool "Support socrates"
  20. select ARCH_MPC8544
  21. config TARGET_P3041DS
  22. bool "Support P3041DS"
  23. select PHYS_64BIT
  24. select ARCH_P3041
  25. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  26. imply CMD_SATA
  27. imply PANIC_HANG
  28. config TARGET_P4080DS
  29. bool "Support P4080DS"
  30. select PHYS_64BIT
  31. select ARCH_P4080
  32. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  33. imply CMD_SATA
  34. imply PANIC_HANG
  35. config TARGET_P5040DS
  36. bool "Support P5040DS"
  37. select PHYS_64BIT
  38. select ARCH_P5040
  39. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  40. imply CMD_SATA
  41. imply PANIC_HANG
  42. config TARGET_MPC8541CDS
  43. bool "Support MPC8541CDS"
  44. select ARCH_MPC8541
  45. config TARGET_MPC8544DS
  46. bool "Support MPC8544DS"
  47. select ARCH_MPC8544
  48. imply PANIC_HANG
  49. config TARGET_MPC8548CDS
  50. bool "Support MPC8548CDS"
  51. select ARCH_MPC8548
  52. config TARGET_MPC8555CDS
  53. bool "Support MPC8555CDS"
  54. select ARCH_MPC8555
  55. config TARGET_MPC8568MDS
  56. bool "Support MPC8568MDS"
  57. select ARCH_MPC8568
  58. config TARGET_MPC8569MDS
  59. bool "Support MPC8569MDS"
  60. select ARCH_MPC8569
  61. config TARGET_MPC8572DS
  62. bool "Support MPC8572DS"
  63. select ARCH_MPC8572
  64. # Use DDR3 controller with DDR2 DIMMs on this board
  65. select SYS_FSL_DDRC_GEN3
  66. imply SCSI
  67. imply PANIC_HANG
  68. config TARGET_P1010RDB_PA
  69. bool "Support P1010RDB_PA"
  70. select ARCH_P1010
  71. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  72. select SUPPORT_SPL
  73. select SUPPORT_TPL
  74. imply CMD_EEPROM
  75. imply CMD_SATA
  76. imply PANIC_HANG
  77. config TARGET_P1010RDB_PB
  78. bool "Support P1010RDB_PB"
  79. select ARCH_P1010
  80. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  81. select SUPPORT_SPL
  82. select SUPPORT_TPL
  83. imply CMD_EEPROM
  84. imply CMD_SATA
  85. imply PANIC_HANG
  86. config TARGET_P1020RDB_PC
  87. bool "Support P1020RDB-PC"
  88. select SUPPORT_SPL
  89. select SUPPORT_TPL
  90. select ARCH_P1020
  91. imply CMD_EEPROM
  92. imply CMD_SATA
  93. imply PANIC_HANG
  94. config TARGET_P1020RDB_PD
  95. bool "Support P1020RDB-PD"
  96. select SUPPORT_SPL
  97. select SUPPORT_TPL
  98. select ARCH_P1020
  99. imply CMD_EEPROM
  100. imply CMD_SATA
  101. imply PANIC_HANG
  102. config TARGET_P2020RDB
  103. bool "Support P2020RDB-PC"
  104. select SUPPORT_SPL
  105. select SUPPORT_TPL
  106. select ARCH_P2020
  107. imply CMD_EEPROM
  108. imply CMD_SATA
  109. imply SATA_SIL
  110. config TARGET_P2041RDB
  111. bool "Support P2041RDB"
  112. select ARCH_P2041
  113. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  114. select PHYS_64BIT
  115. imply CMD_SATA
  116. imply FSL_SATA
  117. config TARGET_QEMU_PPCE500
  118. bool "Support qemu-ppce500"
  119. select ARCH_QEMU_E500
  120. select PHYS_64BIT
  121. config TARGET_T1023RDB
  122. bool "Support T1023RDB"
  123. select ARCH_T1023
  124. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  125. select SUPPORT_SPL
  126. select PHYS_64BIT
  127. select FSL_DDR_INTERACTIVE
  128. imply CMD_EEPROM
  129. imply PANIC_HANG
  130. config TARGET_T1024RDB
  131. bool "Support T1024RDB"
  132. select ARCH_T1024
  133. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  134. select SUPPORT_SPL
  135. select PHYS_64BIT
  136. select FSL_DDR_INTERACTIVE
  137. imply CMD_EEPROM
  138. imply PANIC_HANG
  139. config TARGET_T1040RDB
  140. bool "Support T1040RDB"
  141. select ARCH_T1040
  142. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  143. select SUPPORT_SPL
  144. select PHYS_64BIT
  145. imply CMD_SATA
  146. imply PANIC_HANG
  147. config TARGET_T1040D4RDB
  148. bool "Support T1040D4RDB"
  149. select ARCH_T1040
  150. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  151. select SUPPORT_SPL
  152. select PHYS_64BIT
  153. imply CMD_SATA
  154. imply PANIC_HANG
  155. config TARGET_T1042RDB
  156. bool "Support T1042RDB"
  157. select ARCH_T1042
  158. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  159. select SUPPORT_SPL
  160. select PHYS_64BIT
  161. imply CMD_SATA
  162. config TARGET_T1042D4RDB
  163. bool "Support T1042D4RDB"
  164. select ARCH_T1042
  165. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  166. select SUPPORT_SPL
  167. select PHYS_64BIT
  168. imply CMD_SATA
  169. imply PANIC_HANG
  170. config TARGET_T1042RDB_PI
  171. bool "Support T1042RDB_PI"
  172. select ARCH_T1042
  173. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  174. select SUPPORT_SPL
  175. select PHYS_64BIT
  176. imply CMD_SATA
  177. imply PANIC_HANG
  178. config TARGET_T2080QDS
  179. bool "Support T2080QDS"
  180. select ARCH_T2080
  181. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  182. select SUPPORT_SPL
  183. select PHYS_64BIT
  184. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  185. select FSL_DDR_INTERACTIVE
  186. imply CMD_SATA
  187. config TARGET_T2080RDB
  188. bool "Support T2080RDB"
  189. select ARCH_T2080
  190. select BOARD_LATE_INIT if CHAIN_OF_TRUST
  191. select SUPPORT_SPL
  192. select PHYS_64BIT
  193. imply CMD_SATA
  194. imply PANIC_HANG
  195. config TARGET_T2081QDS
  196. bool "Support T2081QDS"
  197. select ARCH_T2081
  198. select SUPPORT_SPL
  199. select PHYS_64BIT
  200. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  201. select FSL_DDR_INTERACTIVE
  202. config TARGET_T4160RDB
  203. bool "Support T4160RDB"
  204. select ARCH_T4160
  205. select SUPPORT_SPL
  206. select PHYS_64BIT
  207. imply PANIC_HANG
  208. config TARGET_T4240RDB
  209. bool "Support T4240RDB"
  210. select ARCH_T4240
  211. select SUPPORT_SPL
  212. select PHYS_64BIT
  213. select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  214. imply CMD_SATA
  215. imply PANIC_HANG
  216. config TARGET_CONTROLCENTERD
  217. bool "Support controlcenterd"
  218. select ARCH_P1022
  219. config TARGET_KMP204X
  220. bool "Support kmp204x"
  221. select VENDOR_KM
  222. config TARGET_XPEDITE520X
  223. bool "Support xpedite520x"
  224. select ARCH_MPC8548
  225. config TARGET_XPEDITE537X
  226. bool "Support xpedite537x"
  227. select ARCH_MPC8572
  228. # Use DDR3 controller with DDR2 DIMMs on this board
  229. select SYS_FSL_DDRC_GEN3
  230. config TARGET_XPEDITE550X
  231. bool "Support xpedite550x"
  232. select ARCH_P2020
  233. config TARGET_UCP1020
  234. bool "Support uCP1020"
  235. select ARCH_P1020
  236. imply CMD_SATA
  237. imply PANIC_HANG
  238. config TARGET_CYRUS_P5020
  239. bool "Support Varisys Cyrus P5020"
  240. select ARCH_P5020
  241. select PHYS_64BIT
  242. imply PANIC_HANG
  243. config TARGET_CYRUS_P5040
  244. bool "Support Varisys Cyrus P5040"
  245. select ARCH_P5040
  246. select PHYS_64BIT
  247. imply PANIC_HANG
  248. endchoice
  249. config ARCH_B4420
  250. bool
  251. select E500MC
  252. select E6500
  253. select FSL_LAW
  254. select SYS_FSL_DDR_VER_47
  255. select SYS_FSL_ERRATUM_A004477
  256. select SYS_FSL_ERRATUM_A005871
  257. select SYS_FSL_ERRATUM_A006379
  258. select SYS_FSL_ERRATUM_A006384
  259. select SYS_FSL_ERRATUM_A006475
  260. select SYS_FSL_ERRATUM_A006593
  261. select SYS_FSL_ERRATUM_A007075
  262. select SYS_FSL_ERRATUM_A007186
  263. select SYS_FSL_ERRATUM_A007212
  264. select SYS_FSL_ERRATUM_A009942
  265. select SYS_FSL_HAS_DDR3
  266. select SYS_FSL_HAS_SEC
  267. select SYS_FSL_QORIQ_CHASSIS2
  268. select SYS_FSL_SEC_BE
  269. select SYS_FSL_SEC_COMPAT_4
  270. select SYS_PPC64
  271. select FSL_IFC
  272. imply CMD_EEPROM
  273. imply CMD_NAND
  274. imply CMD_REGINFO
  275. config ARCH_B4860
  276. bool
  277. select E500MC
  278. select E6500
  279. select FSL_LAW
  280. select SYS_FSL_DDR_VER_47
  281. select SYS_FSL_ERRATUM_A004477
  282. select SYS_FSL_ERRATUM_A005871
  283. select SYS_FSL_ERRATUM_A006379
  284. select SYS_FSL_ERRATUM_A006384
  285. select SYS_FSL_ERRATUM_A006475
  286. select SYS_FSL_ERRATUM_A006593
  287. select SYS_FSL_ERRATUM_A007075
  288. select SYS_FSL_ERRATUM_A007186
  289. select SYS_FSL_ERRATUM_A007212
  290. select SYS_FSL_ERRATUM_A007907
  291. select SYS_FSL_ERRATUM_A009942
  292. select SYS_FSL_HAS_DDR3
  293. select SYS_FSL_HAS_SEC
  294. select SYS_FSL_QORIQ_CHASSIS2
  295. select SYS_FSL_SEC_BE
  296. select SYS_FSL_SEC_COMPAT_4
  297. select SYS_PPC64
  298. select FSL_IFC
  299. imply CMD_EEPROM
  300. imply CMD_NAND
  301. imply CMD_REGINFO
  302. config ARCH_BSC9131
  303. bool
  304. select FSL_LAW
  305. select SYS_FSL_DDR_VER_44
  306. select SYS_FSL_ERRATUM_A004477
  307. select SYS_FSL_ERRATUM_A005125
  308. select SYS_FSL_ERRATUM_ESDHC111
  309. select SYS_FSL_HAS_DDR3
  310. select SYS_FSL_HAS_SEC
  311. select SYS_FSL_SEC_BE
  312. select SYS_FSL_SEC_COMPAT_4
  313. select FSL_IFC
  314. imply CMD_EEPROM
  315. imply CMD_NAND
  316. imply CMD_REGINFO
  317. config ARCH_BSC9132
  318. bool
  319. select FSL_LAW
  320. select SYS_FSL_DDR_VER_46
  321. select SYS_FSL_ERRATUM_A004477
  322. select SYS_FSL_ERRATUM_A005125
  323. select SYS_FSL_ERRATUM_A005434
  324. select SYS_FSL_ERRATUM_ESDHC111
  325. select SYS_FSL_ERRATUM_I2C_A004447
  326. select SYS_FSL_ERRATUM_IFC_A002769
  327. select FSL_PCIE_RESET
  328. select SYS_FSL_HAS_DDR3
  329. select SYS_FSL_HAS_SEC
  330. select SYS_FSL_SEC_BE
  331. select SYS_FSL_SEC_COMPAT_4
  332. select SYS_PPC_E500_USE_DEBUG_TLB
  333. select FSL_IFC
  334. imply CMD_EEPROM
  335. imply CMD_MTDPARTS
  336. imply CMD_NAND
  337. imply CMD_PCI
  338. imply CMD_REGINFO
  339. config ARCH_C29X
  340. bool
  341. select FSL_LAW
  342. select SYS_FSL_DDR_VER_46
  343. select SYS_FSL_ERRATUM_A005125
  344. select SYS_FSL_ERRATUM_ESDHC111
  345. select FSL_PCIE_RESET
  346. select SYS_FSL_HAS_DDR3
  347. select SYS_FSL_HAS_SEC
  348. select SYS_FSL_SEC_BE
  349. select SYS_FSL_SEC_COMPAT_6
  350. select SYS_PPC_E500_USE_DEBUG_TLB
  351. select FSL_IFC
  352. imply CMD_NAND
  353. imply CMD_PCI
  354. imply CMD_REGINFO
  355. config ARCH_MPC8536
  356. bool
  357. select FSL_LAW
  358. select SYS_FSL_ERRATUM_A004508
  359. select SYS_FSL_ERRATUM_A005125
  360. select FSL_PCIE_RESET
  361. select SYS_FSL_HAS_DDR2
  362. select SYS_FSL_HAS_DDR3
  363. select SYS_FSL_HAS_SEC
  364. select SYS_FSL_SEC_BE
  365. select SYS_FSL_SEC_COMPAT_2
  366. select SYS_PPC_E500_USE_DEBUG_TLB
  367. select FSL_ELBC
  368. imply CMD_NAND
  369. imply CMD_SATA
  370. imply CMD_REGINFO
  371. config ARCH_MPC8540
  372. bool
  373. select FSL_LAW
  374. select SYS_FSL_HAS_DDR1
  375. config ARCH_MPC8541
  376. bool
  377. select FSL_LAW
  378. select SYS_FSL_HAS_DDR1
  379. select SYS_FSL_HAS_SEC
  380. select SYS_FSL_SEC_BE
  381. select SYS_FSL_SEC_COMPAT_2
  382. config ARCH_MPC8544
  383. bool
  384. select FSL_LAW
  385. select SYS_FSL_ERRATUM_A005125
  386. select FSL_PCIE_RESET
  387. select SYS_FSL_HAS_DDR2
  388. select SYS_FSL_HAS_SEC
  389. select SYS_FSL_SEC_BE
  390. select SYS_FSL_SEC_COMPAT_2
  391. select SYS_PPC_E500_USE_DEBUG_TLB
  392. select FSL_ELBC
  393. config ARCH_MPC8548
  394. bool
  395. select FSL_LAW
  396. select SYS_FSL_ERRATUM_A005125
  397. select SYS_FSL_ERRATUM_NMG_DDR120
  398. select SYS_FSL_ERRATUM_NMG_LBC103
  399. select SYS_FSL_ERRATUM_NMG_ETSEC129
  400. select SYS_FSL_ERRATUM_I2C_A004447
  401. select FSL_PCIE_RESET
  402. select SYS_FSL_HAS_DDR2
  403. select SYS_FSL_HAS_DDR1
  404. select SYS_FSL_HAS_SEC
  405. select SYS_FSL_SEC_BE
  406. select SYS_FSL_SEC_COMPAT_2
  407. select SYS_PPC_E500_USE_DEBUG_TLB
  408. imply CMD_REGINFO
  409. config ARCH_MPC8555
  410. bool
  411. select FSL_LAW
  412. select SYS_FSL_HAS_DDR1
  413. select SYS_FSL_HAS_SEC
  414. select SYS_FSL_SEC_BE
  415. select SYS_FSL_SEC_COMPAT_2
  416. config ARCH_MPC8560
  417. bool
  418. select FSL_LAW
  419. select SYS_FSL_HAS_DDR1
  420. config ARCH_MPC8568
  421. bool
  422. select FSL_LAW
  423. select FSL_PCIE_RESET
  424. select SYS_FSL_HAS_DDR2
  425. select SYS_FSL_HAS_SEC
  426. select SYS_FSL_SEC_BE
  427. select SYS_FSL_SEC_COMPAT_2
  428. config ARCH_MPC8569
  429. bool
  430. select FSL_LAW
  431. select SYS_FSL_ERRATUM_A004508
  432. select SYS_FSL_ERRATUM_A005125
  433. select FSL_PCIE_RESET
  434. select SYS_FSL_HAS_DDR3
  435. select SYS_FSL_HAS_SEC
  436. select SYS_FSL_SEC_BE
  437. select SYS_FSL_SEC_COMPAT_2
  438. select FSL_ELBC
  439. imply CMD_NAND
  440. config ARCH_MPC8572
  441. bool
  442. select FSL_LAW
  443. select SYS_FSL_ERRATUM_A004508
  444. select SYS_FSL_ERRATUM_A005125
  445. select SYS_FSL_ERRATUM_DDR_115
  446. select SYS_FSL_ERRATUM_DDR111_DDR134
  447. select FSL_PCIE_RESET
  448. select SYS_FSL_HAS_DDR2
  449. select SYS_FSL_HAS_DDR3
  450. select SYS_FSL_HAS_SEC
  451. select SYS_FSL_SEC_BE
  452. select SYS_FSL_SEC_COMPAT_2
  453. select SYS_PPC_E500_USE_DEBUG_TLB
  454. select FSL_ELBC
  455. imply CMD_NAND
  456. config ARCH_P1010
  457. bool
  458. select FSL_LAW
  459. select SYS_FSL_ERRATUM_A004477
  460. select SYS_FSL_ERRATUM_A004508
  461. select SYS_FSL_ERRATUM_A005125
  462. select SYS_FSL_ERRATUM_A005275
  463. select SYS_FSL_ERRATUM_A006261
  464. select SYS_FSL_ERRATUM_A007075
  465. select SYS_FSL_ERRATUM_ESDHC111
  466. select SYS_FSL_ERRATUM_I2C_A004447
  467. select SYS_FSL_ERRATUM_IFC_A002769
  468. select SYS_FSL_ERRATUM_P1010_A003549
  469. select SYS_FSL_ERRATUM_SEC_A003571
  470. select SYS_FSL_ERRATUM_IFC_A003399
  471. select FSL_PCIE_RESET
  472. select SYS_FSL_HAS_DDR3
  473. select SYS_FSL_HAS_SEC
  474. select SYS_FSL_SEC_BE
  475. select SYS_FSL_SEC_COMPAT_4
  476. select SYS_PPC_E500_USE_DEBUG_TLB
  477. select FSL_IFC
  478. imply CMD_EEPROM
  479. imply CMD_MTDPARTS
  480. imply CMD_NAND
  481. imply CMD_SATA
  482. imply CMD_PCI
  483. imply CMD_REGINFO
  484. imply FSL_SATA
  485. config ARCH_P1011
  486. bool
  487. select FSL_LAW
  488. select SYS_FSL_ERRATUM_A004508
  489. select SYS_FSL_ERRATUM_A005125
  490. select SYS_FSL_ERRATUM_ELBC_A001
  491. select SYS_FSL_ERRATUM_ESDHC111
  492. select FSL_PCIE_DISABLE_ASPM
  493. select SYS_FSL_HAS_DDR3
  494. select SYS_FSL_HAS_SEC
  495. select SYS_FSL_SEC_BE
  496. select SYS_FSL_SEC_COMPAT_2
  497. select SYS_PPC_E500_USE_DEBUG_TLB
  498. select FSL_ELBC
  499. config ARCH_P1020
  500. bool
  501. select FSL_LAW
  502. select SYS_FSL_ERRATUM_A004508
  503. select SYS_FSL_ERRATUM_A005125
  504. select SYS_FSL_ERRATUM_ELBC_A001
  505. select SYS_FSL_ERRATUM_ESDHC111
  506. select FSL_PCIE_DISABLE_ASPM
  507. select FSL_PCIE_RESET
  508. select SYS_FSL_HAS_DDR3
  509. select SYS_FSL_HAS_SEC
  510. select SYS_FSL_SEC_BE
  511. select SYS_FSL_SEC_COMPAT_2
  512. select SYS_PPC_E500_USE_DEBUG_TLB
  513. select FSL_ELBC
  514. imply CMD_NAND
  515. imply CMD_SATA
  516. imply CMD_PCI
  517. imply CMD_REGINFO
  518. imply SATA_SIL
  519. config ARCH_P1021
  520. bool
  521. select FSL_LAW
  522. select SYS_FSL_ERRATUM_A004508
  523. select SYS_FSL_ERRATUM_A005125
  524. select SYS_FSL_ERRATUM_ELBC_A001
  525. select SYS_FSL_ERRATUM_ESDHC111
  526. select FSL_PCIE_DISABLE_ASPM
  527. select FSL_PCIE_RESET
  528. select SYS_FSL_HAS_DDR3
  529. select SYS_FSL_HAS_SEC
  530. select SYS_FSL_SEC_BE
  531. select SYS_FSL_SEC_COMPAT_2
  532. select SYS_PPC_E500_USE_DEBUG_TLB
  533. select FSL_ELBC
  534. imply CMD_REGINFO
  535. imply CMD_NAND
  536. imply CMD_SATA
  537. imply CMD_REGINFO
  538. imply SATA_SIL
  539. config ARCH_P1022
  540. bool
  541. select FSL_LAW
  542. select SYS_FSL_ERRATUM_A004477
  543. select SYS_FSL_ERRATUM_A004508
  544. select SYS_FSL_ERRATUM_A005125
  545. select SYS_FSL_ERRATUM_ELBC_A001
  546. select SYS_FSL_ERRATUM_ESDHC111
  547. select SYS_FSL_ERRATUM_SATA_A001
  548. select FSL_PCIE_RESET
  549. select SYS_FSL_HAS_DDR3
  550. select SYS_FSL_HAS_SEC
  551. select SYS_FSL_SEC_BE
  552. select SYS_FSL_SEC_COMPAT_2
  553. select SYS_PPC_E500_USE_DEBUG_TLB
  554. select FSL_ELBC
  555. config ARCH_P1023
  556. bool
  557. select FSL_LAW
  558. select SYS_FSL_ERRATUM_A004508
  559. select SYS_FSL_ERRATUM_A005125
  560. select SYS_FSL_ERRATUM_I2C_A004447
  561. select FSL_PCIE_RESET
  562. select SYS_FSL_HAS_DDR3
  563. select SYS_FSL_HAS_SEC
  564. select SYS_FSL_SEC_BE
  565. select SYS_FSL_SEC_COMPAT_4
  566. select FSL_ELBC
  567. config ARCH_P1024
  568. bool
  569. select FSL_LAW
  570. select SYS_FSL_ERRATUM_A004508
  571. select SYS_FSL_ERRATUM_A005125
  572. select SYS_FSL_ERRATUM_ELBC_A001
  573. select SYS_FSL_ERRATUM_ESDHC111
  574. select FSL_PCIE_DISABLE_ASPM
  575. select FSL_PCIE_RESET
  576. select SYS_FSL_HAS_DDR3
  577. select SYS_FSL_HAS_SEC
  578. select SYS_FSL_SEC_BE
  579. select SYS_FSL_SEC_COMPAT_2
  580. select SYS_PPC_E500_USE_DEBUG_TLB
  581. select FSL_ELBC
  582. imply CMD_EEPROM
  583. imply CMD_NAND
  584. imply CMD_SATA
  585. imply CMD_PCI
  586. imply CMD_REGINFO
  587. imply SATA_SIL
  588. config ARCH_P1025
  589. bool
  590. select FSL_LAW
  591. select SYS_FSL_ERRATUM_A004508
  592. select SYS_FSL_ERRATUM_A005125
  593. select SYS_FSL_ERRATUM_ELBC_A001
  594. select SYS_FSL_ERRATUM_ESDHC111
  595. select FSL_PCIE_DISABLE_ASPM
  596. select FSL_PCIE_RESET
  597. select SYS_FSL_HAS_DDR3
  598. select SYS_FSL_HAS_SEC
  599. select SYS_FSL_SEC_BE
  600. select SYS_FSL_SEC_COMPAT_2
  601. select SYS_PPC_E500_USE_DEBUG_TLB
  602. select FSL_ELBC
  603. imply CMD_SATA
  604. imply CMD_REGINFO
  605. config ARCH_P2020
  606. bool
  607. select FSL_LAW
  608. select SYS_FSL_ERRATUM_A004477
  609. select SYS_FSL_ERRATUM_A004508
  610. select SYS_FSL_ERRATUM_A005125
  611. select SYS_FSL_ERRATUM_ESDHC111
  612. select SYS_FSL_ERRATUM_ESDHC_A001
  613. select FSL_PCIE_RESET
  614. select SYS_FSL_HAS_DDR3
  615. select SYS_FSL_HAS_SEC
  616. select SYS_FSL_SEC_BE
  617. select SYS_FSL_SEC_COMPAT_2
  618. select SYS_PPC_E500_USE_DEBUG_TLB
  619. select FSL_ELBC
  620. imply CMD_EEPROM
  621. imply CMD_NAND
  622. imply CMD_REGINFO
  623. config ARCH_P2041
  624. bool
  625. select E500MC
  626. select FSL_LAW
  627. select SYS_FSL_ERRATUM_A004510
  628. select SYS_FSL_ERRATUM_A004849
  629. select SYS_FSL_ERRATUM_A005275
  630. select SYS_FSL_ERRATUM_A006261
  631. select SYS_FSL_ERRATUM_CPU_A003999
  632. select SYS_FSL_ERRATUM_DDR_A003
  633. select SYS_FSL_ERRATUM_DDR_A003474
  634. select SYS_FSL_ERRATUM_ESDHC111
  635. select SYS_FSL_ERRATUM_I2C_A004447
  636. select SYS_FSL_ERRATUM_NMG_CPU_A011
  637. select SYS_FSL_ERRATUM_SRIO_A004034
  638. select SYS_FSL_ERRATUM_USB14
  639. select SYS_FSL_HAS_DDR3
  640. select SYS_FSL_HAS_SEC
  641. select SYS_FSL_QORIQ_CHASSIS1
  642. select SYS_FSL_SEC_BE
  643. select SYS_FSL_SEC_COMPAT_4
  644. select FSL_ELBC
  645. imply CMD_NAND
  646. config ARCH_P3041
  647. bool
  648. select E500MC
  649. select FSL_LAW
  650. select SYS_FSL_DDR_VER_44
  651. select SYS_FSL_ERRATUM_A004510
  652. select SYS_FSL_ERRATUM_A004849
  653. select SYS_FSL_ERRATUM_A005275
  654. select SYS_FSL_ERRATUM_A005812
  655. select SYS_FSL_ERRATUM_A006261
  656. select SYS_FSL_ERRATUM_CPU_A003999
  657. select SYS_FSL_ERRATUM_DDR_A003
  658. select SYS_FSL_ERRATUM_DDR_A003474
  659. select SYS_FSL_ERRATUM_ESDHC111
  660. select SYS_FSL_ERRATUM_I2C_A004447
  661. select SYS_FSL_ERRATUM_NMG_CPU_A011
  662. select SYS_FSL_ERRATUM_SRIO_A004034
  663. select SYS_FSL_ERRATUM_USB14
  664. select SYS_FSL_HAS_DDR3
  665. select SYS_FSL_HAS_SEC
  666. select SYS_FSL_QORIQ_CHASSIS1
  667. select SYS_FSL_SEC_BE
  668. select SYS_FSL_SEC_COMPAT_4
  669. select FSL_ELBC
  670. imply CMD_NAND
  671. imply CMD_SATA
  672. imply CMD_REGINFO
  673. imply FSL_SATA
  674. config ARCH_P4080
  675. bool
  676. select E500MC
  677. select FSL_LAW
  678. select SYS_FSL_DDR_VER_44
  679. select SYS_FSL_ERRATUM_A004510
  680. select SYS_FSL_ERRATUM_A004580
  681. select SYS_FSL_ERRATUM_A004849
  682. select SYS_FSL_ERRATUM_A005812
  683. select SYS_FSL_ERRATUM_A007075
  684. select SYS_FSL_ERRATUM_CPC_A002
  685. select SYS_FSL_ERRATUM_CPC_A003
  686. select SYS_FSL_ERRATUM_CPU_A003999
  687. select SYS_FSL_ERRATUM_DDR_A003
  688. select SYS_FSL_ERRATUM_DDR_A003474
  689. select SYS_FSL_ERRATUM_ELBC_A001
  690. select SYS_FSL_ERRATUM_ESDHC111
  691. select SYS_FSL_ERRATUM_ESDHC13
  692. select SYS_FSL_ERRATUM_ESDHC135
  693. select SYS_FSL_ERRATUM_I2C_A004447
  694. select SYS_FSL_ERRATUM_NMG_CPU_A011
  695. select SYS_FSL_ERRATUM_SRIO_A004034
  696. select SYS_P4080_ERRATUM_CPU22
  697. select SYS_P4080_ERRATUM_PCIE_A003
  698. select SYS_P4080_ERRATUM_SERDES8
  699. select SYS_P4080_ERRATUM_SERDES9
  700. select SYS_P4080_ERRATUM_SERDES_A001
  701. select SYS_P4080_ERRATUM_SERDES_A005
  702. select SYS_FSL_HAS_DDR3
  703. select SYS_FSL_HAS_SEC
  704. select SYS_FSL_QORIQ_CHASSIS1
  705. select SYS_FSL_SEC_BE
  706. select SYS_FSL_SEC_COMPAT_4
  707. select FSL_ELBC
  708. imply CMD_SATA
  709. imply CMD_REGINFO
  710. imply SATA_SIL
  711. config ARCH_P5020
  712. bool
  713. select E500MC
  714. select FSL_LAW
  715. select SYS_FSL_DDR_VER_44
  716. select SYS_FSL_ERRATUM_A004510
  717. select SYS_FSL_ERRATUM_A005275
  718. select SYS_FSL_ERRATUM_A006261
  719. select SYS_FSL_ERRATUM_DDR_A003
  720. select SYS_FSL_ERRATUM_DDR_A003474
  721. select SYS_FSL_ERRATUM_ESDHC111
  722. select SYS_FSL_ERRATUM_I2C_A004447
  723. select SYS_FSL_ERRATUM_SRIO_A004034
  724. select SYS_FSL_ERRATUM_USB14
  725. select SYS_FSL_HAS_DDR3
  726. select SYS_FSL_HAS_SEC
  727. select SYS_FSL_QORIQ_CHASSIS1
  728. select SYS_FSL_SEC_BE
  729. select SYS_FSL_SEC_COMPAT_4
  730. select SYS_PPC64
  731. select FSL_ELBC
  732. imply CMD_SATA
  733. imply CMD_REGINFO
  734. imply FSL_SATA
  735. config ARCH_P5040
  736. bool
  737. select E500MC
  738. select FSL_LAW
  739. select SYS_FSL_DDR_VER_44
  740. select SYS_FSL_ERRATUM_A004510
  741. select SYS_FSL_ERRATUM_A004699
  742. select SYS_FSL_ERRATUM_A005275
  743. select SYS_FSL_ERRATUM_A005812
  744. select SYS_FSL_ERRATUM_A006261
  745. select SYS_FSL_ERRATUM_DDR_A003
  746. select SYS_FSL_ERRATUM_DDR_A003474
  747. select SYS_FSL_ERRATUM_ESDHC111
  748. select SYS_FSL_ERRATUM_USB14
  749. select SYS_FSL_HAS_DDR3
  750. select SYS_FSL_HAS_SEC
  751. select SYS_FSL_QORIQ_CHASSIS1
  752. select SYS_FSL_SEC_BE
  753. select SYS_FSL_SEC_COMPAT_4
  754. select SYS_PPC64
  755. select FSL_ELBC
  756. imply CMD_SATA
  757. imply CMD_REGINFO
  758. imply FSL_SATA
  759. config ARCH_QEMU_E500
  760. bool
  761. config ARCH_T1023
  762. bool
  763. select E500MC
  764. select FSL_LAW
  765. select SYS_FSL_DDR_VER_50
  766. select SYS_FSL_ERRATUM_A008378
  767. select SYS_FSL_ERRATUM_A008109
  768. select SYS_FSL_ERRATUM_A009663
  769. select SYS_FSL_ERRATUM_A009942
  770. select SYS_FSL_ERRATUM_ESDHC111
  771. select SYS_FSL_HAS_DDR3
  772. select SYS_FSL_HAS_DDR4
  773. select SYS_FSL_HAS_SEC
  774. select SYS_FSL_QORIQ_CHASSIS2
  775. select SYS_FSL_SEC_BE
  776. select SYS_FSL_SEC_COMPAT_5
  777. select FSL_IFC
  778. imply CMD_EEPROM
  779. imply CMD_NAND
  780. imply CMD_REGINFO
  781. config ARCH_T1024
  782. bool
  783. select E500MC
  784. select FSL_LAW
  785. select SYS_FSL_DDR_VER_50
  786. select SYS_FSL_ERRATUM_A008378
  787. select SYS_FSL_ERRATUM_A008109
  788. select SYS_FSL_ERRATUM_A009663
  789. select SYS_FSL_ERRATUM_A009942
  790. select SYS_FSL_ERRATUM_ESDHC111
  791. select SYS_FSL_HAS_DDR3
  792. select SYS_FSL_HAS_DDR4
  793. select SYS_FSL_HAS_SEC
  794. select SYS_FSL_QORIQ_CHASSIS2
  795. select SYS_FSL_SEC_BE
  796. select SYS_FSL_SEC_COMPAT_5
  797. select FSL_IFC
  798. imply CMD_EEPROM
  799. imply CMD_NAND
  800. imply CMD_MTDPARTS
  801. imply CMD_REGINFO
  802. config ARCH_T1040
  803. bool
  804. select E500MC
  805. select FSL_LAW
  806. select SYS_FSL_DDR_VER_50
  807. select SYS_FSL_ERRATUM_A008044
  808. select SYS_FSL_ERRATUM_A008378
  809. select SYS_FSL_ERRATUM_A008109
  810. select SYS_FSL_ERRATUM_A009663
  811. select SYS_FSL_ERRATUM_A009942
  812. select SYS_FSL_ERRATUM_ESDHC111
  813. select SYS_FSL_HAS_DDR3
  814. select SYS_FSL_HAS_DDR4
  815. select SYS_FSL_HAS_SEC
  816. select SYS_FSL_QORIQ_CHASSIS2
  817. select SYS_FSL_SEC_BE
  818. select SYS_FSL_SEC_COMPAT_5
  819. select FSL_IFC
  820. imply CMD_MTDPARTS
  821. imply CMD_NAND
  822. imply CMD_SATA
  823. imply CMD_REGINFO
  824. imply FSL_SATA
  825. config ARCH_T1042
  826. bool
  827. select E500MC
  828. select FSL_LAW
  829. select SYS_FSL_DDR_VER_50
  830. select SYS_FSL_ERRATUM_A008044
  831. select SYS_FSL_ERRATUM_A008378
  832. select SYS_FSL_ERRATUM_A008109
  833. select SYS_FSL_ERRATUM_A009663
  834. select SYS_FSL_ERRATUM_A009942
  835. select SYS_FSL_ERRATUM_ESDHC111
  836. select SYS_FSL_HAS_DDR3
  837. select SYS_FSL_HAS_DDR4
  838. select SYS_FSL_HAS_SEC
  839. select SYS_FSL_QORIQ_CHASSIS2
  840. select SYS_FSL_SEC_BE
  841. select SYS_FSL_SEC_COMPAT_5
  842. select FSL_IFC
  843. imply CMD_MTDPARTS
  844. imply CMD_NAND
  845. imply CMD_SATA
  846. imply CMD_REGINFO
  847. imply FSL_SATA
  848. config ARCH_T2080
  849. bool
  850. select E500MC
  851. select E6500
  852. select FSL_LAW
  853. select SYS_FSL_DDR_VER_47
  854. select SYS_FSL_ERRATUM_A006379
  855. select SYS_FSL_ERRATUM_A006593
  856. select SYS_FSL_ERRATUM_A007186
  857. select SYS_FSL_ERRATUM_A007212
  858. select SYS_FSL_ERRATUM_A007815
  859. select SYS_FSL_ERRATUM_A007907
  860. select SYS_FSL_ERRATUM_A008109
  861. select SYS_FSL_ERRATUM_A009942
  862. select SYS_FSL_ERRATUM_ESDHC111
  863. select FSL_PCIE_RESET
  864. select SYS_FSL_HAS_DDR3
  865. select SYS_FSL_HAS_SEC
  866. select SYS_FSL_QORIQ_CHASSIS2
  867. select SYS_FSL_SEC_BE
  868. select SYS_FSL_SEC_COMPAT_4
  869. select SYS_PPC64
  870. select FSL_IFC
  871. imply CMD_SATA
  872. imply CMD_NAND
  873. imply CMD_REGINFO
  874. imply FSL_SATA
  875. config ARCH_T2081
  876. bool
  877. select E500MC
  878. select E6500
  879. select FSL_LAW
  880. select SYS_FSL_DDR_VER_47
  881. select SYS_FSL_ERRATUM_A006379
  882. select SYS_FSL_ERRATUM_A006593
  883. select SYS_FSL_ERRATUM_A007186
  884. select SYS_FSL_ERRATUM_A007212
  885. select SYS_FSL_ERRATUM_A009942
  886. select SYS_FSL_ERRATUM_ESDHC111
  887. select FSL_PCIE_RESET
  888. select SYS_FSL_HAS_DDR3
  889. select SYS_FSL_HAS_SEC
  890. select SYS_FSL_QORIQ_CHASSIS2
  891. select SYS_FSL_SEC_BE
  892. select SYS_FSL_SEC_COMPAT_4
  893. select SYS_PPC64
  894. select FSL_IFC
  895. imply CMD_NAND
  896. imply CMD_REGINFO
  897. config ARCH_T4160
  898. bool
  899. select E500MC
  900. select E6500
  901. select FSL_LAW
  902. select SYS_FSL_DDR_VER_47
  903. select SYS_FSL_ERRATUM_A004468
  904. select SYS_FSL_ERRATUM_A005871
  905. select SYS_FSL_ERRATUM_A006379
  906. select SYS_FSL_ERRATUM_A006593
  907. select SYS_FSL_ERRATUM_A007186
  908. select SYS_FSL_ERRATUM_A007798
  909. select SYS_FSL_ERRATUM_A009942
  910. select SYS_FSL_HAS_DDR3
  911. select SYS_FSL_HAS_SEC
  912. select SYS_FSL_QORIQ_CHASSIS2
  913. select SYS_FSL_SEC_BE
  914. select SYS_FSL_SEC_COMPAT_4
  915. select SYS_PPC64
  916. select FSL_IFC
  917. imply CMD_SATA
  918. imply CMD_NAND
  919. imply CMD_REGINFO
  920. imply FSL_SATA
  921. config ARCH_T4240
  922. bool
  923. select E500MC
  924. select E6500
  925. select FSL_LAW
  926. select SYS_FSL_DDR_VER_47
  927. select SYS_FSL_ERRATUM_A004468
  928. select SYS_FSL_ERRATUM_A005871
  929. select SYS_FSL_ERRATUM_A006261
  930. select SYS_FSL_ERRATUM_A006379
  931. select SYS_FSL_ERRATUM_A006593
  932. select SYS_FSL_ERRATUM_A007186
  933. select SYS_FSL_ERRATUM_A007798
  934. select SYS_FSL_ERRATUM_A007815
  935. select SYS_FSL_ERRATUM_A007907
  936. select SYS_FSL_ERRATUM_A008109
  937. select SYS_FSL_ERRATUM_A009942
  938. select SYS_FSL_HAS_DDR3
  939. select SYS_FSL_HAS_SEC
  940. select SYS_FSL_QORIQ_CHASSIS2
  941. select SYS_FSL_SEC_BE
  942. select SYS_FSL_SEC_COMPAT_4
  943. select SYS_PPC64
  944. select FSL_IFC
  945. imply CMD_SATA
  946. imply CMD_NAND
  947. imply CMD_REGINFO
  948. imply FSL_SATA
  949. config MPC85XX_HAVE_RESET_VECTOR
  950. bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
  951. depends on MPC85xx
  952. config BOOKE
  953. bool
  954. default y
  955. config E500
  956. bool
  957. default y
  958. help
  959. Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
  960. config E500MC
  961. bool
  962. imply CMD_PCI
  963. help
  964. Enble PowerPC E500MC core
  965. config E6500
  966. bool
  967. help
  968. Enable PowerPC E6500 core
  969. config FSL_LAW
  970. bool
  971. help
  972. Use Freescale common code for Local Access Window
  973. config NXP_ESBC
  974. bool "NXP_ESBC"
  975. help
  976. Enable Freescale Secure Boot feature. Normally selected
  977. by defconfig. If unsure, do not change.
  978. config MAX_CPUS
  979. int "Maximum number of CPUs permitted for MPC85xx"
  980. default 12 if ARCH_T4240
  981. default 8 if ARCH_P4080 || \
  982. ARCH_T4160
  983. default 4 if ARCH_B4860 || \
  984. ARCH_P2041 || \
  985. ARCH_P3041 || \
  986. ARCH_P5040 || \
  987. ARCH_T1040 || \
  988. ARCH_T1042 || \
  989. ARCH_T2080 || \
  990. ARCH_T2081
  991. default 2 if ARCH_B4420 || \
  992. ARCH_BSC9132 || \
  993. ARCH_MPC8572 || \
  994. ARCH_P1020 || \
  995. ARCH_P1021 || \
  996. ARCH_P1022 || \
  997. ARCH_P1023 || \
  998. ARCH_P1024 || \
  999. ARCH_P1025 || \
  1000. ARCH_P2020 || \
  1001. ARCH_P5020 || \
  1002. ARCH_T1023 || \
  1003. ARCH_T1024
  1004. default 1
  1005. help
  1006. Set this number to the maximum number of possible CPUs in the SoC.
  1007. SoCs may have multiple clusters with each cluster may have multiple
  1008. ports. If some ports are reserved but higher ports are used for
  1009. cores, count the reserved ports. This will allocate enough memory
  1010. in spin table to properly handle all cores.
  1011. config SYS_CCSRBAR_DEFAULT
  1012. hex "Default CCSRBAR address"
  1013. default 0xff700000 if ARCH_BSC9131 || \
  1014. ARCH_BSC9132 || \
  1015. ARCH_C29X || \
  1016. ARCH_MPC8536 || \
  1017. ARCH_MPC8540 || \
  1018. ARCH_MPC8541 || \
  1019. ARCH_MPC8544 || \
  1020. ARCH_MPC8548 || \
  1021. ARCH_MPC8555 || \
  1022. ARCH_MPC8560 || \
  1023. ARCH_MPC8568 || \
  1024. ARCH_MPC8569 || \
  1025. ARCH_MPC8572 || \
  1026. ARCH_P1010 || \
  1027. ARCH_P1011 || \
  1028. ARCH_P1020 || \
  1029. ARCH_P1021 || \
  1030. ARCH_P1022 || \
  1031. ARCH_P1024 || \
  1032. ARCH_P1025 || \
  1033. ARCH_P2020
  1034. default 0xff600000 if ARCH_P1023
  1035. default 0xfe000000 if ARCH_B4420 || \
  1036. ARCH_B4860 || \
  1037. ARCH_P2041 || \
  1038. ARCH_P3041 || \
  1039. ARCH_P4080 || \
  1040. ARCH_P5020 || \
  1041. ARCH_P5040 || \
  1042. ARCH_T1023 || \
  1043. ARCH_T1024 || \
  1044. ARCH_T1040 || \
  1045. ARCH_T1042 || \
  1046. ARCH_T2080 || \
  1047. ARCH_T2081 || \
  1048. ARCH_T4160 || \
  1049. ARCH_T4240
  1050. default 0xe0000000 if ARCH_QEMU_E500
  1051. help
  1052. Default value of CCSRBAR comes from power-on-reset. It
  1053. is fixed on each SoC. Some SoCs can have different value
  1054. if changed by pre-boot regime. The value here must match
  1055. the current value in SoC. If not sure, do not change.
  1056. config SYS_FSL_ERRATUM_A004468
  1057. bool
  1058. config SYS_FSL_ERRATUM_A004477
  1059. bool
  1060. config SYS_FSL_ERRATUM_A004508
  1061. bool
  1062. config SYS_FSL_ERRATUM_A004580
  1063. bool
  1064. config SYS_FSL_ERRATUM_A004699
  1065. bool
  1066. config SYS_FSL_ERRATUM_A004849
  1067. bool
  1068. config SYS_FSL_ERRATUM_A004510
  1069. bool
  1070. config SYS_FSL_ERRATUM_A004510_SVR_REV
  1071. hex
  1072. depends on SYS_FSL_ERRATUM_A004510
  1073. default 0x20 if ARCH_P4080
  1074. default 0x10
  1075. config SYS_FSL_ERRATUM_A004510_SVR_REV2
  1076. hex
  1077. depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
  1078. default 0x11
  1079. config SYS_FSL_ERRATUM_A005125
  1080. bool
  1081. config SYS_FSL_ERRATUM_A005434
  1082. bool
  1083. config SYS_FSL_ERRATUM_A005812
  1084. bool
  1085. config SYS_FSL_ERRATUM_A005871
  1086. bool
  1087. config SYS_FSL_ERRATUM_A005275
  1088. bool
  1089. config SYS_FSL_ERRATUM_A006261
  1090. bool
  1091. config SYS_FSL_ERRATUM_A006379
  1092. bool
  1093. config SYS_FSL_ERRATUM_A006384
  1094. bool
  1095. config SYS_FSL_ERRATUM_A006475
  1096. bool
  1097. config SYS_FSL_ERRATUM_A006593
  1098. bool
  1099. config SYS_FSL_ERRATUM_A007075
  1100. bool
  1101. config SYS_FSL_ERRATUM_A007186
  1102. bool
  1103. config SYS_FSL_ERRATUM_A007212
  1104. bool
  1105. config SYS_FSL_ERRATUM_A007815
  1106. bool
  1107. config SYS_FSL_ERRATUM_A007798
  1108. bool
  1109. config SYS_FSL_ERRATUM_A007907
  1110. bool
  1111. config SYS_FSL_ERRATUM_A008044
  1112. bool
  1113. config SYS_FSL_ERRATUM_CPC_A002
  1114. bool
  1115. config SYS_FSL_ERRATUM_CPC_A003
  1116. bool
  1117. config SYS_FSL_ERRATUM_CPU_A003999
  1118. bool
  1119. config SYS_FSL_ERRATUM_ELBC_A001
  1120. bool
  1121. config SYS_FSL_ERRATUM_I2C_A004447
  1122. bool
  1123. config SYS_FSL_A004447_SVR_REV
  1124. hex
  1125. depends on SYS_FSL_ERRATUM_I2C_A004447
  1126. default 0x00 if ARCH_MPC8548
  1127. default 0x10 if ARCH_P1010
  1128. default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
  1129. default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020
  1130. config SYS_FSL_ERRATUM_IFC_A002769
  1131. bool
  1132. config SYS_FSL_ERRATUM_IFC_A003399
  1133. bool
  1134. config SYS_FSL_ERRATUM_NMG_CPU_A011
  1135. bool
  1136. config SYS_FSL_ERRATUM_NMG_ETSEC129
  1137. bool
  1138. config SYS_FSL_ERRATUM_NMG_LBC103
  1139. bool
  1140. config SYS_FSL_ERRATUM_P1010_A003549
  1141. bool
  1142. config SYS_FSL_ERRATUM_SATA_A001
  1143. bool
  1144. config SYS_FSL_ERRATUM_SEC_A003571
  1145. bool
  1146. config SYS_FSL_ERRATUM_SRIO_A004034
  1147. bool
  1148. config SYS_FSL_ERRATUM_USB14
  1149. bool
  1150. config SYS_P4080_ERRATUM_CPU22
  1151. bool
  1152. config SYS_P4080_ERRATUM_PCIE_A003
  1153. bool
  1154. config SYS_P4080_ERRATUM_SERDES8
  1155. bool
  1156. config SYS_P4080_ERRATUM_SERDES9
  1157. bool
  1158. config SYS_P4080_ERRATUM_SERDES_A001
  1159. bool
  1160. config SYS_P4080_ERRATUM_SERDES_A005
  1161. bool
  1162. config FSL_PCIE_DISABLE_ASPM
  1163. bool
  1164. config FSL_PCIE_RESET
  1165. bool
  1166. config SYS_FSL_QORIQ_CHASSIS1
  1167. bool
  1168. config SYS_FSL_QORIQ_CHASSIS2
  1169. bool
  1170. config SYS_FSL_NUM_LAWS
  1171. int "Number of local access windows"
  1172. depends on FSL_LAW
  1173. default 32 if ARCH_B4420 || \
  1174. ARCH_B4860 || \
  1175. ARCH_P2041 || \
  1176. ARCH_P3041 || \
  1177. ARCH_P4080 || \
  1178. ARCH_P5020 || \
  1179. ARCH_P5040 || \
  1180. ARCH_T2080 || \
  1181. ARCH_T2081 || \
  1182. ARCH_T4160 || \
  1183. ARCH_T4240
  1184. default 16 if ARCH_T1023 || \
  1185. ARCH_T1024 || \
  1186. ARCH_T1040 || \
  1187. ARCH_T1042
  1188. default 12 if ARCH_BSC9131 || \
  1189. ARCH_BSC9132 || \
  1190. ARCH_C29X || \
  1191. ARCH_MPC8536 || \
  1192. ARCH_MPC8572 || \
  1193. ARCH_P1010 || \
  1194. ARCH_P1011 || \
  1195. ARCH_P1020 || \
  1196. ARCH_P1021 || \
  1197. ARCH_P1022 || \
  1198. ARCH_P1023 || \
  1199. ARCH_P1024 || \
  1200. ARCH_P1025 || \
  1201. ARCH_P2020
  1202. default 10 if ARCH_MPC8544 || \
  1203. ARCH_MPC8548 || \
  1204. ARCH_MPC8568 || \
  1205. ARCH_MPC8569
  1206. default 8 if ARCH_MPC8540 || \
  1207. ARCH_MPC8541 || \
  1208. ARCH_MPC8555 || \
  1209. ARCH_MPC8560
  1210. help
  1211. Number of local access windows. This is fixed per SoC.
  1212. If not sure, do not change.
  1213. config SYS_FSL_THREADS_PER_CORE
  1214. int
  1215. default 2 if E6500
  1216. default 1
  1217. config SYS_NUM_TLBCAMS
  1218. int "Number of TLB CAM entries"
  1219. default 64 if E500MC
  1220. default 16
  1221. help
  1222. Number of TLB CAM entries for Book-E chips. 64 for E500MC,
  1223. 16 for other E500 SoCs.
  1224. config SYS_PPC64
  1225. bool
  1226. config SYS_PPC_E500_USE_DEBUG_TLB
  1227. bool
  1228. config FSL_IFC
  1229. bool
  1230. config FSL_ELBC
  1231. bool
  1232. config SYS_PPC_E500_DEBUG_TLB
  1233. int "Temporary TLB entry for external debugger"
  1234. depends on SYS_PPC_E500_USE_DEBUG_TLB
  1235. default 0 if ARCH_MPC8544 || ARCH_MPC8548
  1236. default 1 if ARCH_MPC8536
  1237. default 2 if ARCH_MPC8572 || \
  1238. ARCH_P1011 || \
  1239. ARCH_P1020 || \
  1240. ARCH_P1021 || \
  1241. ARCH_P1022 || \
  1242. ARCH_P1024 || \
  1243. ARCH_P1025 || \
  1244. ARCH_P2020
  1245. default 3 if ARCH_P1010 || \
  1246. ARCH_BSC9132 || \
  1247. ARCH_C29X
  1248. help
  1249. Select a temporary TLB entry to be used during boot to work
  1250. around limitations in e500v1 and e500v2 external debugger
  1251. support. This reduces the portions of the boot code where
  1252. breakpoints and single stepping do not work. The value of this
  1253. symbol should be set to the TLB1 entry to be used for this
  1254. purpose. If unsure, do not change.
  1255. config SYS_FSL_IFC_CLK_DIV
  1256. int "Divider of platform clock"
  1257. depends on FSL_IFC
  1258. default 2 if ARCH_B4420 || \
  1259. ARCH_B4860 || \
  1260. ARCH_T1024 || \
  1261. ARCH_T1023 || \
  1262. ARCH_T1040 || \
  1263. ARCH_T1042 || \
  1264. ARCH_T4160 || \
  1265. ARCH_T4240
  1266. default 1
  1267. help
  1268. Defines divider of platform clock(clock input to
  1269. IFC controller).
  1270. config SYS_FSL_LBC_CLK_DIV
  1271. int "Divider of platform clock"
  1272. depends on FSL_ELBC || ARCH_MPC8540 || \
  1273. ARCH_MPC8548 || ARCH_MPC8541 || \
  1274. ARCH_MPC8555 || ARCH_MPC8560 || \
  1275. ARCH_MPC8568
  1276. default 2 if ARCH_P2041 || \
  1277. ARCH_P3041 || \
  1278. ARCH_P4080 || \
  1279. ARCH_P5020 || \
  1280. ARCH_P5040
  1281. default 1
  1282. help
  1283. Defines divider of platform clock(clock input to
  1284. eLBC controller).
  1285. source "board/freescale/corenet_ds/Kconfig"
  1286. source "board/freescale/mpc8541cds/Kconfig"
  1287. source "board/freescale/mpc8544ds/Kconfig"
  1288. source "board/freescale/mpc8548cds/Kconfig"
  1289. source "board/freescale/mpc8555cds/Kconfig"
  1290. source "board/freescale/mpc8568mds/Kconfig"
  1291. source "board/freescale/mpc8569mds/Kconfig"
  1292. source "board/freescale/mpc8572ds/Kconfig"
  1293. source "board/freescale/p1010rdb/Kconfig"
  1294. source "board/freescale/p1_p2_rdb_pc/Kconfig"
  1295. source "board/freescale/p2041rdb/Kconfig"
  1296. source "board/freescale/qemu-ppce500/Kconfig"
  1297. source "board/freescale/t102xrdb/Kconfig"
  1298. source "board/freescale/t104xrdb/Kconfig"
  1299. source "board/freescale/t208xqds/Kconfig"
  1300. source "board/freescale/t208xrdb/Kconfig"
  1301. source "board/freescale/t4rdb/Kconfig"
  1302. source "board/gdsys/p1022/Kconfig"
  1303. source "board/keymile/Kconfig"
  1304. source "board/sbc8548/Kconfig"
  1305. source "board/socrates/Kconfig"
  1306. source "board/varisys/cyrus/Kconfig"
  1307. source "board/xes/xpedite520x/Kconfig"
  1308. source "board/xes/xpedite537x/Kconfig"
  1309. source "board/xes/xpedite550x/Kconfig"
  1310. source "board/Arcturus/ucp1020/Kconfig"
  1311. endmenu