qe_io.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #include <common.h>
  9. #include <linux/errno.h>
  10. #include <asm/io.h>
  11. #include <asm/immap_83xx.h>
  12. #define NUM_OF_PINS 32
  13. /** qe_cfg_iopin configure one io pin setting
  14. *
  15. * @par_io: pointer to parallel I/O base
  16. * @port: io pin port
  17. * @pin: io pin number which get configured
  18. * @dir: direction of io pin 2 bits valid
  19. * 00 = pin disabled
  20. * 01 = output
  21. * 10 = input
  22. * 11 = pin is I/O
  23. * @open_drain: is pin open drain
  24. * @assign: pin assignment registers select the function of the pin
  25. */
  26. static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
  27. int open_drain, int assign)
  28. {
  29. u32 dbit_mask;
  30. u32 dbit_dir;
  31. u32 dbit_asgn;
  32. u32 bit_mask;
  33. u32 tmp_val;
  34. int offset;
  35. offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
  36. /* Calculate pin location and 2bit mask and dir */
  37. dbit_mask = (u32)(0x3 << offset);
  38. dbit_dir = (u32)(dir << offset);
  39. /* Setup the direction */
  40. tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
  41. in_be32(&par_io->ioport[port].dir2) :
  42. in_be32(&par_io->ioport[port].dir1);
  43. if (pin > (NUM_OF_PINS / 2) - 1) {
  44. out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
  45. out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
  46. } else {
  47. out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
  48. out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
  49. }
  50. /* Calculate pin location for 1bit mask */
  51. bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
  52. /* Setup the open drain */
  53. tmp_val = in_be32(&par_io->ioport[port].podr);
  54. if (open_drain)
  55. out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
  56. else
  57. out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
  58. /* Setup the assignment */
  59. tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
  60. in_be32(&par_io->ioport[port].ppar2) :
  61. in_be32(&par_io->ioport[port].ppar1);
  62. dbit_asgn = (u32)(assign << offset);
  63. /* Clear and set 2 bits mask */
  64. if (pin > (NUM_OF_PINS / 2) - 1) {
  65. out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
  66. out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
  67. } else {
  68. out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
  69. out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
  70. }
  71. }
  72. #if !defined(CONFIG_PINCTRL)
  73. /** qe_config_iopin configure one io pin setting
  74. *
  75. * @port: io pin port
  76. * @pin: io pin number which get configured
  77. * @dir: direction of io pin 2 bits valid
  78. * 00 = pin disabled
  79. * 01 = output
  80. * 10 = input
  81. * 11 = pin is I/O
  82. * @open_drain: is pin open drain
  83. * @assign: pin assignment registers select the function of the pin
  84. */
  85. void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
  86. {
  87. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  88. qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
  89. qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
  90. }
  91. #endif