cpu_init.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm-offsets.h>
  7. #include <mpc83xx.h>
  8. #include <ioports.h>
  9. #include <asm/io.h>
  10. #include <asm/processor.h>
  11. #include <fsl_qe.h>
  12. #ifdef CONFIG_USB_EHCI_FSL
  13. #include <usb/ehci-ci.h>
  14. #endif
  15. #include <linux/delay.h>
  16. #ifdef CONFIG_QE
  17. #include <fsl_qe.h>
  18. #endif
  19. #include "lblaw/lblaw.h"
  20. #include "elbc/elbc.h"
  21. #include "sysio/sysio.h"
  22. #include "arbiter/arbiter.h"
  23. #include "initreg/initreg.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifdef CONFIG_QE
  26. extern qe_iop_conf_t qe_iop_conf_tab[];
  27. extern void qe_config_iopin(u8 port, u8 pin, int dir,
  28. int open_drain, int assign);
  29. #if !defined(CONFIG_PINCTRL)
  30. static void config_qe_ioports(void)
  31. {
  32. u8 port, pin;
  33. int dir, open_drain, assign;
  34. int i;
  35. for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  36. port = qe_iop_conf_tab[i].port;
  37. pin = qe_iop_conf_tab[i].pin;
  38. dir = qe_iop_conf_tab[i].dir;
  39. open_drain = qe_iop_conf_tab[i].open_drain;
  40. assign = qe_iop_conf_tab[i].assign;
  41. qe_config_iopin(port, pin, dir, open_drain, assign);
  42. }
  43. }
  44. #endif
  45. #endif
  46. /*
  47. * Breathe some life into the CPU...
  48. *
  49. * Set up the memory map,
  50. * initialize a bunch of registers,
  51. * initialize the UPM's
  52. */
  53. void cpu_init_f (volatile immap_t * im)
  54. {
  55. __be32 sccr_mask =
  56. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  57. SCCR_ENCCM |
  58. #endif
  59. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  60. SCCR_PCICM |
  61. #endif
  62. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  63. SCCR_PCIEXP1CM |
  64. #endif
  65. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  66. SCCR_PCIEXP2CM |
  67. #endif
  68. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  69. SCCR_TSECCM |
  70. #endif
  71. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  72. SCCR_TSEC1CM |
  73. #endif
  74. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  75. SCCR_TSEC2CM |
  76. #endif
  77. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  78. SCCR_TSEC1ON |
  79. #endif
  80. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  81. SCCR_TSEC2ON |
  82. #endif
  83. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  84. SCCR_USBMPHCM |
  85. #endif
  86. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  87. SCCR_USBDRCM |
  88. #endif
  89. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  90. SCCR_SATACM |
  91. #endif
  92. 0;
  93. __be32 sccr_val =
  94. #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  95. (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
  96. #endif
  97. #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  98. (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
  99. #endif
  100. #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
  101. (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
  102. #endif
  103. #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
  104. (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
  105. #endif
  106. #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  107. (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
  108. #endif
  109. #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  110. (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
  111. #endif
  112. #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  113. (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
  114. #endif
  115. #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  116. (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
  117. #endif
  118. #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  119. (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
  120. #endif
  121. #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  122. (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
  123. #endif
  124. #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  125. (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
  126. #endif
  127. #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  128. (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
  129. #endif
  130. 0;
  131. /* Pointer is writable since we allocated a register for it */
  132. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  133. /* global data region was cleared in start.S */
  134. /* system performance tweaking */
  135. clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
  136. clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
  137. clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
  138. /* RSR - Reset Status Register - clear all status (4.6.1.3) */
  139. gd->arch.reset_status = __raw_readl(&im->reset.rsr);
  140. __raw_writel(~(RSR_RES), &im->reset.rsr);
  141. /* AER - Arbiter Event Register - store status */
  142. gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
  143. gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
  144. /*
  145. * RMR - Reset Mode Register
  146. * contains checkstop reset enable (4.6.1.4)
  147. */
  148. __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
  149. /* LCRR - Clock Ratio Register (10.3.1.16)
  150. * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
  151. */
  152. clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
  153. __raw_readl(&im->im_lbc.lcrr);
  154. isync();
  155. /* Enable Time Base & Decrementer ( so we will have udelay() )*/
  156. setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
  157. /* System General Purpose Register */
  158. #ifdef CONFIG_SYS_SICRH
  159. #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
  160. /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
  161. __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
  162. &im->sysconf.sicrh);
  163. #else
  164. __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
  165. #endif
  166. #endif
  167. #ifdef CONFIG_SYS_SICRL
  168. __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
  169. #endif
  170. #ifdef CONFIG_SYS_GPR1
  171. __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
  172. #endif
  173. #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
  174. __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
  175. #endif
  176. #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
  177. __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
  178. #endif
  179. #if !defined(CONFIG_PINCTRL)
  180. #ifdef CONFIG_QE
  181. /* Config QE ioports */
  182. config_qe_ioports();
  183. #endif
  184. #endif
  185. /* Set up preliminary BR/OR regs */
  186. init_early_memctl_regs();
  187. /* Local Access window setup */
  188. #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
  189. im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
  190. im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
  191. #else
  192. #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
  193. #endif
  194. #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
  195. im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
  196. im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
  197. #endif
  198. #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
  199. im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
  200. im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
  201. #endif
  202. #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
  203. im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
  204. im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
  205. #endif
  206. #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
  207. im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
  208. im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
  209. #endif
  210. #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
  211. im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
  212. im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
  213. #endif
  214. #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
  215. im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
  216. im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
  217. #endif
  218. #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
  219. im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
  220. im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
  221. #endif
  222. #ifdef CONFIG_SYS_GPIO1_PRELIM
  223. im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
  224. im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
  225. #endif
  226. #ifdef CONFIG_SYS_GPIO2_PRELIM
  227. im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
  228. im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
  229. #endif
  230. #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
  231. uint32_t temp;
  232. struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
  233. /* Configure interface. */
  234. setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
  235. /* Wait for clock to stabilize */
  236. do {
  237. temp = __raw_readl(&ehci->control);
  238. udelay(1000);
  239. } while (!(temp & PHY_CLK_VALID));
  240. #endif
  241. }
  242. int cpu_init_r (void)
  243. {
  244. #ifdef CONFIG_QE
  245. uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
  246. qe_init(qe_base);
  247. qe_reset();
  248. #endif
  249. return 0;
  250. }
  251. /*
  252. * Print out the bus arbiter event
  253. */
  254. #if defined(CONFIG_DISPLAY_AER_FULL)
  255. static int print_83xx_arb_event(int force)
  256. {
  257. static char* event[] = {
  258. "Address Time Out",
  259. "Data Time Out",
  260. "Address Only Transfer Type",
  261. "External Control Word Transfer Type",
  262. "Reserved Transfer Type",
  263. "Transfer Error",
  264. "reserved",
  265. "reserved"
  266. };
  267. static char* master[] = {
  268. "e300 Core Data Transaction",
  269. "reserved",
  270. "e300 Core Instruction Fetch",
  271. "reserved",
  272. "TSEC1",
  273. "TSEC2",
  274. "USB MPH",
  275. "USB DR",
  276. "Encryption Core",
  277. "I2C Boot Sequencer",
  278. "JTAG",
  279. "reserved",
  280. "eSDHC",
  281. "PCI1",
  282. "PCI2",
  283. "DMA",
  284. "QUICC Engine 00",
  285. "QUICC Engine 01",
  286. "QUICC Engine 10",
  287. "QUICC Engine 11",
  288. "reserved",
  289. "reserved",
  290. "reserved",
  291. "reserved",
  292. "SATA1",
  293. "SATA2",
  294. "SATA3",
  295. "SATA4",
  296. "reserved",
  297. "PCI Express 1",
  298. "PCI Express 2",
  299. "TDM-DMAC"
  300. };
  301. static char *transfer[] = {
  302. "Address-only, Clean Block",
  303. "Address-only, lwarx reservation set",
  304. "Single-beat or Burst write",
  305. "reserved",
  306. "Address-only, Flush Block",
  307. "reserved",
  308. "Burst write",
  309. "reserved",
  310. "Address-only, sync",
  311. "Address-only, tlbsync",
  312. "Single-beat or Burst read",
  313. "Single-beat or Burst read",
  314. "Address-only, Kill Block",
  315. "Address-only, icbi",
  316. "Burst read",
  317. "reserved",
  318. "Address-only, eieio",
  319. "reserved",
  320. "Single-beat write",
  321. "reserved",
  322. "ecowx - Illegal single-beat write",
  323. "reserved",
  324. "reserved",
  325. "reserved",
  326. "Address-only, TLB Invalidate",
  327. "reserved",
  328. "Single-beat or Burst read",
  329. "reserved",
  330. "eciwx - Illegal single-beat read",
  331. "reserved",
  332. "Burst read",
  333. "reserved"
  334. };
  335. int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
  336. >> AEATR_EVENT_SHIFT;
  337. int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
  338. >> AEATR_MSTR_ID_SHIFT;
  339. int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
  340. >> AEATR_TBST_SHIFT;
  341. int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
  342. >> AEATR_TSIZE_SHIFT;
  343. int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
  344. >> AEATR_TTYPE_SHIFT;
  345. if (!force && !gd->arch.arbiter_event_address)
  346. return 0;
  347. puts("Arbiter Event Status:\n");
  348. printf(" Event Address: 0x%08lX\n",
  349. gd->arch.arbiter_event_address);
  350. printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
  351. printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
  352. printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
  353. tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
  354. printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
  355. return gd->arch.arbiter_event_address;
  356. }
  357. #elif defined(CONFIG_DISPLAY_AER_BRIEF)
  358. static int print_83xx_arb_event(int force)
  359. {
  360. if (!force && !gd->arch.arbiter_event_address)
  361. return 0;
  362. printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
  363. gd->arch.arbiter_event_attributes,
  364. gd->arch.arbiter_event_address);
  365. return gd->arch.arbiter_event_address;
  366. }
  367. #endif /* CONFIG_DISPLAY_AER_xxxx */
  368. #ifndef CONFIG_CPU_MPC83XX
  369. /*
  370. * Figure out the cause of the reset
  371. */
  372. int prt_83xx_rsr(void)
  373. {
  374. static struct {
  375. ulong mask;
  376. char *desc;
  377. } bits[] = {
  378. {
  379. RSR_SWSR, "Software Soft"}, {
  380. RSR_SWHR, "Software Hard"}, {
  381. RSR_JSRS, "JTAG Soft"}, {
  382. RSR_CSHR, "Check Stop"}, {
  383. RSR_SWRS, "Software Watchdog"}, {
  384. RSR_BMRS, "Bus Monitor"}, {
  385. RSR_SRS, "External/Internal Soft"}, {
  386. RSR_HRS, "External/Internal Hard"}
  387. };
  388. static int n = ARRAY_SIZE(bits);
  389. ulong rsr = gd->arch.reset_status;
  390. int i;
  391. char *sep;
  392. puts("Reset Status:");
  393. sep = " ";
  394. for (i = 0; i < n; i++)
  395. if (rsr & bits[i].mask) {
  396. printf("%s%s", sep, bits[i].desc);
  397. sep = ", ";
  398. }
  399. puts("\n");
  400. #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
  401. print_83xx_arb_event(rsr & RSR_BMRS);
  402. #endif
  403. puts("\n");
  404. return 0;
  405. }
  406. #endif