cache.h 578 B

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. */
  5. #ifndef __MICROBLAZE_CACHE_H__
  6. #define __MICROBLAZE_CACHE_H__
  7. /*
  8. * The microblaze can have either a 4 or 16 byte cacheline depending on whether
  9. * you are using OPB(4) or CacheLink(16). If the board config has not specified
  10. * a cacheline size we assume the larger value of 16 bytes for DMA buffer
  11. * alignment.
  12. */
  13. #ifdef CONFIG_SYS_CACHELINE_SIZE
  14. #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
  15. #else
  16. #define ARCH_DMA_MINALIGN 16
  17. #endif
  18. #endif /* __MICROBLAZE_CACHE_H__ */