mp.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <log.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/io.h>
  12. #include <linux/delay.h>
  13. #define LOCK 0
  14. #define SPLIT 1
  15. #define HALT 0
  16. #define RELEASE 1
  17. #define ZYNQMP_BOOTADDR_HIGH_MASK 0xFFFFFFFF
  18. #define ZYNQMP_R5_HIVEC_ADDR 0xFFFF0000
  19. #define ZYNQMP_R5_LOVEC_ADDR 0x0
  20. #define ZYNQMP_RPU_CFG_CPU_HALT_MASK 0x01
  21. #define ZYNQMP_RPU_CFG_HIVEC_MASK 0x04
  22. #define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK 0x08
  23. #define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK 0x40
  24. #define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK 0x10
  25. #define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK 0x04
  26. #define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK 0x01
  27. #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02
  28. #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000
  29. #define ZYNQMP_TCM_START_ADDRESS 0xFFE00000
  30. #define ZYNQMP_TCM_BOTH_SIZE 0x40000
  31. #define ZYNQMP_CORE_APU0 0
  32. #define ZYNQMP_CORE_APU3 3
  33. #define ZYNQMP_MAX_CORES 6
  34. int is_core_valid(unsigned int core)
  35. {
  36. if (core < ZYNQMP_MAX_CORES)
  37. return 1;
  38. return 0;
  39. }
  40. int cpu_reset(u32 nr)
  41. {
  42. puts("Feature is not implemented.\n");
  43. return 0;
  44. }
  45. static void set_r5_halt_mode(u8 halt, u8 mode)
  46. {
  47. u32 tmp;
  48. tmp = readl(&rpu_base->rpu0_cfg);
  49. if (halt == HALT)
  50. tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  51. else
  52. tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  53. writel(tmp, &rpu_base->rpu0_cfg);
  54. if (mode == LOCK) {
  55. tmp = readl(&rpu_base->rpu1_cfg);
  56. if (halt == HALT)
  57. tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  58. else
  59. tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  60. writel(tmp, &rpu_base->rpu1_cfg);
  61. }
  62. }
  63. static void set_r5_tcm_mode(u8 mode)
  64. {
  65. u32 tmp;
  66. tmp = readl(&rpu_base->rpu_glbl_ctrl);
  67. if (mode == LOCK) {
  68. tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  69. tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  70. ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
  71. } else {
  72. tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  73. tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  74. ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
  75. }
  76. writel(tmp, &rpu_base->rpu_glbl_ctrl);
  77. }
  78. static void set_r5_reset(u8 mode)
  79. {
  80. u32 tmp;
  81. tmp = readl(&crlapb_base->rst_lpd_top);
  82. tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
  83. ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
  84. if (mode == LOCK)
  85. tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
  86. writel(tmp, &crlapb_base->rst_lpd_top);
  87. }
  88. static void release_r5_reset(u8 mode)
  89. {
  90. u32 tmp;
  91. tmp = readl(&crlapb_base->rst_lpd_top);
  92. tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
  93. ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
  94. if (mode == LOCK)
  95. tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
  96. writel(tmp, &crlapb_base->rst_lpd_top);
  97. }
  98. static void enable_clock_r5(void)
  99. {
  100. u32 tmp;
  101. tmp = readl(&crlapb_base->cpu_r5_ctrl);
  102. tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
  103. writel(tmp, &crlapb_base->cpu_r5_ctrl);
  104. /* Give some delay for clock
  105. * to propagate */
  106. udelay(0x500);
  107. }
  108. int cpu_disable(u32 nr)
  109. {
  110. if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
  111. u32 val = readl(&crfapb_base->rst_fpd_apu);
  112. val |= 1 << nr;
  113. writel(val, &crfapb_base->rst_fpd_apu);
  114. } else {
  115. set_r5_reset(LOCK);
  116. }
  117. return 0;
  118. }
  119. int cpu_status(u32 nr)
  120. {
  121. if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
  122. u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
  123. u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
  124. nr * 8);
  125. u32 val = readl(&crfapb_base->rst_fpd_apu);
  126. val &= 1 << nr;
  127. printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
  128. nr, val ? "OFF" : "ON" , addr_high, addr_low);
  129. } else {
  130. u32 val = readl(&crlapb_base->rst_lpd_top);
  131. val &= 1 << (nr - 4);
  132. printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
  133. }
  134. return 0;
  135. }
  136. static void set_r5_start(u8 high)
  137. {
  138. u32 tmp;
  139. tmp = readl(&rpu_base->rpu0_cfg);
  140. if (high)
  141. tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
  142. else
  143. tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
  144. writel(tmp, &rpu_base->rpu0_cfg);
  145. tmp = readl(&rpu_base->rpu1_cfg);
  146. if (high)
  147. tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
  148. else
  149. tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
  150. writel(tmp, &rpu_base->rpu1_cfg);
  151. }
  152. static void write_tcm_boot_trampoline(u32 boot_addr)
  153. {
  154. if (boot_addr) {
  155. /*
  156. * Boot trampoline is simple ASM code below.
  157. *
  158. * b over;
  159. * label:
  160. * .word 0
  161. * over: ldr r0, =label
  162. * ldr r1, [r0]
  163. * bx r1
  164. */
  165. debug("Write boot trampoline for %x\n", boot_addr);
  166. writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
  167. writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
  168. writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
  169. writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
  170. writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
  171. writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
  172. }
  173. }
  174. void initialize_tcm(bool mode)
  175. {
  176. if (!mode) {
  177. set_r5_tcm_mode(LOCK);
  178. set_r5_halt_mode(HALT, LOCK);
  179. enable_clock_r5();
  180. release_r5_reset(LOCK);
  181. } else {
  182. set_r5_tcm_mode(SPLIT);
  183. set_r5_halt_mode(HALT, SPLIT);
  184. enable_clock_r5();
  185. release_r5_reset(SPLIT);
  186. }
  187. }
  188. int cpu_release(u32 nr, int argc, char *const argv[])
  189. {
  190. if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
  191. u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
  192. /* HIGH */
  193. writel((u32)(boot_addr >> 32),
  194. ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
  195. /* LOW */
  196. writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
  197. ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
  198. u32 val = readl(&crfapb_base->rst_fpd_apu);
  199. val &= ~(1 << nr);
  200. writel(val, &crfapb_base->rst_fpd_apu);
  201. } else {
  202. if (argc != 2) {
  203. printf("Invalid number of arguments to release.\n");
  204. printf("<addr> <mode>-Start addr lockstep or split\n");
  205. return 1;
  206. }
  207. u32 boot_addr = simple_strtoul(argv[0], NULL, 16);
  208. u32 boot_addr_uniq = 0;
  209. if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
  210. boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
  211. printf("Using TCM jump trampoline for address 0x%x\n",
  212. boot_addr);
  213. /* Save boot address for later usage */
  214. boot_addr_uniq = boot_addr;
  215. /*
  216. * R5 needs to start from LOVEC at TCM
  217. * OCM will be probably occupied by ATF
  218. */
  219. boot_addr = ZYNQMP_R5_LOVEC_ADDR;
  220. }
  221. /*
  222. * Since we don't know where the user may have loaded the image
  223. * for an R5 we have to flush all the data cache to ensure
  224. * the R5 sees it.
  225. */
  226. flush_dcache_all();
  227. if (!strncmp(argv[1], "lockstep", 8)) {
  228. printf("R5 lockstep mode\n");
  229. set_r5_reset(LOCK);
  230. set_r5_tcm_mode(LOCK);
  231. set_r5_halt_mode(HALT, LOCK);
  232. set_r5_start(boot_addr);
  233. enable_clock_r5();
  234. release_r5_reset(LOCK);
  235. dcache_disable();
  236. write_tcm_boot_trampoline(boot_addr_uniq);
  237. dcache_enable();
  238. set_r5_halt_mode(RELEASE, LOCK);
  239. } else if (!strncmp(argv[1], "split", 5)) {
  240. printf("R5 split mode\n");
  241. set_r5_reset(SPLIT);
  242. set_r5_tcm_mode(SPLIT);
  243. set_r5_halt_mode(HALT, SPLIT);
  244. set_r5_start(boot_addr);
  245. enable_clock_r5();
  246. release_r5_reset(SPLIT);
  247. dcache_disable();
  248. write_tcm_boot_trampoline(boot_addr_uniq);
  249. dcache_enable();
  250. set_r5_halt_mode(RELEASE, SPLIT);
  251. } else {
  252. printf("Unsupported mode\n");
  253. return 1;
  254. }
  255. }
  256. return 0;
  257. }