cpu.c 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <time.h>
  9. #include <asm/arch/hardware.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/armv8/mmu.h>
  12. #include <asm/cache.h>
  13. #include <asm/io.h>
  14. #include <zynqmp_firmware.h>
  15. #include <asm/cache.h>
  16. #define ZYNQ_SILICON_VER_MASK 0xF000
  17. #define ZYNQ_SILICON_VER_SHIFT 12
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /*
  20. * Number of filled static entries and also the first empty
  21. * slot in zynqmp_mem_map.
  22. */
  23. #define ZYNQMP_MEM_MAP_USED 4
  24. #if !defined(CONFIG_ZYNQMP_NO_DDR)
  25. #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  26. #else
  27. #define DRAM_BANKS 0
  28. #endif
  29. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  30. #define TCM_MAP 1
  31. #else
  32. #define TCM_MAP 0
  33. #endif
  34. /* +1 is end of list which needs to be empty */
  35. #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  36. static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
  37. {
  38. .virt = 0x80000000UL,
  39. .phys = 0x80000000UL,
  40. .size = 0x70000000UL,
  41. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  42. PTE_BLOCK_NON_SHARE |
  43. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  44. }, {
  45. .virt = 0xf8000000UL,
  46. .phys = 0xf8000000UL,
  47. .size = 0x07e00000UL,
  48. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  49. PTE_BLOCK_NON_SHARE |
  50. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  51. }, {
  52. .virt = 0x400000000UL,
  53. .phys = 0x400000000UL,
  54. .size = 0x400000000UL,
  55. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56. PTE_BLOCK_NON_SHARE |
  57. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  58. }, {
  59. .virt = 0x1000000000UL,
  60. .phys = 0x1000000000UL,
  61. .size = 0xf000000000UL,
  62. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  63. PTE_BLOCK_NON_SHARE |
  64. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  65. }
  66. };
  67. void mem_map_fill(void)
  68. {
  69. int banks = ZYNQMP_MEM_MAP_USED;
  70. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  71. zynqmp_mem_map[banks].virt = 0xffe00000UL;
  72. zynqmp_mem_map[banks].phys = 0xffe00000UL;
  73. zynqmp_mem_map[banks].size = 0x00200000UL;
  74. zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  75. PTE_BLOCK_INNER_SHARE;
  76. banks = banks + 1;
  77. #endif
  78. #if !defined(CONFIG_ZYNQMP_NO_DDR)
  79. for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  80. /* Zero size means no more DDR that's this is end */
  81. if (!gd->bd->bi_dram[i].size)
  82. break;
  83. zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  84. zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  85. zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  86. zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  87. PTE_BLOCK_INNER_SHARE;
  88. banks = banks + 1;
  89. }
  90. #endif
  91. }
  92. struct mm_region *mem_map = zynqmp_mem_map;
  93. u64 get_page_table_size(void)
  94. {
  95. return 0x14000;
  96. }
  97. #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  98. void tcm_init(u8 mode)
  99. {
  100. puts("WARNING: Initializing TCM overwrites TCM content\n");
  101. initialize_tcm(mode);
  102. memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
  103. }
  104. #endif
  105. #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
  106. int arm_reserve_mmu(void)
  107. {
  108. tcm_init(TCM_LOCK);
  109. gd->arch.tlb_size = PGTABLE_SIZE;
  110. gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
  111. return 0;
  112. }
  113. #endif
  114. static unsigned int zynqmp_get_silicon_version_secure(void)
  115. {
  116. u32 ver;
  117. ver = readl(&csu_base->version);
  118. ver &= ZYNQMP_SILICON_VER_MASK;
  119. ver >>= ZYNQMP_SILICON_VER_SHIFT;
  120. return ver;
  121. }
  122. unsigned int zynqmp_get_silicon_version(void)
  123. {
  124. if (current_el() == 3)
  125. return zynqmp_get_silicon_version_secure();
  126. gd->cpu_clk = get_tbclk();
  127. switch (gd->cpu_clk) {
  128. case 50000000:
  129. return ZYNQMP_CSU_VERSION_QEMU;
  130. }
  131. return ZYNQMP_CSU_VERSION_SILICON;
  132. }
  133. static int zynqmp_mmio_rawwrite(const u32 address,
  134. const u32 mask,
  135. const u32 value)
  136. {
  137. u32 data;
  138. u32 value_local = value;
  139. int ret;
  140. ret = zynqmp_mmio_read(address, &data);
  141. if (ret)
  142. return ret;
  143. data &= ~mask;
  144. value_local &= mask;
  145. value_local |= data;
  146. writel(value_local, (ulong)address);
  147. return 0;
  148. }
  149. static int zynqmp_mmio_rawread(const u32 address, u32 *value)
  150. {
  151. *value = readl((ulong)address);
  152. return 0;
  153. }
  154. int zynqmp_mmio_write(const u32 address,
  155. const u32 mask,
  156. const u32 value)
  157. {
  158. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
  159. return zynqmp_mmio_rawwrite(address, mask, value);
  160. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  161. else
  162. return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
  163. value, 0, NULL);
  164. #endif
  165. return -EINVAL;
  166. }
  167. int zynqmp_mmio_read(const u32 address, u32 *value)
  168. {
  169. u32 ret = -EINVAL;
  170. if (!value)
  171. return ret;
  172. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
  173. ret = zynqmp_mmio_rawread(address, value);
  174. }
  175. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  176. else {
  177. u32 ret_payload[PAYLOAD_ARG_CNT];
  178. ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
  179. 0, ret_payload);
  180. *value = ret_payload[1];
  181. }
  182. #endif
  183. return ret;
  184. }