pfc-r8a7790.h 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
  4. *
  5. * Copyright (C) 2013 Renesas Electronics Corporation
  6. */
  7. #ifndef __PFC_R8A7790_H__
  8. #define __PFC_R8A7790_H__
  9. #include <sh_pfc.h>
  10. #include <asm/gpio.h>
  11. #define CPU_32_PORT(fn, pfx, sfx) \
  12. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  13. PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
  14. PORT_1(fn, pfx##31, sfx)
  15. #define CPU_32_PORT2(fn, pfx, sfx) \
  16. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  17. PORT_10(fn, pfx##2, sfx)
  18. #if defined(CONFIG_R8A7790)
  19. #define CPU_32_PORT1(fn, pfx, sfx) \
  20. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  21. PORT_10(fn, pfx##2, sfx) \
  22. /* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
  23. #define CPU_ALL_PORT(fn, pfx, sfx) \
  24. CPU_32_PORT(fn, pfx##_0_, sfx), \
  25. CPU_32_PORT1(fn, pfx##_1_, sfx), \
  26. CPU_32_PORT2(fn, pfx##_2_, sfx), \
  27. CPU_32_PORT(fn, pfx##_3_, sfx), \
  28. CPU_32_PORT(fn, pfx##_4_, sfx), \
  29. CPU_32_PORT(fn, pfx##_5_, sfx)
  30. #elif defined(CONFIG_R8A7791)
  31. #define CPU_32_PORT1(fn, pfx, sfx) \
  32. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  33. PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
  34. PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
  35. PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
  36. /*
  37. * GP_0_0_DATA -> GP_7_25_DATA
  38. * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
  39. * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
  40. */
  41. #define CPU_ALL_PORT(fn, pfx, sfx) \
  42. CPU_32_PORT(fn, pfx##_0_, sfx), \
  43. CPU_32_PORT1(fn, pfx##_1_, sfx), \
  44. CPU_32_PORT(fn, pfx##_2_, sfx), \
  45. CPU_32_PORT(fn, pfx##_3_, sfx), \
  46. CPU_32_PORT(fn, pfx##_4_, sfx), \
  47. CPU_32_PORT(fn, pfx##_5_, sfx), \
  48. CPU_32_PORT(fn, pfx##_6_, sfx), \
  49. CPU_32_PORT1(fn, pfx##_7_, sfx)
  50. #elif defined(CONFIG_R8A7792)
  51. /*
  52. * GP_0_0_DATA -> GP_11_29_DATA
  53. * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
  54. * GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
  55. */
  56. #define CPU_32_PORT0_28(fn, pfx, sfx) \
  57. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  58. PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
  59. PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
  60. PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
  61. PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \
  62. PORT_1(fn, pfx##28, sfx)
  63. #define CPU_32_PORT0_22(fn, pfx, sfx) \
  64. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  65. PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
  66. PORT_1(fn, pfx##22, sfx)
  67. #define CPU_32_PORT0_27(fn, pfx, sfx) \
  68. PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
  69. PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
  70. PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
  71. PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
  72. PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
  73. #define CPU_32_PORT0_16(fn, pfx, sfx) \
  74. PORT_10(fn, pfx, sfx), \
  75. PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
  76. PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
  77. PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
  78. PORT_1(fn, pfx##16, sfx)
  79. #define CPU_ALL_PORT(fn, pfx, sfx) \
  80. CPU_32_PORT0_28(fn, pfx##_0_, sfx), \
  81. CPU_32_PORT0_22(fn, pfx##_1_, sfx), \
  82. CPU_32_PORT(fn, pfx##_2_, sfx), \
  83. CPU_32_PORT0_27(fn, pfx##_3_, sfx), \
  84. CPU_32_PORT0_16(fn, pfx##_4_, sfx), \
  85. CPU_32_PORT0_16(fn, pfx##_5_, sfx), \
  86. CPU_32_PORT0_16(fn, pfx##_6_, sfx), \
  87. CPU_32_PORT0_16(fn, pfx##_7_, sfx), \
  88. CPU_32_PORT0_16(fn, pfx##_8_, sfx), \
  89. CPU_32_PORT0_16(fn, pfx##_9_, sfx), \
  90. CPU_32_PORT(fn, pfx##_10_, sfx), \
  91. CPU_32_PORT2(fn, pfx##_11_, sfx)
  92. #else
  93. #error "NO support"
  94. #endif
  95. #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
  96. #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
  97. GP##pfx##_IN, GP##pfx##_OUT)
  98. #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
  99. #define _GP_INDT(pfx, sfx) GP##pfx##_DATA
  100. #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
  101. #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
  102. #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
  103. #define PORT_10_REV(fn, pfx, sfx) \
  104. PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
  105. PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
  106. PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
  107. PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
  108. PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
  109. #define CPU_32_PORT_REV(fn, pfx, sfx) \
  110. PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
  111. PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
  112. PORT_10_REV(fn, pfx, sfx)
  113. #define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
  114. #define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
  115. #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  116. #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  117. FN_##ipsr, FN_##fn)
  118. #endif /* __PFC_R8A7790_H__ */