lowlevel_init_gen3.S 2.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
  4. * This file is lowlevel initialize routine.
  5. *
  6. * (C) Copyright 2015 Renesas Electronics Corporation
  7. *
  8. * This file is based on the arch/arm/cpu/armv8/start.S
  9. *
  10. * (C) Copyright 2013
  11. * David Feng <fenghua@phytium.com.cn>
  12. */
  13. #include <asm-offsets.h>
  14. #include <config.h>
  15. #include <linux/linkage.h>
  16. #include <asm/macro.h>
  17. .align 8
  18. .globl rcar_atf_boot_args
  19. rcar_atf_boot_args:
  20. .dword 0
  21. .dword 0
  22. .dword 0
  23. .dword 0
  24. ENTRY(save_boot_params)
  25. adr x8, rcar_atf_boot_args
  26. stp x0, x1, [x8], #16
  27. stp x2, x3, [x8], #16
  28. b save_boot_params_ret
  29. ENDPROC(save_boot_params)
  30. .pushsection .text.s_init, "ax"
  31. WEAK(s_init)
  32. ret
  33. ENDPROC(s_init)
  34. .popsection
  35. ENTRY(lowlevel_init)
  36. mov x29, lr /* Save LR */
  37. #ifndef CONFIG_ARMV8_MULTIENTRY
  38. /*
  39. * For single-entry systems the lowlevel init is very simple.
  40. */
  41. ldr x0, =GICD_BASE
  42. bl gic_init_secure
  43. #else /* CONFIG_ARMV8_MULTIENTRY is set */
  44. #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  45. branch_if_slave x0, 1f
  46. ldr x0, =GICD_BASE
  47. bl gic_init_secure
  48. 1:
  49. #if defined(CONFIG_GICV3)
  50. ldr x0, =GICR_BASE
  51. bl gic_init_secure_percpu
  52. #elif defined(CONFIG_GICV2)
  53. ldr x0, =GICD_BASE
  54. ldr x1, =GICC_BASE
  55. bl gic_init_secure_percpu
  56. #endif
  57. #endif
  58. branch_if_master x0, x1, 2f
  59. /*
  60. * Slave should wait for master clearing spin table.
  61. * This sync prevent salves observing incorrect
  62. * value of spin table and jumping to wrong place.
  63. */
  64. #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  65. #ifdef CONFIG_GICV2
  66. ldr x0, =GICC_BASE
  67. #endif
  68. bl gic_wait_for_interrupt
  69. #endif
  70. /*
  71. * All slaves will enter EL2 and optionally EL1.
  72. */
  73. adr x4, lowlevel_in_el2
  74. ldr x5, =ES_TO_AARCH64
  75. bl armv8_switch_to_el2
  76. lowlevel_in_el2:
  77. #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
  78. adr x4, lowlevel_in_el1
  79. ldr x5, =ES_TO_AARCH64
  80. bl armv8_switch_to_el1
  81. lowlevel_in_el1:
  82. #endif
  83. #endif /* CONFIG_ARMV8_MULTIENTRY */
  84. bl s_init
  85. 2:
  86. mov lr, x29 /* Restore LR */
  87. ret
  88. ENDPROC(lowlevel_init)