board.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Common board functions for AM33XX based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <debug_uart.h>
  12. #include <errno.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <ns16550.h>
  16. #include <omap3_spi.h>
  17. #include <spl.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/hardware.h>
  20. #include <asm/arch/omap.h>
  21. #include <asm/arch/ddr_defs.h>
  22. #include <asm/arch/clock.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/i2c.h>
  25. #include <asm/arch/mem.h>
  26. #include <asm/arch/mmc_host_def.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <asm/io.h>
  29. #include <asm/emif.h>
  30. #include <asm/gpio.h>
  31. #include <asm/omap_common.h>
  32. #include <i2c.h>
  33. #include <miiphy.h>
  34. #include <cpsw.h>
  35. #include <linux/delay.h>
  36. #include <linux/errno.h>
  37. #include <linux/compiler.h>
  38. #include <linux/usb/ch9.h>
  39. #include <linux/usb/gadget.h>
  40. #include <linux/usb/musb.h>
  41. #include <asm/omap_musb.h>
  42. #include <asm/davinci_rtc.h>
  43. #define AM43XX_EMIF_BASE 0x4C000000
  44. #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
  45. #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
  46. #define AM43XX_SDRAM_TYPE_SHIFT 29
  47. #define AM43XX_SDRAM_TYPE_DDR3 3
  48. #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
  49. #define AM43XX_RDWRLVLFULL_START 0x80000000
  50. /* SPI flash. */
  51. #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
  52. #define AM33XX_SPI0_BASE 0x48030000
  53. #define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET)
  54. #endif
  55. DECLARE_GLOBAL_DATA_PTR;
  56. int dram_init(void)
  57. {
  58. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  59. sdram_init();
  60. #endif
  61. /* dram_init must store complete ramsize in gd->ram_size */
  62. gd->ram_size = get_ram_size(
  63. (void *)CONFIG_SYS_SDRAM_BASE,
  64. CONFIG_MAX_RAM_BANK_SIZE);
  65. return 0;
  66. }
  67. int dram_init_banksize(void)
  68. {
  69. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  70. gd->bd->bi_dram[0].size = gd->ram_size;
  71. return 0;
  72. }
  73. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  74. static const struct ns16550_platdata am33xx_serial[] = {
  75. { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
  76. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  77. # ifdef CONFIG_SYS_NS16550_COM2
  78. { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
  79. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  80. # ifdef CONFIG_SYS_NS16550_COM3
  81. { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
  82. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  83. { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
  84. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  85. { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
  86. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  87. { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
  88. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  89. # endif
  90. # endif
  91. };
  92. U_BOOT_DEVICES(am33xx_uarts) = {
  93. { "ns16550_serial", &am33xx_serial[0] },
  94. # ifdef CONFIG_SYS_NS16550_COM2
  95. { "ns16550_serial", &am33xx_serial[1] },
  96. # ifdef CONFIG_SYS_NS16550_COM3
  97. { "ns16550_serial", &am33xx_serial[2] },
  98. { "ns16550_serial", &am33xx_serial[3] },
  99. { "ns16550_serial", &am33xx_serial[4] },
  100. { "ns16550_serial", &am33xx_serial[5] },
  101. # endif
  102. # endif
  103. };
  104. #ifdef CONFIG_DM_I2C
  105. static const struct omap_i2c_platdata am33xx_i2c[] = {
  106. { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
  107. { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
  108. { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
  109. };
  110. U_BOOT_DEVICES(am33xx_i2c) = {
  111. { "i2c_omap", &am33xx_i2c[0] },
  112. { "i2c_omap", &am33xx_i2c[1] },
  113. { "i2c_omap", &am33xx_i2c[2] },
  114. };
  115. #endif
  116. #if CONFIG_IS_ENABLED(DM_GPIO)
  117. static const struct omap_gpio_platdata am33xx_gpio[] = {
  118. { 0, AM33XX_GPIO0_BASE },
  119. { 1, AM33XX_GPIO1_BASE },
  120. { 2, AM33XX_GPIO2_BASE },
  121. { 3, AM33XX_GPIO3_BASE },
  122. #ifdef CONFIG_AM43XX
  123. { 4, AM33XX_GPIO4_BASE },
  124. { 5, AM33XX_GPIO5_BASE },
  125. #endif
  126. };
  127. U_BOOT_DEVICES(am33xx_gpios) = {
  128. { "gpio_omap", &am33xx_gpio[0] },
  129. { "gpio_omap", &am33xx_gpio[1] },
  130. { "gpio_omap", &am33xx_gpio[2] },
  131. { "gpio_omap", &am33xx_gpio[3] },
  132. #ifdef CONFIG_AM43XX
  133. { "gpio_omap", &am33xx_gpio[4] },
  134. { "gpio_omap", &am33xx_gpio[5] },
  135. #endif
  136. };
  137. #endif
  138. #if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL)
  139. static const struct omap3_spi_plat omap3_spi_pdata = {
  140. .regs = (struct mcspi *)AM33XX_SPI0_OFFSET,
  141. .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
  142. };
  143. U_BOOT_DEVICE(am33xx_spi) = {
  144. .name = "omap3_spi",
  145. .platdata = &omap3_spi_pdata,
  146. };
  147. #endif
  148. #endif
  149. #if !CONFIG_IS_ENABLED(DM_GPIO)
  150. static const struct gpio_bank gpio_bank_am33xx[] = {
  151. { (void *)AM33XX_GPIO0_BASE },
  152. { (void *)AM33XX_GPIO1_BASE },
  153. { (void *)AM33XX_GPIO2_BASE },
  154. { (void *)AM33XX_GPIO3_BASE },
  155. #ifdef CONFIG_AM43XX
  156. { (void *)AM33XX_GPIO4_BASE },
  157. { (void *)AM33XX_GPIO5_BASE },
  158. #endif
  159. };
  160. const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  161. #endif
  162. #if defined(CONFIG_MMC_OMAP_HS)
  163. int cpu_mmc_init(struct bd_info *bis)
  164. {
  165. int ret;
  166. ret = omap_mmc_init(0, 0, 0, -1, -1);
  167. if (ret)
  168. return ret;
  169. return omap_mmc_init(1, 0, 0, -1, -1);
  170. }
  171. #endif
  172. /*
  173. * RTC only with DDR in self-refresh mode magic value, checked against during
  174. * boot to see if we have a valid config. This should be in sync with the value
  175. * that will be in drivers/soc/ti/pm33xx.c.
  176. */
  177. #define RTC_MAGIC_VAL 0x8cd0
  178. /* Board type field bit shift for RTC only with DDR in self-refresh mode */
  179. #define RTC_BOARD_TYPE_SHIFT 16
  180. /* AM33XX has two MUSB controllers which can be host or gadget */
  181. #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
  182. (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
  183. (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
  184. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
  185. static struct musb_hdrc_config musb_config = {
  186. .multipoint = 1,
  187. .dyn_fifo = 1,
  188. .num_eps = 16,
  189. .ram_bits = 12,
  190. };
  191. #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
  192. static struct ti_musb_platdata usb0 = {
  193. .base = (void *)USB0_OTG_BASE,
  194. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
  195. .plat = {
  196. .config = &musb_config,
  197. .power = 50,
  198. .platform_ops = &musb_dsps_ops,
  199. },
  200. };
  201. static struct ti_musb_platdata usb1 = {
  202. .base = (void *)USB1_OTG_BASE,
  203. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
  204. .plat = {
  205. .config = &musb_config,
  206. .power = 50,
  207. .platform_ops = &musb_dsps_ops,
  208. },
  209. };
  210. U_BOOT_DEVICES(am33xx_usbs) = {
  211. #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
  212. { "ti-musb-peripheral", &usb0 },
  213. #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
  214. { "ti-musb-host", &usb0 },
  215. #endif
  216. #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
  217. { "ti-musb-peripheral", &usb1 },
  218. #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
  219. { "ti-musb-host", &usb1 },
  220. #endif
  221. };
  222. int arch_misc_init(void)
  223. {
  224. return 0;
  225. }
  226. #else
  227. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  228. /* USB 2.0 PHY Control */
  229. #define CM_PHY_PWRDN (1 << 0)
  230. #define CM_PHY_OTG_PWRDN (1 << 1)
  231. #define OTGVDET_EN (1 << 19)
  232. #define OTGSESSENDEN (1 << 20)
  233. static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
  234. {
  235. if (on) {
  236. clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
  237. OTGVDET_EN | OTGSESSENDEN);
  238. } else {
  239. clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
  240. }
  241. }
  242. #ifdef CONFIG_AM335X_USB0
  243. static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
  244. {
  245. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
  246. }
  247. struct omap_musb_board_data otg0_board_data = {
  248. .set_phy_power = am33xx_otg0_set_phy_power,
  249. };
  250. static struct musb_hdrc_platform_data otg0_plat = {
  251. .mode = CONFIG_AM335X_USB0_MODE,
  252. .config = &musb_config,
  253. .power = 50,
  254. .platform_ops = &musb_dsps_ops,
  255. .board_data = &otg0_board_data,
  256. };
  257. #endif
  258. #ifdef CONFIG_AM335X_USB1
  259. static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
  260. {
  261. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
  262. }
  263. struct omap_musb_board_data otg1_board_data = {
  264. .set_phy_power = am33xx_otg1_set_phy_power,
  265. };
  266. static struct musb_hdrc_platform_data otg1_plat = {
  267. .mode = CONFIG_AM335X_USB1_MODE,
  268. .config = &musb_config,
  269. .power = 50,
  270. .platform_ops = &musb_dsps_ops,
  271. .board_data = &otg1_board_data,
  272. };
  273. #endif
  274. int arch_misc_init(void)
  275. {
  276. #ifdef CONFIG_AM335X_USB0
  277. musb_register(&otg0_plat, &otg0_board_data,
  278. (void *)USB0_OTG_BASE);
  279. #endif
  280. #ifdef CONFIG_AM335X_USB1
  281. musb_register(&otg1_plat, &otg1_board_data,
  282. (void *)USB1_OTG_BASE);
  283. #endif
  284. return 0;
  285. }
  286. #endif
  287. #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  288. int arch_misc_init(void)
  289. {
  290. struct udevice *dev;
  291. int ret;
  292. ret = uclass_first_device(UCLASS_MISC, &dev);
  293. if (ret || !dev)
  294. return ret;
  295. #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
  296. ret = usb_ether_init();
  297. if (ret) {
  298. pr_err("USB ether init failed\n");
  299. return ret;
  300. }
  301. #endif
  302. return 0;
  303. }
  304. #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  305. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  306. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
  307. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
  308. static void rtc32k_unlock(struct davinci_rtc *rtc)
  309. {
  310. /*
  311. * Unlock the RTC's registers. For more details please see the
  312. * RTC_SS section of the TRM. In order to unlock we need to
  313. * write these specific values (keys) in this order.
  314. */
  315. writel(RTC_KICK0R_WE, &rtc->kick0r);
  316. writel(RTC_KICK1R_WE, &rtc->kick1r);
  317. }
  318. #endif
  319. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  320. /*
  321. * Write contents of the RTC_SCRATCH1 register based on board type
  322. * Two things are passed
  323. * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
  324. * control gets to kernel, kernel reads the scratchpad register and gets to
  325. * know that bootloader has rtc_only support.
  326. *
  327. * Second important thing is the board type (16:31). This is needed in the
  328. * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
  329. * identify the board type and we go ahead and copy the board strings to
  330. * am43xx_board_name.
  331. */
  332. void update_rtc_magic(void)
  333. {
  334. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  335. u32 magic = RTC_MAGIC_VAL;
  336. magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
  337. rtc32k_unlock(rtc);
  338. /* write magic */
  339. writel(magic, &rtc->scratch1);
  340. }
  341. #endif
  342. /*
  343. * In the case of non-SPL based booting we'll want to call these
  344. * functions a tiny bit later as it will require gd to be set and cleared
  345. * and that's not true in s_init in this case so we cannot do it there.
  346. */
  347. int board_early_init_f(void)
  348. {
  349. set_mux_conf_regs();
  350. prcm_init();
  351. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  352. update_rtc_magic();
  353. #endif
  354. return 0;
  355. }
  356. /*
  357. * This function is the place to do per-board things such as ramp up the
  358. * MPU clock frequency.
  359. */
  360. __weak void am33xx_spl_board_init(void)
  361. {
  362. }
  363. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  364. static void rtc32k_enable(void)
  365. {
  366. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  367. rtc32k_unlock(rtc);
  368. /* Enable the RTC 32K OSC by setting bits 3 and 6. */
  369. writel((1 << 3) | (1 << 6), &rtc->osc);
  370. }
  371. #endif
  372. static void uart_soft_reset(void)
  373. {
  374. struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  375. u32 regval;
  376. regval = readl(&uart_base->uartsyscfg);
  377. regval |= UART_RESET;
  378. writel(regval, &uart_base->uartsyscfg);
  379. while ((readl(&uart_base->uartsyssts) &
  380. UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  381. ;
  382. /* Disable smart idle */
  383. regval = readl(&uart_base->uartsyscfg);
  384. regval |= UART_SMART_IDLE_EN;
  385. writel(regval, &uart_base->uartsyscfg);
  386. }
  387. static void watchdog_disable(void)
  388. {
  389. struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  390. writel(0xAAAA, &wdtimer->wdtwspr);
  391. while (readl(&wdtimer->wdtwwps) != 0x0)
  392. ;
  393. writel(0x5555, &wdtimer->wdtwspr);
  394. while (readl(&wdtimer->wdtwwps) != 0x0)
  395. ;
  396. }
  397. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  398. /*
  399. * Check if we are executing rtc-only + DDR mode, and resume from it if needed
  400. */
  401. static void rtc_only(void)
  402. {
  403. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  404. struct prm_device_inst *prm_device =
  405. (struct prm_device_inst *)PRM_DEVICE_INST;
  406. u32 scratch1, sdrc;
  407. void (*resume_func)(void);
  408. scratch1 = readl(&rtc->scratch1);
  409. /*
  410. * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
  411. * written to this register when we want to wake up from RTC only
  412. * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
  413. * bits 0-15: RTC_MAGIC_VAL
  414. * bits 16-31: board type (needed for sdram_init)
  415. */
  416. if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
  417. return;
  418. rtc32k_unlock(rtc);
  419. /* Clear RTC magic */
  420. writel(0, &rtc->scratch1);
  421. /*
  422. * Update board type based on value stored on RTC_SCRATCH1, this
  423. * is done so that we don't need to read the board type from eeprom
  424. * over i2c bus which is expensive
  425. */
  426. rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
  427. /*
  428. * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
  429. * are resuming from self-refresh. This avoids an unnecessary re-init
  430. * of the DDR. The re-init takes time and we would need to wait for
  431. * it to complete before accessing DDR to avoid L3 NOC errors.
  432. */
  433. writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
  434. rtc_only_prcm_init();
  435. sdram_init();
  436. /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
  437. /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
  438. sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
  439. sdrc &= AM43XX_SDRAM_TYPE_MASK;
  440. sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
  441. if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
  442. writel(AM43XX_RDWRLVLFULL_START,
  443. AM43XX_EMIF_BASE +
  444. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  445. mdelay(1);
  446. am43xx_wait:
  447. sdrc = readl(AM43XX_EMIF_BASE +
  448. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  449. if (sdrc == AM43XX_RDWRLVLFULL_START)
  450. goto am43xx_wait;
  451. }
  452. resume_func = (void *)readl(&rtc->scratch0);
  453. if (resume_func)
  454. resume_func();
  455. }
  456. #endif
  457. void s_init(void)
  458. {
  459. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  460. rtc_only();
  461. #endif
  462. }
  463. void early_system_init(void)
  464. {
  465. /*
  466. * The ROM will only have set up sufficient pinmux to allow for the
  467. * first 4KiB NOR to be read, we must finish doing what we know of
  468. * the NOR mux in this space in order to continue.
  469. */
  470. #ifdef CONFIG_NOR_BOOT
  471. enable_norboot_pin_mux();
  472. #endif
  473. watchdog_disable();
  474. set_uart_mux_conf();
  475. setup_early_clocks();
  476. uart_soft_reset();
  477. #ifdef CONFIG_SPL_BUILD
  478. /*
  479. * Save the boot parameters passed from romcode.
  480. * We cannot delay the saving further than this,
  481. * to prevent overwrites.
  482. */
  483. save_omap_boot_params();
  484. #endif
  485. #ifdef CONFIG_DEBUG_UART_OMAP
  486. debug_uart_init();
  487. #endif
  488. #ifdef CONFIG_SPL_BUILD
  489. spl_early_init();
  490. #endif
  491. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  492. do_board_detect();
  493. #endif
  494. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  495. /* Enable RTC32K clock */
  496. rtc32k_enable();
  497. #endif
  498. }
  499. #ifdef CONFIG_SPL_BUILD
  500. void board_init_f(ulong dummy)
  501. {
  502. hw_data_init();
  503. early_system_init();
  504. board_early_init_f();
  505. sdram_init();
  506. /* dram_init must store complete ramsize in gd->ram_size */
  507. gd->ram_size = get_ram_size(
  508. (void *)CONFIG_SYS_SDRAM_BASE,
  509. CONFIG_MAX_RAM_BANK_SIZE);
  510. }
  511. #endif
  512. #endif
  513. int arch_cpu_init_dm(void)
  514. {
  515. hw_data_init();
  516. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  517. early_system_init();
  518. #endif
  519. return 0;
  520. }