board-gx.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/boot.h>
  10. #include <asm/arch/eth.h>
  11. #include <asm/arch/gx.h>
  12. #include <asm/arch/mem.h>
  13. #include <asm/arch/meson-vpu.h>
  14. #include <asm/io.h>
  15. #include <asm/armv8/mmu.h>
  16. #include <linux/sizes.h>
  17. #include <usb.h>
  18. #include <linux/usb/otg.h>
  19. #include <asm/arch/usb-gx.h>
  20. #include <usb/dwc2_udc.h>
  21. #include <clk.h>
  22. #include <phy.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. int meson_get_boot_device(void)
  25. {
  26. return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
  27. }
  28. /* Configure the reserved memory zones exported by the secure registers
  29. * into EFI and DTB reserved memory entries.
  30. */
  31. void meson_init_reserved_memory(void *fdt)
  32. {
  33. u64 bl31_size, bl31_start;
  34. u64 bl32_size, bl32_start;
  35. u32 reg;
  36. /*
  37. * Get ARM Trusted Firmware reserved memory zones in :
  38. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  39. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  40. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  41. */
  42. reg = readl(GX_AO_SEC_GP_CFG3);
  43. bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
  44. >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  45. bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  46. bl31_start = readl(GX_AO_SEC_GP_CFG5);
  47. bl32_start = readl(GX_AO_SEC_GP_CFG4);
  48. /*
  49. * Early Meson GX Firmware revisions did not provide the reserved
  50. * memory zones in the registers, keep fixed memory zone handling.
  51. */
  52. if (IS_ENABLED(CONFIG_MESON_GX) &&
  53. !reg && !bl31_start && !bl32_start) {
  54. bl31_start = 0x10000000;
  55. bl31_size = 0x200000;
  56. }
  57. /* Add first 16MiB reserved zone */
  58. meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
  59. /* Add BL31 reserved zone */
  60. if (bl31_start && bl31_size)
  61. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  62. /* Add BL32 reserved zone */
  63. if (bl32_start && bl32_size)
  64. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  65. #if defined(CONFIG_VIDEO_MESON)
  66. meson_vpu_rsv_fb(fdt);
  67. #endif
  68. }
  69. phys_size_t get_effective_memsize(void)
  70. {
  71. /* Size is reported in MiB, convert it in bytes */
  72. return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
  73. >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
  74. }
  75. static struct mm_region gx_mem_map[] = {
  76. {
  77. .virt = 0x0UL,
  78. .phys = 0x0UL,
  79. .size = 0xc0000000UL,
  80. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  81. PTE_BLOCK_INNER_SHARE
  82. }, {
  83. .virt = 0xc0000000UL,
  84. .phys = 0xc0000000UL,
  85. .size = 0x30000000UL,
  86. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  87. PTE_BLOCK_NON_SHARE |
  88. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  89. }, {
  90. /* List terminator */
  91. 0,
  92. }
  93. };
  94. struct mm_region *mem_map = gx_mem_map;
  95. /* Configure the Ethernet MAC with the requested interface mode
  96. * with some optional flags.
  97. */
  98. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  99. {
  100. switch (mode) {
  101. case PHY_INTERFACE_MODE_RGMII:
  102. case PHY_INTERFACE_MODE_RGMII_ID:
  103. case PHY_INTERFACE_MODE_RGMII_RXID:
  104. case PHY_INTERFACE_MODE_RGMII_TXID:
  105. /* Set RGMII mode */
  106. setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
  107. GX_ETH_REG_0_TX_PHASE(1) |
  108. GX_ETH_REG_0_TX_RATIO(4) |
  109. GX_ETH_REG_0_PHY_CLK_EN |
  110. GX_ETH_REG_0_CLK_EN);
  111. /* Reset to external PHY */
  112. if(!IS_ENABLED(CONFIG_MESON_GXBB))
  113. writel(0x2009087f, GX_ETH_REG_3);
  114. break;
  115. case PHY_INTERFACE_MODE_RMII:
  116. /* Set RMII mode */
  117. out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
  118. GX_ETH_REG_0_CLK_EN);
  119. /* Use GXL RMII Internal PHY (also on GXM) */
  120. if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
  121. if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
  122. writel(0x10110181, GX_ETH_REG_2);
  123. writel(0xe40908ff, GX_ETH_REG_3);
  124. } else
  125. writel(0x2009087f, GX_ETH_REG_3);
  126. }
  127. break;
  128. default:
  129. printf("Invalid Ethernet interface mode\n");
  130. return;
  131. }
  132. /* Enable power gate */
  133. clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
  134. }
  135. #if CONFIG_IS_ENABLED(USB_XHCI_DWC3_OF_SIMPLE) && \
  136. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  137. static struct dwc2_plat_otg_data meson_gx_dwc2_data;
  138. static struct phy usb_phys[2];
  139. int board_usb_init(int index, enum usb_init_type init)
  140. {
  141. struct ofnode_phandle_args args;
  142. struct udevice *clk_dev;
  143. ofnode dwc2_node;
  144. struct clk clk;
  145. int ret, i;
  146. u32 val;
  147. /* find the dwc2 node */
  148. dwc2_node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
  149. if (!ofnode_valid(dwc2_node)) {
  150. debug("Not found dwc2 node\n");
  151. return -ENODEV;
  152. }
  153. if (!ofnode_is_available(dwc2_node)) {
  154. debug("dwc2 is disabled in the device tree\n");
  155. return -ENODEV;
  156. }
  157. /* get the PHYs */
  158. for (i = 0; i < 2; i++) {
  159. ret = generic_phy_get_by_index_nodev(dwc2_node, i,
  160. &usb_phys[i]);
  161. if (ret && ret != -ENOENT) {
  162. pr_err("Failed to get USB PHY%d for %s\n",
  163. i, ofnode_get_name(dwc2_node));
  164. return ret;
  165. }
  166. }
  167. for (i = 0; i < 2; i++) {
  168. ret = generic_phy_init(&usb_phys[i]);
  169. if (ret) {
  170. pr_debug("Can't init USB PHY%d for %s\n",
  171. i, ofnode_get_name(dwc2_node));
  172. return ret;
  173. }
  174. }
  175. for (i = 0; i < 2; i++) {
  176. ret = generic_phy_power_on(&usb_phys[i]);
  177. if (ret) {
  178. pr_debug("Can't power USB PHY%d for %s\n",
  179. i, ofnode_get_name(dwc2_node));
  180. return ret;
  181. }
  182. }
  183. phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_PERIPHERAL);
  184. phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_PERIPHERAL);
  185. meson_gx_dwc2_data.regs_otg = ofnode_get_addr(dwc2_node);
  186. if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  187. debug("usbotg: can't get base address\n");
  188. return -ENODATA;
  189. }
  190. /* Enable clock */
  191. ret = ofnode_parse_phandle_with_args(dwc2_node, "clocks",
  192. "#clock-cells", 0, 0, &args);
  193. if (ret) {
  194. debug("usbotg has no clocks defined in the device tree\n");
  195. return ret;
  196. }
  197. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &clk_dev);
  198. if (ret)
  199. return ret;
  200. if (args.args_count != 1) {
  201. debug("Can't find clock ID in the device tree\n");
  202. return -ENODATA;
  203. }
  204. clk.dev = clk_dev;
  205. clk.id = args.args[0];
  206. ret = clk_enable(&clk);
  207. if (ret) {
  208. debug("Failed to enable usbotg clock\n");
  209. return ret;
  210. }
  211. ofnode_read_u32(dwc2_node, "g-rx-fifo-size", &val);
  212. meson_gx_dwc2_data.rx_fifo_sz = val;
  213. ofnode_read_u32(dwc2_node, "g-np-tx-fifo-size", &val);
  214. meson_gx_dwc2_data.np_tx_fifo_sz = val;
  215. ofnode_read_u32(dwc2_node, "g-tx-fifo-size", &val);
  216. meson_gx_dwc2_data.tx_fifo_sz = val;
  217. return dwc2_udc_probe(&meson_gx_dwc2_data);
  218. }
  219. int board_usb_cleanup(int index, enum usb_init_type init)
  220. {
  221. int i;
  222. phy_meson_gxl_usb3_set_mode(&usb_phys[0], USB_DR_MODE_HOST);
  223. phy_meson_gxl_usb2_set_mode(&usb_phys[1], USB_DR_MODE_HOST);
  224. for (i = 0; i < 2; i++)
  225. usb_phys[i].dev = NULL;
  226. return 0;
  227. }
  228. #endif