arm64-mmu.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K3: ARM64 MMU setup
  4. *
  5. * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. * Suman Anna <s-anna@ti.com>
  8. * (This file is derived from arch/arm/mach-zynqmp/cpu.c)
  9. *
  10. */
  11. #include <common.h>
  12. #include <asm/system.h>
  13. #include <asm/armv8/mmu.h>
  14. #ifdef CONFIG_SOC_K3_AM6
  15. /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  16. #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
  17. /* ToDo: Add 64bit IO */
  18. struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
  19. {
  20. .virt = 0x0UL,
  21. .phys = 0x0UL,
  22. .size = 0x80000000UL,
  23. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  24. PTE_BLOCK_NON_SHARE |
  25. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  26. }, {
  27. .virt = 0x80000000UL,
  28. .phys = 0x80000000UL,
  29. .size = 0x20000000UL,
  30. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  31. PTE_BLOCK_INNER_SHARE
  32. }, {
  33. .virt = 0xa0000000UL,
  34. .phys = 0xa0000000UL,
  35. .size = 0x02100000UL,
  36. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  37. PTE_BLOCK_INNER_SHARE
  38. }, {
  39. .virt = 0xa2100000UL,
  40. .phys = 0xa2100000UL,
  41. .size = 0x5df00000UL,
  42. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  43. PTE_BLOCK_INNER_SHARE
  44. }, {
  45. .virt = 0x880000000UL,
  46. .phys = 0x880000000UL,
  47. .size = 0x80000000UL,
  48. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  49. PTE_BLOCK_INNER_SHARE
  50. }, {
  51. .virt = 0x500000000UL,
  52. .phys = 0x500000000UL,
  53. .size = 0x400000000UL,
  54. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  55. PTE_BLOCK_NON_SHARE |
  56. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  57. }, {
  58. /* List terminator */
  59. 0,
  60. }
  61. };
  62. struct mm_region *mem_map = am654_mem_map;
  63. #endif /* CONFIG_SOC_K3_AM6 */
  64. #ifdef CONFIG_SOC_K3_J721E
  65. #ifdef CONFIG_TARGET_J721E_A72_EVM
  66. /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
  67. #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6)
  68. /* ToDo: Add 64bit IO */
  69. struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
  70. {
  71. .virt = 0x0UL,
  72. .phys = 0x0UL,
  73. .size = 0x80000000UL,
  74. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  75. PTE_BLOCK_NON_SHARE |
  76. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  77. }, {
  78. .virt = 0x80000000UL,
  79. .phys = 0x80000000UL,
  80. .size = 0x20000000UL,
  81. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  82. PTE_BLOCK_INNER_SHARE
  83. }, {
  84. .virt = 0xa0000000UL,
  85. .phys = 0xa0000000UL,
  86. .size = 0x1bc00000UL,
  87. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  88. PTE_BLOCK_NON_SHARE
  89. }, {
  90. .virt = 0xbbc00000UL,
  91. .phys = 0xbbc00000UL,
  92. .size = 0x44400000UL,
  93. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  94. PTE_BLOCK_INNER_SHARE
  95. }, {
  96. .virt = 0x880000000UL,
  97. .phys = 0x880000000UL,
  98. .size = 0x80000000UL,
  99. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  100. PTE_BLOCK_INNER_SHARE
  101. }, {
  102. .virt = 0x500000000UL,
  103. .phys = 0x500000000UL,
  104. .size = 0x400000000UL,
  105. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  106. PTE_BLOCK_NON_SHARE |
  107. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  108. }, {
  109. .virt = 0x4d80000000UL,
  110. .phys = 0x4d80000000UL,
  111. .size = 0x0002000000UL,
  112. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  113. PTE_BLOCK_INNER_SHARE
  114. }, {
  115. /* List terminator */
  116. 0,
  117. }
  118. };
  119. struct mm_region *mem_map = j721e_mem_map;
  120. #endif /* CONFIG_TARGET_J721E_A72_EVM */
  121. #ifdef CONFIG_TARGET_J7200_A72_EVM
  122. #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
  123. /* ToDo: Add 64bit IO */
  124. struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
  125. {
  126. .virt = 0x0UL,
  127. .phys = 0x0UL,
  128. .size = 0x80000000UL,
  129. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  130. PTE_BLOCK_NON_SHARE |
  131. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  132. }, {
  133. .virt = 0x80000000UL,
  134. .phys = 0x80000000UL,
  135. .size = 0x20000000UL,
  136. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  137. PTE_BLOCK_INNER_SHARE
  138. }, {
  139. .virt = 0xa0000000UL,
  140. .phys = 0xa0000000UL,
  141. .size = 0x04800000UL,
  142. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
  143. PTE_BLOCK_NON_SHARE
  144. }, {
  145. .virt = 0xa4800000UL,
  146. .phys = 0xa4800000UL,
  147. .size = 0x5b800000UL,
  148. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  149. PTE_BLOCK_INNER_SHARE
  150. }, {
  151. .virt = 0x880000000UL,
  152. .phys = 0x880000000UL,
  153. .size = 0x80000000UL,
  154. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  155. PTE_BLOCK_INNER_SHARE
  156. }, {
  157. .virt = 0x500000000UL,
  158. .phys = 0x500000000UL,
  159. .size = 0x400000000UL,
  160. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  161. PTE_BLOCK_NON_SHARE |
  162. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  163. }, {
  164. /* List terminator */
  165. 0,
  166. }
  167. };
  168. struct mm_region *mem_map = j7200_mem_map;
  169. #endif /* CONFIG_TARGET_J7200_A72_EVM */
  170. #endif /* CONFIG_SOC_K3_J721E */