clock-ipq4019.c 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Clock drivers for Qualcomm IPQ40xx
  4. *
  5. * Copyright (c) 2019 Sartura Ltd.
  6. *
  7. * Author: Robert Marko <robert.marko@sartura.hr>
  8. *
  9. */
  10. #include <common.h>
  11. #include <clk-uclass.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
  15. struct msm_clk_priv {
  16. phys_addr_t base;
  17. };
  18. ulong msm_set_rate(struct clk *clk, ulong rate)
  19. {
  20. switch (clk->id) {
  21. case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
  22. /* This clock is already initialized by SBL1 */
  23. return 0;
  24. break;
  25. default:
  26. return 0;
  27. }
  28. }
  29. static int msm_clk_probe(struct udevice *dev)
  30. {
  31. struct msm_clk_priv *priv = dev_get_priv(dev);
  32. priv->base = devfdt_get_addr(dev);
  33. if (priv->base == FDT_ADDR_T_NONE)
  34. return -EINVAL;
  35. return 0;
  36. }
  37. static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
  38. {
  39. return msm_set_rate(clk, rate);
  40. }
  41. static struct clk_ops msm_clk_ops = {
  42. .set_rate = msm_clk_set_rate,
  43. };
  44. static const struct udevice_id msm_clk_ids[] = {
  45. { .compatible = "qcom,gcc-ipq4019" },
  46. { }
  47. };
  48. U_BOOT_DRIVER(clk_msm) = {
  49. .name = "clk_msm",
  50. .id = UCLASS_CLK,
  51. .of_match = msm_clk_ids,
  52. .ops = &msm_clk_ops,
  53. .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
  54. .probe = msm_clk_probe,
  55. };