sdram_ast2500.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2012-2020 ASPEED Technology Inc.
  4. *
  5. * Copyright 2016 Google, Inc
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <ram.h>
  13. #include <regmap.h>
  14. #include <reset.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/scu_ast2500.h>
  17. #include <asm/arch/sdram_ast2500.h>
  18. #include <asm/arch/wdt.h>
  19. #include <linux/err.h>
  20. #include <linux/kernel.h>
  21. #include <dt-bindings/clock/aspeed-clock.h>
  22. /* These configuration parameters are taken from Aspeed SDK */
  23. #define DDR4_MR46_MODE 0x08000000
  24. #define DDR4_MR5_MODE 0x400
  25. #define DDR4_MR13_MODE 0x101
  26. #define DDR4_MR02_MODE 0x410
  27. #define DDR4_TRFC 0x45457188
  28. #define PHY_CFG_SIZE 15
  29. static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
  30. static const struct {
  31. u32 index[PHY_CFG_SIZE];
  32. u32 value[PHY_CFG_SIZE];
  33. } ddr4_phy_config = {
  34. .index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
  35. .value = {
  36. 0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
  37. 0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
  38. 0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
  39. },
  40. };
  41. #define SDRAM_MAX_SIZE (1024 * 1024 * 1024)
  42. #define SDRAM_MIN_SIZE (128 * 1024 * 1024)
  43. DECLARE_GLOBAL_DATA_PTR;
  44. /*
  45. * Bandwidth configuration parameters for different SDRAM requests.
  46. * These are hardcoded settings taken from Aspeed SDK.
  47. */
  48. static const u32 ddr_max_grant_params[4] = {
  49. 0x88448844, 0x24422288, 0x22222222, 0x22222222
  50. };
  51. /*
  52. * These registers are not documented by Aspeed at all.
  53. * All writes and reads are taken pretty much as is from SDK.
  54. */
  55. struct ast2500_ddr_phy {
  56. u32 phy[117];
  57. };
  58. struct dram_info {
  59. struct ram_info info;
  60. struct clk ddr_clk;
  61. struct ast2500_sdrammc_regs *regs;
  62. struct ast2500_scu *scu;
  63. struct ast2500_ddr_phy *phy;
  64. ulong clock_rate;
  65. };
  66. static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
  67. {
  68. writel(0, &phy->phy[2]);
  69. writel(0, &phy->phy[6]);
  70. writel(0, &phy->phy[8]);
  71. writel(0, &phy->phy[10]);
  72. writel(0, &phy->phy[12]);
  73. writel(0, &phy->phy[42]);
  74. writel(0, &phy->phy[44]);
  75. writel(0x86000000, &phy->phy[16]);
  76. writel(0x00008600, &phy->phy[17]);
  77. writel(0x80000000, &phy->phy[18]);
  78. writel(0x80808080, &phy->phy[19]);
  79. return 0;
  80. }
  81. static void ast2500_ddr_phy_init_process(struct dram_info *info)
  82. {
  83. struct ast2500_sdrammc_regs *regs = info->regs;
  84. writel(0, &regs->phy_ctrl[0]);
  85. writel(0x4040, &info->phy->phy[51]);
  86. writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
  87. while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
  88. ;
  89. writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
  90. &regs->phy_ctrl[0]);
  91. }
  92. static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
  93. {
  94. writel(0, &info->regs->phy_ctrl[0]);
  95. writel((vref << 8) | 0x6, &info->phy->phy[48]);
  96. ast2500_ddr_phy_init_process(info);
  97. }
  98. static int ast2500_ddr_cbr_test(struct dram_info *info)
  99. {
  100. struct ast2500_sdrammc_regs *regs = info->regs;
  101. int i;
  102. const u32 test_params = SDRAM_TEST_EN
  103. | SDRAM_TEST_ERRSTOP
  104. | SDRAM_TEST_TWO_MODES;
  105. int ret = 0;
  106. writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
  107. (0x5c << SDRAM_REFRESH_PERIOD_SHIFT), &regs->refresh_timing);
  108. writel((0xfff << SDRAM_TEST_LEN_SHIFT), &regs->test_addr);
  109. writel(0xff00ff00, &regs->test_init_val);
  110. writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
  111. SDRAM_TEST_ERRSTOP, &regs->ecc_test_ctrl);
  112. while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
  113. ;
  114. if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
  115. ret = -EIO;
  116. } else {
  117. for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
  118. writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
  119. &regs->ecc_test_ctrl);
  120. while (!(readl(&regs->ecc_test_ctrl) & SDRAM_TEST_DONE))
  121. ;
  122. if (readl(&regs->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
  123. ret = -EIO;
  124. break;
  125. }
  126. }
  127. }
  128. writel(0, &regs->refresh_timing);
  129. writel(0, &regs->ecc_test_ctrl);
  130. return ret;
  131. }
  132. static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
  133. {
  134. int i;
  135. int vref_min = 0xff;
  136. int vref_max = 0;
  137. int range_size = 0;
  138. for (i = 1; i < 0x40; ++i) {
  139. int res;
  140. ast2500_sdrammc_set_vref(info, i);
  141. res = ast2500_ddr_cbr_test(info);
  142. if (res < 0) {
  143. if (range_size > 0)
  144. break;
  145. } else {
  146. ++range_size;
  147. vref_min = min(vref_min, i);
  148. vref_max = max(vref_max, i);
  149. }
  150. }
  151. /* Pick average setting */
  152. ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
  153. return 0;
  154. }
  155. static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
  156. {
  157. size_t vga_mem_size_base = 8 * 1024 * 1024;
  158. u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
  159. >> SCU_HWSTRAP_VGAMEM_SHIFT;
  160. return vga_mem_size_base << vga_hwconf;
  161. }
  162. /*
  163. * Find out RAM size and save it in dram_info
  164. *
  165. * The procedure is taken from Aspeed SDK
  166. */
  167. static void ast2500_sdrammc_calc_size(struct dram_info *info)
  168. {
  169. /* The controller supports 128/256/512/1024 MB ram */
  170. size_t ram_size = SDRAM_MIN_SIZE;
  171. const int write_test_offset = 0x100000;
  172. u32 test_pattern = 0xdeadbeef;
  173. u32 cap_param = SDRAM_CONF_CAP_1024M;
  174. u32 refresh_timing_param = DDR4_TRFC;
  175. const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
  176. for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
  177. ram_size >>= 1) {
  178. writel(test_pattern, write_addr_base + (ram_size >> 1));
  179. test_pattern = (test_pattern >> 4) | (test_pattern << 28);
  180. }
  181. /* One last write to overwrite all wrapped values */
  182. writel(test_pattern, write_addr_base);
  183. /* Reset the pattern and see which value was really written */
  184. test_pattern = 0xdeadbeef;
  185. for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
  186. ram_size >>= 1) {
  187. if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
  188. break;
  189. --cap_param;
  190. refresh_timing_param >>= 8;
  191. test_pattern = (test_pattern >> 4) | (test_pattern << 28);
  192. }
  193. clrsetbits_le32(&info->regs->ac_timing[1],
  194. (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
  195. ((refresh_timing_param & SDRAM_AC_TRFC_MASK)
  196. << SDRAM_AC_TRFC_SHIFT));
  197. info->info.base = CONFIG_SYS_SDRAM_BASE;
  198. info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
  199. clrsetbits_le32(&info->regs->config,
  200. (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
  201. ((cap_param & SDRAM_CONF_CAP_MASK)
  202. << SDRAM_CONF_CAP_SHIFT));
  203. }
  204. static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
  205. {
  206. int i;
  207. const u32 power_control = SDRAM_PCR_CKE_EN
  208. | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
  209. | (2 << SDRAM_PCR_TCKE_PW_SHIFT)
  210. | SDRAM_PCR_RESETN_DIS
  211. | SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
  212. const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
  213. #ifdef CONFIG_DUALX8_RAM
  214. | SDRAM_CONF_DUALX8
  215. #endif
  216. | SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
  217. int ret;
  218. writel(conf, &info->regs->config);
  219. for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
  220. writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
  221. writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
  222. writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
  223. writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
  224. writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
  225. for (i = 0; i < PHY_CFG_SIZE; ++i) {
  226. writel(ddr4_phy_config.value[i],
  227. &info->phy->phy[ddr4_phy_config.index[i]]);
  228. }
  229. writel(power_control, &info->regs->power_control);
  230. ast2500_ddr_phy_init_process(info);
  231. ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
  232. if (ret < 0) {
  233. debug("Vref calibration failed!\n");
  234. return ret;
  235. }
  236. writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
  237. | SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
  238. &info->regs->refresh_timing);
  239. setbits_le32(&info->regs->power_control,
  240. SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);
  241. ast2500_sdrammc_calc_size(info);
  242. setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
  243. while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
  244. ;
  245. setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
  246. writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
  247. /* Enable all requests except video & display */
  248. writel(SDRAM_REQ_USB20_EHCI1
  249. | SDRAM_REQ_USB20_EHCI2
  250. | SDRAM_REQ_CPU
  251. | SDRAM_REQ_AHB2
  252. | SDRAM_REQ_AHB
  253. | SDRAM_REQ_MAC0
  254. | SDRAM_REQ_MAC1
  255. | SDRAM_REQ_PCIE
  256. | SDRAM_REQ_XDMA
  257. | SDRAM_REQ_ENCRYPTION
  258. | SDRAM_REQ_VIDEO_FLAG
  259. | SDRAM_REQ_VIDEO_LOW_PRI_WRITE
  260. | SDRAM_REQ_2D_RW
  261. | SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
  262. return 0;
  263. }
  264. static void ast2500_sdrammc_unlock(struct dram_info *info)
  265. {
  266. writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
  267. while (!readl(&info->regs->protection_key))
  268. ;
  269. }
  270. static void ast2500_sdrammc_lock(struct dram_info *info)
  271. {
  272. writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
  273. while (readl(&info->regs->protection_key))
  274. ;
  275. }
  276. static int ast2500_sdrammc_probe(struct udevice *dev)
  277. {
  278. struct reset_ctl reset_ctl;
  279. struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
  280. struct ast2500_sdrammc_regs *regs = priv->regs;
  281. int i;
  282. int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
  283. if (ret) {
  284. debug("DDR:No CLK\n");
  285. return ret;
  286. }
  287. priv->scu = ast_get_scu();
  288. if (IS_ERR(priv->scu)) {
  289. debug("%s(): can't get SCU\n", __func__);
  290. return PTR_ERR(priv->scu);
  291. }
  292. clk_set_rate(&priv->ddr_clk, priv->clock_rate);
  293. ret = reset_get_by_index(dev, 0, &reset_ctl);
  294. if (ret) {
  295. debug("%s(): Failed to get reset signal\n", __func__);
  296. return ret;
  297. }
  298. ret = reset_assert(&reset_ctl);
  299. if (ret) {
  300. debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
  301. return ret;
  302. }
  303. ast2500_sdrammc_unlock(priv);
  304. writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
  305. &regs->power_control);
  306. writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
  307. /* Mask all requests except CPU and AHB during PHY init */
  308. writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), &regs->req_limit_mask);
  309. for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
  310. writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
  311. setbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
  312. ast2500_sdrammc_init_phy(priv->phy);
  313. if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
  314. ast2500_sdrammc_init_ddr4(priv);
  315. } else {
  316. debug("Unsupported DRAM3\n");
  317. return -EINVAL;
  318. }
  319. clrbits_le32(&regs->intr_ctrl, SDRAM_ICR_RESET_ALL);
  320. ast2500_sdrammc_lock(priv);
  321. return 0;
  322. }
  323. static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
  324. {
  325. struct dram_info *priv = dev_get_priv(dev);
  326. struct regmap *map;
  327. int ret;
  328. ret = regmap_init_mem(dev_ofnode(dev), &map);
  329. if (ret)
  330. return ret;
  331. priv->regs = regmap_get_range(map, 0);
  332. priv->phy = regmap_get_range(map, 1);
  333. priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  334. "clock-frequency", 0);
  335. if (!priv->clock_rate) {
  336. debug("DDR Clock Rate not defined\n");
  337. return -EINVAL;
  338. }
  339. return 0;
  340. }
  341. static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
  342. {
  343. struct dram_info *priv = dev_get_priv(dev);
  344. *info = priv->info;
  345. return 0;
  346. }
  347. static struct ram_ops ast2500_sdrammc_ops = {
  348. .get_info = ast2500_sdrammc_get_info,
  349. };
  350. static const struct udevice_id ast2500_sdrammc_ids[] = {
  351. { .compatible = "aspeed,ast2500-sdrammc" },
  352. { }
  353. };
  354. U_BOOT_DRIVER(sdrammc_ast2500) = {
  355. .name = "aspeed_ast2500_sdrammc",
  356. .id = UCLASS_RAM,
  357. .of_match = ast2500_sdrammc_ids,
  358. .ops = &ast2500_sdrammc_ops,
  359. .ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
  360. .probe = ast2500_sdrammc_probe,
  361. .priv_auto_alloc_size = sizeof(struct dram_info),
  362. };