gic-v3-its.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Broadcom.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <regmap.h>
  8. #include <syscon.h>
  9. #include <asm/gic.h>
  10. #include <asm/gic-v3.h>
  11. #include <asm/io.h>
  12. #include <linux/bitops.h>
  13. #include <linux/sizes.h>
  14. static u32 lpi_id_bits;
  15. #define LPI_NRBITS lpi_id_bits
  16. #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
  17. #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
  18. /* Number of GIC re-distributors */
  19. #define MAX_GIC_REDISTRIBUTORS 8
  20. /*
  21. * gic_v3_its_priv - gic details
  22. *
  23. * @gicd_base: gicd base address
  24. * @gicr_base: gicr base address
  25. * @lpi_base: gic lpi base address
  26. * @num_redist: number of gic re-distributors
  27. */
  28. struct gic_v3_its_priv {
  29. ulong gicd_base;
  30. ulong gicr_base;
  31. ulong lpi_base;
  32. u32 num_redist;
  33. };
  34. static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
  35. {
  36. struct udevice *dev;
  37. fdt_addr_t addr;
  38. int ret;
  39. ret = uclass_get_device_by_driver(UCLASS_IRQ,
  40. DM_GET_DRIVER(arm_gic_v3_its), &dev);
  41. if (ret) {
  42. pr_err("%s: failed to get %s irq device\n", __func__,
  43. DM_GET_DRIVER(arm_gic_v3_its)->name);
  44. return ret;
  45. }
  46. addr = dev_read_addr_index(dev, 0);
  47. if (addr == FDT_ADDR_T_NONE) {
  48. pr_err("%s: failed to get GICD address\n", __func__);
  49. return -EINVAL;
  50. }
  51. priv->gicd_base = addr;
  52. addr = dev_read_addr_index(dev, 1);
  53. if (addr == FDT_ADDR_T_NONE) {
  54. pr_err("%s: failed to get GICR address\n", __func__);
  55. return -EINVAL;
  56. }
  57. priv->gicr_base = addr;
  58. return 0;
  59. }
  60. static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
  61. {
  62. struct regmap *regmap;
  63. struct udevice *dev;
  64. int ret;
  65. ret = uclass_get_device_by_driver(UCLASS_SYSCON,
  66. DM_GET_DRIVER(gic_lpi_syscon), &dev);
  67. if (ret) {
  68. pr_err("%s: failed to get %s syscon device\n", __func__,
  69. DM_GET_DRIVER(gic_lpi_syscon)->name);
  70. return ret;
  71. }
  72. regmap = syscon_get_regmap(dev);
  73. if (!regmap) {
  74. pr_err("%s: failed to regmap for %s syscon device\n", __func__,
  75. DM_GET_DRIVER(gic_lpi_syscon)->name);
  76. return -ENODEV;
  77. }
  78. priv->lpi_base = regmap->ranges[0].start;
  79. priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors",
  80. MAX_GIC_REDISTRIBUTORS);
  81. return 0;
  82. }
  83. /*
  84. * Program the GIC LPI configuration tables for all
  85. * the re-distributors and enable the LPI table
  86. */
  87. int gic_lpi_tables_init(void)
  88. {
  89. struct gic_v3_its_priv priv;
  90. u32 gicd_typer;
  91. u64 val;
  92. u64 tmp;
  93. int i;
  94. u64 redist_lpi_base;
  95. u64 pend_base;
  96. if (gic_v3_its_get_gic_addr(&priv))
  97. return -EINVAL;
  98. if (gic_v3_its_get_gic_lpi_addr(&priv))
  99. return -EINVAL;
  100. gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER));
  101. /* GIC support for Locality specific peripheral interrupts (LPI's) */
  102. if (!(gicd_typer & GICD_TYPER_LPIS)) {
  103. pr_err("GIC implementation does not support LPI's\n");
  104. return -EINVAL;
  105. }
  106. /*
  107. * Check for LPI is disabled for all the redistributors.
  108. * Once the LPI table is enabled, can not program the
  109. * LPI configuration tables again, unless the GIC is reset.
  110. */
  111. for (i = 0; i < priv.num_redist; i++) {
  112. u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
  113. if ((readl((uintptr_t)(priv.gicr_base + offset))) &
  114. GICR_CTLR_ENABLE_LPIS) {
  115. pr_err("Re-Distributor %d LPI is already enabled\n",
  116. i);
  117. return -EINVAL;
  118. }
  119. }
  120. /* lpi_id_bits to get LPI_PENDBASE_SZ and LPi_PROPBASE_SZ */
  121. lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gicd_typer),
  122. ITS_MAX_LPI_NRBITS);
  123. /* Set PropBase */
  124. val = (priv.lpi_base |
  125. GICR_PROPBASER_INNERSHAREABLE |
  126. GICR_PROPBASER_RAWAWB |
  127. ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
  128. writeq(val, (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
  129. tmp = readl((uintptr_t)(priv.gicr_base + GICR_PROPBASER));
  130. if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
  131. if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
  132. val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
  133. GICR_PROPBASER_CACHEABILITY_MASK);
  134. val |= GICR_PROPBASER_NC;
  135. writeq(val,
  136. (uintptr_t)(priv.gicr_base + GICR_PROPBASER));
  137. }
  138. }
  139. redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
  140. pend_base = priv.gicr_base + GICR_PENDBASER;
  141. for (i = 0; i < priv.num_redist; i++) {
  142. u32 offset = i * GIC_REDISTRIBUTOR_OFFSET;
  143. val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
  144. GICR_PENDBASER_INNERSHAREABLE |
  145. GICR_PENDBASER_RAWAWB);
  146. writeq(val, (uintptr_t)(pend_base + offset));
  147. tmp = readq((uintptr_t)(pend_base + offset));
  148. if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
  149. val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
  150. GICR_PENDBASER_CACHEABILITY_MASK);
  151. val |= GICR_PENDBASER_NC;
  152. writeq(val, (uintptr_t)(pend_base + offset));
  153. }
  154. /* Enable LPI for the redistributor */
  155. writel(GICR_CTLR_ENABLE_LPIS,
  156. (uintptr_t)(priv.gicr_base + offset));
  157. }
  158. return 0;
  159. }
  160. static const struct udevice_id gic_v3_its_ids[] = {
  161. { .compatible = "arm,gic-v3" },
  162. {}
  163. };
  164. U_BOOT_DRIVER(arm_gic_v3_its) = {
  165. .name = "gic-v3",
  166. .id = UCLASS_IRQ,
  167. .of_match = gic_v3_its_ids,
  168. };
  169. static const struct udevice_id gic_lpi_syscon_ids[] = {
  170. { .compatible = "gic-lpi-base" },
  171. {}
  172. };
  173. U_BOOT_DRIVER(gic_lpi_syscon) = {
  174. .name = "gic-lpi-base",
  175. .id = UCLASS_SYSCON,
  176. .of_match = gic_lpi_syscon_ids,
  177. };