zynqmp-e-a2197-00-revA.dts 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * dts file for Xilinx Versal a2197 RevA System Controller
  4. *
  5. * (C) Copyright 2019 - 2020, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/phy/phy.h>
  14. / {
  15. model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
  16. compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
  17. "xlnx,zynqmp-a2197", "xlnx,zynqmp";
  18. aliases {
  19. ethernet0 = &gem0;
  20. gpio0 = &gpio;
  21. i2c0 = &i2c0;
  22. i2c1 = &i2c1;
  23. mmc0 = &sdhci1;
  24. rtc0 = &rtc;
  25. serial0 = &uart0;
  26. serial1 = &dcc;
  27. };
  28. chosen {
  29. bootargs = "earlycon";
  30. stdout-path = "serial0:115200n8";
  31. xlnx,eeprom = <&eeprom>;
  32. };
  33. memory@0 {
  34. device_type = "memory";
  35. reg = <0x0 0x0 0x0 0x80000000>;
  36. };
  37. ina226-vccint {
  38. compatible = "iio-hwmon";
  39. io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
  40. };
  41. ina226-vcc-soc {
  42. compatible = "iio-hwmon";
  43. io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
  44. };
  45. ina226-vcc-pmc {
  46. compatible = "iio-hwmon";
  47. io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
  48. };
  49. ina226-vcc-ram {
  50. compatible = "iio-hwmon";
  51. io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
  52. };
  53. ina226-vcc-pslp {
  54. compatible = "iio-hwmon";
  55. io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
  56. };
  57. ina226-vcc-psfp {
  58. compatible = "iio-hwmon";
  59. io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
  60. };
  61. ina226-vccaux {
  62. compatible = "iio-hwmon";
  63. io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
  64. };
  65. ina226-vccaux-pmc {
  66. compatible = "iio-hwmon";
  67. io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
  68. };
  69. ina226-vcco-500 {
  70. compatible = "iio-hwmon";
  71. io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
  72. };
  73. ina226-vcco-501 {
  74. compatible = "iio-hwmon";
  75. io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
  76. };
  77. ina226-vcco-502 {
  78. compatible = "iio-hwmon";
  79. io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
  80. };
  81. ina226-vcco-503 {
  82. compatible = "iio-hwmon";
  83. io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
  84. };
  85. ina226-vcc-1v8 {
  86. compatible = "iio-hwmon";
  87. io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
  88. };
  89. ina226-vcc-3v3 {
  90. compatible = "iio-hwmon";
  91. io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
  92. };
  93. ina226-vcc-1v2-ddr4 {
  94. compatible = "iio-hwmon";
  95. io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
  96. };
  97. ina226-vcc-1v1-lp4 {
  98. compatible = "iio-hwmon";
  99. io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
  100. };
  101. ina226-vadj-fmc {
  102. compatible = "iio-hwmon";
  103. io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
  104. };
  105. ina226-mgtyavcc {
  106. compatible = "iio-hwmon";
  107. io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
  108. };
  109. ina226-mgtyavtt {
  110. compatible = "iio-hwmon";
  111. io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
  112. };
  113. ina226-mgtyvccaux {
  114. compatible = "iio-hwmon";
  115. io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
  116. };
  117. };
  118. &uart0 { /* uart0 MIO38-39 */
  119. status = "okay";
  120. u-boot,dm-pre-reloc;
  121. };
  122. &sdhci1 { /* sd1 MIO45-51 cd in place */
  123. status = "okay";
  124. no-1-8-v;
  125. disable-wp;
  126. xlnx,mio-bank = <1>;
  127. };
  128. &gem0 {
  129. status = "okay";
  130. phy-handle = <&phy0>;
  131. phy-mode = "sgmii";
  132. is-internal-pcspma;
  133. phy0: ethernet-phy@0 { /* u131 M88E1512 */
  134. reg = <0>;
  135. };
  136. };
  137. &gpio {
  138. status = "okay";
  139. gpio-line-names = "", "", "", "", "", /* 0 - 4 */
  140. "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
  141. "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
  142. "", "", "", "", "", /* 15 - 19 */
  143. "", "", "", "", "", /* 20 - 24 */
  144. "", "", "", "", "", /* 25 - 29 */
  145. "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
  146. "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
  147. "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
  148. "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
  149. "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
  150. "", "", "", "", "", /* 55 - 59 */
  151. "", "", "", "", "", /* 60 - 64 */
  152. "", "", "", "", "", /* 65 - 69 */
  153. "", "", "", "", "", /* 70 - 74 */
  154. "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
  155. "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
  156. "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
  157. "", "", "", "", "", /* 85 - 89 */
  158. "", "", "", "", "", /* 90 - 94 */
  159. "", "", "", "", "", /* 95 - 99 */
  160. "", "", "", "", "", /* 100 - 104 */
  161. "", "", "", "", "", /* 105 - 109 */
  162. "", "", "", "", "", /* 110 - 114 */
  163. "", "", "", "", "", /* 115 - 119 */
  164. "", "", "", "", "", /* 120 - 124 */
  165. "", "", "", "", "", /* 125 - 129 */
  166. "", "", "", "", "", /* 130 - 134 */
  167. "", "", "", "", "", /* 135 - 139 */
  168. "", "", "", "", "", /* 140 - 144 */
  169. "", "", "", "", "", /* 145 - 149 */
  170. "", "", "", "", "", /* 150 - 154 */
  171. "", "", "", "", "", /* 155 - 159 */
  172. "", "", "", "", "", /* 160 - 164 */
  173. "", "", "", "", "", /* 165 - 169 */
  174. "", "", "", ""; /* 170 - 174 */
  175. };
  176. &i2c0 { /* MIO 34-35 - can't stay here */
  177. status = "okay";
  178. clock-frequency = <400000>;
  179. i2c-mux@74 { /* u33 */
  180. compatible = "nxp,pca9548";
  181. #address-cells = <1>;
  182. #size-cells = <0>;
  183. reg = <0x74>;
  184. /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
  185. i2c@0 { /* PMBUS */
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. reg = <0>;
  189. /* u152 IR35215 0x16/0x46 vcc_soc */
  190. /* u179 ir38164 0x19/0x49 vcco_500 */
  191. /* u181 ir38164 0x1a/0x4a vcco_501 */
  192. /* u183 ir38164 0x1b/0x4b vcco_502 */
  193. /* u185 ir38164 0x1e/0x4e vadj_fmc */
  194. /* u187 ir38164 0x1F/0x4f mgtyavcc */
  195. /* u189 ir38164 0x20/0x50 mgtyavtt */
  196. /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
  197. /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
  198. irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
  199. compatible = "infineon,irps5401";
  200. reg = <0x47>; /* pmbus / i2c 0x17 */
  201. };
  202. irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
  203. compatible = "infineon,irps5401";
  204. reg = <0x4c>; /* pmbus / i2c 0x1c */
  205. };
  206. irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
  207. compatible = "infineon,irps5401";
  208. reg = <0x4d>; /* pmbus / i2c 0x1d */
  209. };
  210. };
  211. i2c@1 { /* PMBUS1_INA226 */
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. reg = <1>;
  215. /* FIXME check alerts coming to SC */
  216. vccint: ina226@40 { /* u65 */
  217. compatible = "ti,ina226";
  218. #io-channel-cells = <1>;
  219. label = "ina226-vccint";
  220. reg = <0x40>;
  221. shunt-resistor = <500>; /* R440 */
  222. /* 0.80V @ 32A 1 of 6 Phases*/
  223. };
  224. vcc_soc: ina226@41 { /* u161 */
  225. compatible = "ti,ina226";
  226. #io-channel-cells = <1>;
  227. label = "ina226-vcc-soc";
  228. reg = <0x41>;
  229. shunt-resistor = <500>; /* R1702 */
  230. /* 0.80V @ 18A */
  231. };
  232. vcc_pmc: ina226@42 { /* u163 */
  233. compatible = "ti,ina226";
  234. #io-channel-cells = <1>;
  235. label = "ina226-vcc-pmc";
  236. reg = <0x42>;
  237. shunt-resistor = <5000>; /* R1214 */
  238. /* 0.78V @ 500mA */
  239. };
  240. vcc_ram: ina226@43 { /* u162 */
  241. compatible = "ti,ina226";
  242. #io-channel-cells = <1>;
  243. label = "ina226-vcc-ram";
  244. reg = <0x43>;
  245. shunt-resistor = <5000>; /* r1221 */
  246. /* 0.78V @ 4A */
  247. };
  248. vcc_pslp: ina226@44 { /* u165 */
  249. compatible = "ti,ina226";
  250. #io-channel-cells = <1>;
  251. label = "ina226-vcc-pslp";
  252. reg = <0x44>;
  253. shunt-resistor = <5000>; /* R1216 */
  254. /* 0.78V @ 1A */
  255. };
  256. vcc_psfp: ina226@45 { /* u164 */
  257. compatible = "ti,ina226";
  258. #io-channel-cells = <1>;
  259. label = "ina226-vcc-psfp";
  260. reg = <0x45>;
  261. shunt-resistor = <5000>; /* R1219 */
  262. /* 0.78V @ 2A */
  263. };
  264. };
  265. i2c@2 { /* PCIE_CLK */
  266. #address-cells = <1>;
  267. #size-cells = <0>;
  268. reg = <2>;
  269. clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
  270. #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
  271. compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
  272. reg = <0xd8>;
  273. /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
  274. /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
  275. };
  276. };
  277. i2c@3 { /* PMBUS2_INA226 */
  278. #address-cells = <1>;
  279. #size-cells = <0>;
  280. reg = <3>;
  281. /* FIXME check alerts coming to SC */
  282. vccaux: ina226@40 { /* u166 */
  283. compatible = "ti,ina226";
  284. #io-channel-cells = <1>;
  285. label = "ina226-vccaux";
  286. reg = <0x40>;
  287. shunt-resistor = <5000>; /* R382 */
  288. /* 1.5V @ 3A */
  289. };
  290. vccaux_pmc: ina226@41 { /* u168 */
  291. compatible = "ti,ina226";
  292. #io-channel-cells = <1>;
  293. label = "ina226-vccaux-pmc";
  294. reg = <0x41>;
  295. shunt-resistor = <5000>; /* R1246 */
  296. /* 1.5V @ 500mA */
  297. };
  298. vcco_500: ina226@42 { /* u178 */
  299. compatible = "ti,ina226";
  300. #io-channel-cells = <1>;
  301. label = "ina226-vcco-500";
  302. reg = <0x42>;
  303. shunt-resistor = <2000>; /* R1300 */
  304. /* 3.3V @ 5A */
  305. };
  306. vcco_501: ina226@43 { /* u180 */
  307. compatible = "ti,ina226";
  308. #io-channel-cells = <1>;
  309. label = "ina226-vcco-501";
  310. reg = <0x43>;
  311. shunt-resistor = <2000>; /* R1313 */
  312. /* 3.3V @ 5A */
  313. };
  314. vcco_502: ina226@44 { /* u182 */
  315. compatible = "ti,ina226";
  316. #io-channel-cells = <1>;
  317. label = "ina226-vcco-502";
  318. reg = <0x44>;
  319. shunt-resistor = <2000>; /* R1330 */
  320. /* 3.3V @ 5A */
  321. };
  322. vcco_503: ina226@45 { /* u172 */
  323. compatible = "ti,ina226";
  324. #io-channel-cells = <1>;
  325. label = "ina226-vcco-503";
  326. reg = <0x45>;
  327. shunt-resistor = <5000>; /* R1229 */
  328. /* 1.8V @ 2A */
  329. };
  330. vcc_1v8: ina226@46 { /* u173 */
  331. compatible = "ti,ina226";
  332. #io-channel-cells = <1>;
  333. label = "ina226-vcc-1v8";
  334. reg = <0x46>;
  335. shunt-resistor = <5000>; /* R400 */
  336. /* 1.8V @ 6A */
  337. };
  338. vcc_3v3: ina226@47 { /* u174 */
  339. compatible = "ti,ina226";
  340. #io-channel-cells = <1>;
  341. label = "ina226-vcc-3v3";
  342. reg = <0x47>;
  343. shunt-resistor = <5000>; /* R1232 */
  344. /* 3.3V @ 500mA */
  345. };
  346. vcc_1v2_ddr4: ina226@48 { /* u176 */
  347. compatible = "ti,ina226";
  348. #io-channel-cells = <1>;
  349. label = "ina226-vcc-1v2-ddr4";
  350. reg = <0x48>;
  351. shunt-resistor = <5000>; /* R1275 */
  352. /* 1.2V @ 4A */
  353. };
  354. vcc1v1_lp4: ina226@49 { /* u177 */
  355. compatible = "ti,ina226";
  356. #io-channel-cells = <1>;
  357. label = "ina226-vcc1v1-lp4";
  358. reg = <0x49>;
  359. shunt-resistor = <5000>; /* R1286 */
  360. /* 1.1V @ 4A */
  361. };
  362. vadj_fmc: ina226@4a { /* u184 */
  363. compatible = "ti,ina226";
  364. #io-channel-cells = <1>;
  365. label = "ina226-vadj-fmc";
  366. reg = <0x4a>;
  367. shunt-resistor = <2000>; /* R1350 */
  368. /* 1.5V @ 10A */
  369. };
  370. mgtyavcc: ina226@4b { /* u186 */
  371. compatible = "ti,ina226";
  372. #io-channel-cells = <1>;
  373. label = "ina226-mgtyavcc";
  374. reg = <0x4b>;
  375. shunt-resistor = <2000>; /* R1367 */
  376. /* 0.88V @ 6A */
  377. };
  378. mgtyavtt: ina226@4c { /* u188 */
  379. compatible = "ti,ina226";
  380. #io-channel-cells = <1>;
  381. label = "ina226-mgtyavtt";
  382. reg = <0x4c>;
  383. shunt-resistor = <2000>; /* R1384 */
  384. /* 1.2V @ 10A */
  385. };
  386. mgtyvccaux: ina226@4d { /* u234 */
  387. compatible = "ti,ina226";
  388. #io-channel-cells = <1>;
  389. label = "ina226-mgtyvccaux";
  390. reg = <0x4d>;
  391. shunt-resistor = <5000>; /* r1679 */
  392. /* 1.5V @ 500mA */
  393. };
  394. };
  395. i2c@4 { /* LP_I2C_SM */
  396. #address-cells = <1>;
  397. #size-cells = <0>;
  398. reg = <4>;
  399. /* FIXME wires ready but chip is missing */
  400. };
  401. i2c@5 { /* zSFP_SI570 */
  402. #address-cells = <1>;
  403. #size-cells = <0>;
  404. reg = <5>;
  405. si570_zsfp: clock-generator@5d { /* u192 */
  406. #clock-cells = <0>;
  407. compatible = "silabs,si570";
  408. reg = <0x5d>;
  409. temperature-stability = <50>;
  410. factory-fout = <156250000>;
  411. clock-frequency = <156250000>;
  412. clock-output-names = "si570_zsfp_clk";
  413. };
  414. };
  415. i2c@6 { /* USER_SI570_1 */
  416. #address-cells = <1>;
  417. #size-cells = <0>;
  418. reg = <6>;
  419. si570_user1: clock-generator@5d { /* u205 */
  420. #clock-cells = <0>;
  421. compatible = "silabs,si570";
  422. reg = <0x5f>;
  423. temperature-stability = <50>;
  424. factory-fout = <100000000>;
  425. clock-frequency = <100000000>;
  426. clock-output-names = "si570_user1";
  427. };
  428. };
  429. i2c@7 { /* USER_SI570_2 */
  430. #address-cells = <1>;
  431. #size-cells = <0>;
  432. reg = <7>;
  433. /* FIXME wires ready but chip is missing */
  434. };
  435. };
  436. };
  437. &i2c1 { /* i2c1 MIO 36-37 */
  438. status = "okay";
  439. clock-frequency = <400000>;
  440. i2c-mux@74 { /* u35 */
  441. compatible = "nxp,pca9548";
  442. #address-cells = <1>;
  443. #size-cells = <0>;
  444. reg = <0x74>;
  445. /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
  446. dc_i2c: i2c@0 { /* DC_I2C */
  447. #address-cells = <1>;
  448. #size-cells = <0>;
  449. reg = <0>;
  450. /* Use for storing information about SC board */
  451. eeprom: eeprom@54 { /* u34 - m24128 16kB */
  452. compatible = "st,24c128", "atmel,24c128";
  453. reg = <0x54>; /* 0x5c too */
  454. };
  455. si570_ref_clk: clock-generator@5d { /* u32 */
  456. #clock-cells = <0>;
  457. compatible = "silabs,si570";
  458. reg = <0x5d>;
  459. temperature-stability = <50>;
  460. factory-fout = <33333333>;
  461. clock-frequency = <33333333>;
  462. clock-output-names = "ref_clk";
  463. };
  464. /* and connector J212D */
  465. };
  466. fmc1: i2c@1 { /* FMCP1_IIC */
  467. #address-cells = <1>;
  468. #size-cells = <0>;
  469. reg = <1>;
  470. /* FIXME connection to Samtec J51C */
  471. /* expected eeprom 0x50 FMC cards */
  472. };
  473. fmc2: i2c@2 { /* FMCP2_IIC */
  474. #address-cells = <1>;
  475. #size-cells = <0>;
  476. reg = <2>;
  477. /* FIXME connection to Samtec J53C */
  478. /* expected eeprom 0x50 FMC cards */
  479. };
  480. i2c@3 { /* DDR4_DIMM1 */
  481. #address-cells = <1>;
  482. #size-cells = <0>;
  483. reg = <3>;
  484. si570_ddr_dimm1: clock-generator@60 { /* u2 */
  485. #clock-cells = <0>;
  486. compatible = "silabs,si570";
  487. reg = <0x60>;
  488. temperature-stability = <50>;
  489. factory-fout = <200000000>;
  490. clock-frequency = <200000000>;
  491. clock-output-names = "si570_ddrdimm1_clk";
  492. };
  493. };
  494. i2c@4 { /* LPDDR4_SI570_CLK2 */
  495. #address-cells = <1>;
  496. #size-cells = <0>;
  497. reg = <4>;
  498. si570_lpddr4clk2: clock-generator@60 { /* u3 */
  499. #clock-cells = <0>;
  500. compatible = "silabs,si570";
  501. reg = <0x60>;
  502. temperature-stability = <50>;
  503. factory-fout = <200000000>;
  504. clock-frequency = <200000000>;
  505. clock-output-names = "si570_lpddr4_clk2";
  506. };
  507. };
  508. i2c@5 { /* LPDDR4_SI570_CLK1 */
  509. #address-cells = <1>;
  510. #size-cells = <0>;
  511. reg = <5>;
  512. si570_lpddr4clk1: clock-generator@60 { /* u4 */
  513. #clock-cells = <0>;
  514. compatible = "silabs,si570";
  515. reg = <0x60>;
  516. temperature-stability = <50>;
  517. factory-fout = <200000000>;
  518. clock-frequency = <200000000>;
  519. clock-output-names = "si570_lpddr4_clk1";
  520. };
  521. };
  522. i2c@6 { /* HSDP_SI570 */
  523. #address-cells = <1>;
  524. #size-cells = <0>;
  525. reg = <6>;
  526. si570_hsdp: clock-generator@5d { /* u5 */
  527. #clock-cells = <0>;
  528. compatible = "silabs,si570";
  529. reg = <0x5d>;
  530. temperature-stability = <50>;
  531. factory-fout = <156250000>;
  532. clock-frequency = <156250000>;
  533. clock-output-names = "si570_hsdp_clk";
  534. };
  535. };
  536. i2c@7 { /* 8A34001 - U219B and J310 connector */
  537. #address-cells = <1>;
  538. #size-cells = <0>;
  539. reg = <7>;
  540. };
  541. };
  542. i2c-mux@75 { /* u214 */
  543. compatible = "nxp,pca9548";
  544. #address-cells = <1>;
  545. #size-cells = <0>;
  546. reg = <0x75>;
  547. i2c@0 { /* SFP0_IIC */
  548. #address-cells = <1>;
  549. #size-cells = <0>;
  550. reg = <0>;
  551. /* SFP0 */
  552. };
  553. i2c@1 { /* SFP1_IIC */
  554. #address-cells = <1>;
  555. #size-cells = <0>;
  556. reg = <1>;
  557. /* SFP1 */
  558. };
  559. i2c@2 { /* QSFP1_I2C */
  560. #address-cells = <1>;
  561. #size-cells = <0>;
  562. reg = <2>;
  563. /* QSFP1 */
  564. };
  565. /* 3 - 7 unused */
  566. };
  567. };
  568. &xilinx_ams {
  569. status = "okay";
  570. };
  571. &ams_ps {
  572. status = "okay";
  573. };
  574. &ams_pl {
  575. status = "okay";
  576. };