stm32mp151.dtsi 41 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
  4. * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
  5. */
  6. #include <dt-bindings/interrupt-controller/arm-gic.h>
  7. #include <dt-bindings/clock/stm32mp1-clks.h>
  8. #include <dt-bindings/reset/stm32mp1-resets.h>
  9. / {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. cpus {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. cpu0: cpu@0 {
  16. compatible = "arm,cortex-a7";
  17. clock-frequency = <650000000>;
  18. device_type = "cpu";
  19. reg = <0>;
  20. operating-points-v2 = <&cpu0_opp_table>;
  21. nvmem-cells = <&part_number_otp>;
  22. nvmem-cell-names = "part_number";
  23. };
  24. };
  25. cpu0_opp_table: cpu0-opp-table {
  26. compatible = "operating-points-v2";
  27. opp-shared;
  28. opp-650000000 {
  29. opp-hz = /bits/ 64 <650000000>;
  30. opp-microvolt = <1200000>;
  31. opp-supported-hw = <0x1>;
  32. };
  33. opp-800000000 {
  34. opp-hz = /bits/ 64 <800000000>;
  35. opp-microvolt = <1350000>;
  36. opp-supported-hw = <0x2>;
  37. };
  38. };
  39. psci {
  40. compatible = "arm,psci-1.0";
  41. method = "smc";
  42. };
  43. intc: interrupt-controller@a0021000 {
  44. compatible = "arm,cortex-a7-gic";
  45. #interrupt-cells = <3>;
  46. interrupt-controller;
  47. reg = <0xa0021000 0x1000>,
  48. <0xa0022000 0x2000>;
  49. };
  50. timer {
  51. compatible = "arm,armv7-timer";
  52. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  53. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  54. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  55. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  56. interrupt-parent = <&intc>;
  57. };
  58. clocks {
  59. clk_hse: clk-hse {
  60. #clock-cells = <0>;
  61. compatible = "fixed-clock";
  62. clock-frequency = <24000000>;
  63. };
  64. clk_hsi: clk-hsi {
  65. #clock-cells = <0>;
  66. compatible = "fixed-clock";
  67. clock-frequency = <64000000>;
  68. };
  69. clk_lse: clk-lse {
  70. #clock-cells = <0>;
  71. compatible = "fixed-clock";
  72. clock-frequency = <32768>;
  73. };
  74. clk_lsi: clk-lsi {
  75. #clock-cells = <0>;
  76. compatible = "fixed-clock";
  77. clock-frequency = <32000>;
  78. };
  79. clk_csi: clk-csi {
  80. #clock-cells = <0>;
  81. compatible = "fixed-clock";
  82. clock-frequency = <4000000>;
  83. };
  84. };
  85. thermal-zones {
  86. cpu_thermal: cpu-thermal {
  87. polling-delay-passive = <0>;
  88. polling-delay = <0>;
  89. thermal-sensors = <&dts>;
  90. trips {
  91. cpu_alert1: cpu-alert1 {
  92. temperature = <85000>;
  93. hysteresis = <0>;
  94. type = "passive";
  95. };
  96. cpu-crit {
  97. temperature = <120000>;
  98. hysteresis = <0>;
  99. type = "critical";
  100. };
  101. };
  102. cooling-maps {
  103. };
  104. };
  105. };
  106. booster: regulator-booster {
  107. compatible = "st,stm32mp1-booster";
  108. st,syscfg = <&syscfg>;
  109. status = "disabled";
  110. };
  111. soc {
  112. compatible = "simple-bus";
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. interrupt-parent = <&intc>;
  116. ranges;
  117. timers2: timer@40000000 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. compatible = "st,stm32-timers";
  121. reg = <0x40000000 0x400>;
  122. clocks = <&rcc TIM2_K>;
  123. clock-names = "int";
  124. dmas = <&dmamux1 18 0x400 0x1>,
  125. <&dmamux1 19 0x400 0x1>,
  126. <&dmamux1 20 0x400 0x1>,
  127. <&dmamux1 21 0x400 0x1>,
  128. <&dmamux1 22 0x400 0x1>;
  129. dma-names = "ch1", "ch2", "ch3", "ch4", "up";
  130. status = "disabled";
  131. pwm {
  132. compatible = "st,stm32-pwm";
  133. #pwm-cells = <3>;
  134. status = "disabled";
  135. };
  136. timer@1 {
  137. compatible = "st,stm32h7-timer-trigger";
  138. reg = <1>;
  139. status = "disabled";
  140. };
  141. counter {
  142. compatible = "st,stm32-timer-counter";
  143. status = "disabled";
  144. };
  145. };
  146. timers3: timer@40001000 {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. compatible = "st,stm32-timers";
  150. reg = <0x40001000 0x400>;
  151. clocks = <&rcc TIM3_K>;
  152. clock-names = "int";
  153. dmas = <&dmamux1 23 0x400 0x1>,
  154. <&dmamux1 24 0x400 0x1>,
  155. <&dmamux1 25 0x400 0x1>,
  156. <&dmamux1 26 0x400 0x1>,
  157. <&dmamux1 27 0x400 0x1>,
  158. <&dmamux1 28 0x400 0x1>;
  159. dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
  160. status = "disabled";
  161. pwm {
  162. compatible = "st,stm32-pwm";
  163. #pwm-cells = <3>;
  164. status = "disabled";
  165. };
  166. timer@2 {
  167. compatible = "st,stm32h7-timer-trigger";
  168. reg = <2>;
  169. status = "disabled";
  170. };
  171. counter {
  172. compatible = "st,stm32-timer-counter";
  173. status = "disabled";
  174. };
  175. };
  176. timers4: timer@40002000 {
  177. #address-cells = <1>;
  178. #size-cells = <0>;
  179. compatible = "st,stm32-timers";
  180. reg = <0x40002000 0x400>;
  181. clocks = <&rcc TIM4_K>;
  182. clock-names = "int";
  183. dmas = <&dmamux1 29 0x400 0x1>,
  184. <&dmamux1 30 0x400 0x1>,
  185. <&dmamux1 31 0x400 0x1>,
  186. <&dmamux1 32 0x400 0x1>;
  187. dma-names = "ch1", "ch2", "ch3", "ch4";
  188. status = "disabled";
  189. pwm {
  190. compatible = "st,stm32-pwm";
  191. #pwm-cells = <3>;
  192. status = "disabled";
  193. };
  194. timer@3 {
  195. compatible = "st,stm32h7-timer-trigger";
  196. reg = <3>;
  197. status = "disabled";
  198. };
  199. counter {
  200. compatible = "st,stm32-timer-counter";
  201. status = "disabled";
  202. };
  203. };
  204. timers5: timer@40003000 {
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. compatible = "st,stm32-timers";
  208. reg = <0x40003000 0x400>;
  209. clocks = <&rcc TIM5_K>;
  210. clock-names = "int";
  211. dmas = <&dmamux1 55 0x400 0x1>,
  212. <&dmamux1 56 0x400 0x1>,
  213. <&dmamux1 57 0x400 0x1>,
  214. <&dmamux1 58 0x400 0x1>,
  215. <&dmamux1 59 0x400 0x1>,
  216. <&dmamux1 60 0x400 0x1>;
  217. dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
  218. status = "disabled";
  219. pwm {
  220. compatible = "st,stm32-pwm";
  221. #pwm-cells = <3>;
  222. status = "disabled";
  223. };
  224. timer@4 {
  225. compatible = "st,stm32h7-timer-trigger";
  226. reg = <4>;
  227. status = "disabled";
  228. };
  229. counter {
  230. compatible = "st,stm32-timer-counter";
  231. status = "disabled";
  232. };
  233. };
  234. timers6: timer@40004000 {
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. compatible = "st,stm32-timers";
  238. reg = <0x40004000 0x400>;
  239. clocks = <&rcc TIM6_K>;
  240. clock-names = "int";
  241. dmas = <&dmamux1 69 0x400 0x1>;
  242. dma-names = "up";
  243. status = "disabled";
  244. timer@5 {
  245. compatible = "st,stm32h7-timer-trigger";
  246. reg = <5>;
  247. status = "disabled";
  248. };
  249. };
  250. timers7: timer@40005000 {
  251. #address-cells = <1>;
  252. #size-cells = <0>;
  253. compatible = "st,stm32-timers";
  254. reg = <0x40005000 0x400>;
  255. clocks = <&rcc TIM7_K>;
  256. clock-names = "int";
  257. dmas = <&dmamux1 70 0x400 0x1>;
  258. dma-names = "up";
  259. status = "disabled";
  260. timer@6 {
  261. compatible = "st,stm32h7-timer-trigger";
  262. reg = <6>;
  263. status = "disabled";
  264. };
  265. };
  266. timers12: timer@40006000 {
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. compatible = "st,stm32-timers";
  270. reg = <0x40006000 0x400>;
  271. clocks = <&rcc TIM12_K>;
  272. clock-names = "int";
  273. status = "disabled";
  274. pwm {
  275. compatible = "st,stm32-pwm";
  276. #pwm-cells = <3>;
  277. status = "disabled";
  278. };
  279. timer@11 {
  280. compatible = "st,stm32h7-timer-trigger";
  281. reg = <11>;
  282. status = "disabled";
  283. };
  284. };
  285. timers13: timer@40007000 {
  286. #address-cells = <1>;
  287. #size-cells = <0>;
  288. compatible = "st,stm32-timers";
  289. reg = <0x40007000 0x400>;
  290. clocks = <&rcc TIM13_K>;
  291. clock-names = "int";
  292. status = "disabled";
  293. pwm {
  294. compatible = "st,stm32-pwm";
  295. #pwm-cells = <3>;
  296. status = "disabled";
  297. };
  298. timer@12 {
  299. compatible = "st,stm32h7-timer-trigger";
  300. reg = <12>;
  301. status = "disabled";
  302. };
  303. };
  304. timers14: timer@40008000 {
  305. #address-cells = <1>;
  306. #size-cells = <0>;
  307. compatible = "st,stm32-timers";
  308. reg = <0x40008000 0x400>;
  309. clocks = <&rcc TIM14_K>;
  310. clock-names = "int";
  311. status = "disabled";
  312. pwm {
  313. compatible = "st,stm32-pwm";
  314. #pwm-cells = <3>;
  315. status = "disabled";
  316. };
  317. timer@13 {
  318. compatible = "st,stm32h7-timer-trigger";
  319. reg = <13>;
  320. status = "disabled";
  321. };
  322. };
  323. lptimer1: timer@40009000 {
  324. #address-cells = <1>;
  325. #size-cells = <0>;
  326. compatible = "st,stm32-lptimer";
  327. reg = <0x40009000 0x400>;
  328. clocks = <&rcc LPTIM1_K>;
  329. clock-names = "mux";
  330. status = "disabled";
  331. pwm {
  332. compatible = "st,stm32-pwm-lp";
  333. #pwm-cells = <3>;
  334. status = "disabled";
  335. };
  336. trigger@0 {
  337. compatible = "st,stm32-lptimer-trigger";
  338. reg = <0>;
  339. status = "disabled";
  340. };
  341. counter {
  342. compatible = "st,stm32-lptimer-counter";
  343. status = "disabled";
  344. };
  345. };
  346. spi2: spi@4000b000 {
  347. #address-cells = <1>;
  348. #size-cells = <0>;
  349. compatible = "st,stm32h7-spi";
  350. reg = <0x4000b000 0x400>;
  351. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  352. clocks = <&rcc SPI2_K>;
  353. resets = <&rcc SPI2_R>;
  354. dmas = <&dmamux1 39 0x400 0x05>,
  355. <&dmamux1 40 0x400 0x05>;
  356. dma-names = "rx", "tx";
  357. status = "disabled";
  358. };
  359. i2s2: audio-controller@4000b000 {
  360. compatible = "st,stm32h7-i2s";
  361. #sound-dai-cells = <0>;
  362. reg = <0x4000b000 0x400>;
  363. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  364. dmas = <&dmamux1 39 0x400 0x01>,
  365. <&dmamux1 40 0x400 0x01>;
  366. dma-names = "rx", "tx";
  367. status = "disabled";
  368. };
  369. spi3: spi@4000c000 {
  370. #address-cells = <1>;
  371. #size-cells = <0>;
  372. compatible = "st,stm32h7-spi";
  373. reg = <0x4000c000 0x400>;
  374. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  375. clocks = <&rcc SPI3_K>;
  376. resets = <&rcc SPI3_R>;
  377. dmas = <&dmamux1 61 0x400 0x05>,
  378. <&dmamux1 62 0x400 0x05>;
  379. dma-names = "rx", "tx";
  380. status = "disabled";
  381. };
  382. i2s3: audio-controller@4000c000 {
  383. compatible = "st,stm32h7-i2s";
  384. #sound-dai-cells = <0>;
  385. reg = <0x4000c000 0x400>;
  386. interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
  387. dmas = <&dmamux1 61 0x400 0x01>,
  388. <&dmamux1 62 0x400 0x01>;
  389. dma-names = "rx", "tx";
  390. status = "disabled";
  391. };
  392. spdifrx: audio-controller@4000d000 {
  393. compatible = "st,stm32h7-spdifrx";
  394. #sound-dai-cells = <0>;
  395. reg = <0x4000d000 0x400>;
  396. clocks = <&rcc SPDIF_K>;
  397. clock-names = "kclk";
  398. interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  399. dmas = <&dmamux1 93 0x400 0x01>,
  400. <&dmamux1 94 0x400 0x01>;
  401. dma-names = "rx", "rx-ctrl";
  402. status = "disabled";
  403. };
  404. usart2: serial@4000e000 {
  405. compatible = "st,stm32h7-uart";
  406. reg = <0x4000e000 0x400>;
  407. interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  408. clocks = <&rcc USART2_K>;
  409. status = "disabled";
  410. };
  411. usart3: serial@4000f000 {
  412. compatible = "st,stm32h7-uart";
  413. reg = <0x4000f000 0x400>;
  414. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  415. clocks = <&rcc USART3_K>;
  416. status = "disabled";
  417. };
  418. uart4: serial@40010000 {
  419. compatible = "st,stm32h7-uart";
  420. reg = <0x40010000 0x400>;
  421. interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  422. clocks = <&rcc UART4_K>;
  423. status = "disabled";
  424. };
  425. uart5: serial@40011000 {
  426. compatible = "st,stm32h7-uart";
  427. reg = <0x40011000 0x400>;
  428. interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  429. clocks = <&rcc UART5_K>;
  430. status = "disabled";
  431. };
  432. i2c1: i2c@40012000 {
  433. compatible = "st,stm32mp15-i2c";
  434. reg = <0x40012000 0x400>;
  435. interrupt-names = "event", "error";
  436. interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
  437. <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  438. clocks = <&rcc I2C1_K>;
  439. resets = <&rcc I2C1_R>;
  440. #address-cells = <1>;
  441. #size-cells = <0>;
  442. st,syscfg-fmp = <&syscfg 0x4 0x1>;
  443. wakeup-source;
  444. status = "disabled";
  445. };
  446. i2c2: i2c@40013000 {
  447. compatible = "st,stm32mp15-i2c";
  448. reg = <0x40013000 0x400>;
  449. interrupt-names = "event", "error";
  450. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  451. <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  452. clocks = <&rcc I2C2_K>;
  453. resets = <&rcc I2C2_R>;
  454. #address-cells = <1>;
  455. #size-cells = <0>;
  456. st,syscfg-fmp = <&syscfg 0x4 0x2>;
  457. wakeup-source;
  458. status = "disabled";
  459. };
  460. i2c3: i2c@40014000 {
  461. compatible = "st,stm32mp15-i2c";
  462. reg = <0x40014000 0x400>;
  463. interrupt-names = "event", "error";
  464. interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  465. <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  466. clocks = <&rcc I2C3_K>;
  467. resets = <&rcc I2C3_R>;
  468. #address-cells = <1>;
  469. #size-cells = <0>;
  470. st,syscfg-fmp = <&syscfg 0x4 0x4>;
  471. wakeup-source;
  472. status = "disabled";
  473. };
  474. i2c5: i2c@40015000 {
  475. compatible = "st,stm32mp15-i2c";
  476. reg = <0x40015000 0x400>;
  477. interrupt-names = "event", "error";
  478. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
  479. <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  480. clocks = <&rcc I2C5_K>;
  481. resets = <&rcc I2C5_R>;
  482. #address-cells = <1>;
  483. #size-cells = <0>;
  484. st,syscfg-fmp = <&syscfg 0x4 0x10>;
  485. wakeup-source;
  486. status = "disabled";
  487. };
  488. cec: cec@40016000 {
  489. compatible = "st,stm32-cec";
  490. reg = <0x40016000 0x400>;
  491. interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  492. clocks = <&rcc CEC_K>, <&clk_lse>;
  493. clock-names = "cec", "hdmi-cec";
  494. status = "disabled";
  495. };
  496. dac: dac@40017000 {
  497. compatible = "st,stm32h7-dac-core";
  498. reg = <0x40017000 0x400>;
  499. clocks = <&rcc DAC12>;
  500. clock-names = "pclk";
  501. #address-cells = <1>;
  502. #size-cells = <0>;
  503. status = "disabled";
  504. dac1: dac@1 {
  505. compatible = "st,stm32-dac";
  506. #io-channel-cells = <1>;
  507. reg = <1>;
  508. status = "disabled";
  509. };
  510. dac2: dac@2 {
  511. compatible = "st,stm32-dac";
  512. #io-channel-cells = <1>;
  513. reg = <2>;
  514. status = "disabled";
  515. };
  516. };
  517. uart7: serial@40018000 {
  518. compatible = "st,stm32h7-uart";
  519. reg = <0x40018000 0x400>;
  520. interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  521. clocks = <&rcc UART7_K>;
  522. status = "disabled";
  523. };
  524. uart8: serial@40019000 {
  525. compatible = "st,stm32h7-uart";
  526. reg = <0x40019000 0x400>;
  527. interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  528. clocks = <&rcc UART8_K>;
  529. status = "disabled";
  530. };
  531. timers1: timer@44000000 {
  532. #address-cells = <1>;
  533. #size-cells = <0>;
  534. compatible = "st,stm32-timers";
  535. reg = <0x44000000 0x400>;
  536. clocks = <&rcc TIM1_K>;
  537. clock-names = "int";
  538. dmas = <&dmamux1 11 0x400 0x1>,
  539. <&dmamux1 12 0x400 0x1>,
  540. <&dmamux1 13 0x400 0x1>,
  541. <&dmamux1 14 0x400 0x1>,
  542. <&dmamux1 15 0x400 0x1>,
  543. <&dmamux1 16 0x400 0x1>,
  544. <&dmamux1 17 0x400 0x1>;
  545. dma-names = "ch1", "ch2", "ch3", "ch4",
  546. "up", "trig", "com";
  547. status = "disabled";
  548. pwm {
  549. compatible = "st,stm32-pwm";
  550. #pwm-cells = <3>;
  551. status = "disabled";
  552. };
  553. timer@0 {
  554. compatible = "st,stm32h7-timer-trigger";
  555. reg = <0>;
  556. status = "disabled";
  557. };
  558. counter {
  559. compatible = "st,stm32-timer-counter";
  560. status = "disabled";
  561. };
  562. };
  563. timers8: timer@44001000 {
  564. #address-cells = <1>;
  565. #size-cells = <0>;
  566. compatible = "st,stm32-timers";
  567. reg = <0x44001000 0x400>;
  568. clocks = <&rcc TIM8_K>;
  569. clock-names = "int";
  570. dmas = <&dmamux1 47 0x400 0x1>,
  571. <&dmamux1 48 0x400 0x1>,
  572. <&dmamux1 49 0x400 0x1>,
  573. <&dmamux1 50 0x400 0x1>,
  574. <&dmamux1 51 0x400 0x1>,
  575. <&dmamux1 52 0x400 0x1>,
  576. <&dmamux1 53 0x400 0x1>;
  577. dma-names = "ch1", "ch2", "ch3", "ch4",
  578. "up", "trig", "com";
  579. status = "disabled";
  580. pwm {
  581. compatible = "st,stm32-pwm";
  582. #pwm-cells = <3>;
  583. status = "disabled";
  584. };
  585. timer@7 {
  586. compatible = "st,stm32h7-timer-trigger";
  587. reg = <7>;
  588. status = "disabled";
  589. };
  590. counter {
  591. compatible = "st,stm32-timer-counter";
  592. status = "disabled";
  593. };
  594. };
  595. usart6: serial@44003000 {
  596. compatible = "st,stm32h7-uart";
  597. reg = <0x44003000 0x400>;
  598. interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  599. clocks = <&rcc USART6_K>;
  600. status = "disabled";
  601. };
  602. spi1: spi@44004000 {
  603. #address-cells = <1>;
  604. #size-cells = <0>;
  605. compatible = "st,stm32h7-spi";
  606. reg = <0x44004000 0x400>;
  607. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  608. clocks = <&rcc SPI1_K>;
  609. resets = <&rcc SPI1_R>;
  610. dmas = <&dmamux1 37 0x400 0x05>,
  611. <&dmamux1 38 0x400 0x05>;
  612. dma-names = "rx", "tx";
  613. status = "disabled";
  614. };
  615. i2s1: audio-controller@44004000 {
  616. compatible = "st,stm32h7-i2s";
  617. #sound-dai-cells = <0>;
  618. reg = <0x44004000 0x400>;
  619. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  620. dmas = <&dmamux1 37 0x400 0x01>,
  621. <&dmamux1 38 0x400 0x01>;
  622. dma-names = "rx", "tx";
  623. status = "disabled";
  624. };
  625. spi4: spi@44005000 {
  626. #address-cells = <1>;
  627. #size-cells = <0>;
  628. compatible = "st,stm32h7-spi";
  629. reg = <0x44005000 0x400>;
  630. interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  631. clocks = <&rcc SPI4_K>;
  632. resets = <&rcc SPI4_R>;
  633. dmas = <&dmamux1 83 0x400 0x05>,
  634. <&dmamux1 84 0x400 0x05>;
  635. dma-names = "rx", "tx";
  636. status = "disabled";
  637. };
  638. timers15: timer@44006000 {
  639. #address-cells = <1>;
  640. #size-cells = <0>;
  641. compatible = "st,stm32-timers";
  642. reg = <0x44006000 0x400>;
  643. clocks = <&rcc TIM15_K>;
  644. clock-names = "int";
  645. dmas = <&dmamux1 105 0x400 0x1>,
  646. <&dmamux1 106 0x400 0x1>,
  647. <&dmamux1 107 0x400 0x1>,
  648. <&dmamux1 108 0x400 0x1>;
  649. dma-names = "ch1", "up", "trig", "com";
  650. status = "disabled";
  651. pwm {
  652. compatible = "st,stm32-pwm";
  653. #pwm-cells = <3>;
  654. status = "disabled";
  655. };
  656. timer@14 {
  657. compatible = "st,stm32h7-timer-trigger";
  658. reg = <14>;
  659. status = "disabled";
  660. };
  661. };
  662. timers16: timer@44007000 {
  663. #address-cells = <1>;
  664. #size-cells = <0>;
  665. compatible = "st,stm32-timers";
  666. reg = <0x44007000 0x400>;
  667. clocks = <&rcc TIM16_K>;
  668. clock-names = "int";
  669. dmas = <&dmamux1 109 0x400 0x1>,
  670. <&dmamux1 110 0x400 0x1>;
  671. dma-names = "ch1", "up";
  672. status = "disabled";
  673. pwm {
  674. compatible = "st,stm32-pwm";
  675. #pwm-cells = <3>;
  676. status = "disabled";
  677. };
  678. timer@15 {
  679. compatible = "st,stm32h7-timer-trigger";
  680. reg = <15>;
  681. status = "disabled";
  682. };
  683. };
  684. timers17: timer@44008000 {
  685. #address-cells = <1>;
  686. #size-cells = <0>;
  687. compatible = "st,stm32-timers";
  688. reg = <0x44008000 0x400>;
  689. clocks = <&rcc TIM17_K>;
  690. clock-names = "int";
  691. dmas = <&dmamux1 111 0x400 0x1>,
  692. <&dmamux1 112 0x400 0x1>;
  693. dma-names = "ch1", "up";
  694. status = "disabled";
  695. pwm {
  696. compatible = "st,stm32-pwm";
  697. #pwm-cells = <3>;
  698. status = "disabled";
  699. };
  700. timer@16 {
  701. compatible = "st,stm32h7-timer-trigger";
  702. reg = <16>;
  703. status = "disabled";
  704. };
  705. };
  706. spi5: spi@44009000 {
  707. #address-cells = <1>;
  708. #size-cells = <0>;
  709. compatible = "st,stm32h7-spi";
  710. reg = <0x44009000 0x400>;
  711. interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  712. clocks = <&rcc SPI5_K>;
  713. resets = <&rcc SPI5_R>;
  714. dmas = <&dmamux1 85 0x400 0x05>,
  715. <&dmamux1 86 0x400 0x05>;
  716. dma-names = "rx", "tx";
  717. status = "disabled";
  718. };
  719. sai1: sai@4400a000 {
  720. compatible = "st,stm32h7-sai";
  721. #address-cells = <1>;
  722. #size-cells = <1>;
  723. ranges = <0 0x4400a000 0x400>;
  724. reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
  725. interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  726. resets = <&rcc SAI1_R>;
  727. status = "disabled";
  728. sai1a: audio-controller@4400a004 {
  729. #sound-dai-cells = <0>;
  730. compatible = "st,stm32-sai-sub-a";
  731. reg = <0x4 0x1c>;
  732. clocks = <&rcc SAI1_K>;
  733. clock-names = "sai_ck";
  734. dmas = <&dmamux1 87 0x400 0x01>;
  735. status = "disabled";
  736. };
  737. sai1b: audio-controller@4400a024 {
  738. #sound-dai-cells = <0>;
  739. compatible = "st,stm32-sai-sub-b";
  740. reg = <0x24 0x1c>;
  741. clocks = <&rcc SAI1_K>;
  742. clock-names = "sai_ck";
  743. dmas = <&dmamux1 88 0x400 0x01>;
  744. status = "disabled";
  745. };
  746. };
  747. sai2: sai@4400b000 {
  748. compatible = "st,stm32h7-sai";
  749. #address-cells = <1>;
  750. #size-cells = <1>;
  751. ranges = <0 0x4400b000 0x400>;
  752. reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
  753. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  754. resets = <&rcc SAI2_R>;
  755. status = "disabled";
  756. sai2a: audio-controller@4400b004 {
  757. #sound-dai-cells = <0>;
  758. compatible = "st,stm32-sai-sub-a";
  759. reg = <0x4 0x1c>;
  760. clocks = <&rcc SAI2_K>;
  761. clock-names = "sai_ck";
  762. dmas = <&dmamux1 89 0x400 0x01>;
  763. status = "disabled";
  764. };
  765. sai2b: audio-controller@4400b024 {
  766. #sound-dai-cells = <0>;
  767. compatible = "st,stm32-sai-sub-b";
  768. reg = <0x24 0x1c>;
  769. clocks = <&rcc SAI2_K>;
  770. clock-names = "sai_ck";
  771. dmas = <&dmamux1 90 0x400 0x01>;
  772. status = "disabled";
  773. };
  774. };
  775. sai3: sai@4400c000 {
  776. compatible = "st,stm32h7-sai";
  777. #address-cells = <1>;
  778. #size-cells = <1>;
  779. ranges = <0 0x4400c000 0x400>;
  780. reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
  781. interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  782. resets = <&rcc SAI3_R>;
  783. status = "disabled";
  784. sai3a: audio-controller@4400c004 {
  785. #sound-dai-cells = <0>;
  786. compatible = "st,stm32-sai-sub-a";
  787. reg = <0x04 0x1c>;
  788. clocks = <&rcc SAI3_K>;
  789. clock-names = "sai_ck";
  790. dmas = <&dmamux1 113 0x400 0x01>;
  791. status = "disabled";
  792. };
  793. sai3b: audio-controller@4400c024 {
  794. #sound-dai-cells = <0>;
  795. compatible = "st,stm32-sai-sub-b";
  796. reg = <0x24 0x1c>;
  797. clocks = <&rcc SAI3_K>;
  798. clock-names = "sai_ck";
  799. dmas = <&dmamux1 114 0x400 0x01>;
  800. status = "disabled";
  801. };
  802. };
  803. dfsdm: dfsdm@4400d000 {
  804. compatible = "st,stm32mp1-dfsdm";
  805. reg = <0x4400d000 0x800>;
  806. clocks = <&rcc DFSDM_K>;
  807. clock-names = "dfsdm";
  808. #address-cells = <1>;
  809. #size-cells = <0>;
  810. status = "disabled";
  811. dfsdm0: filter@0 {
  812. compatible = "st,stm32-dfsdm-adc";
  813. #io-channel-cells = <1>;
  814. reg = <0>;
  815. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  816. dmas = <&dmamux1 101 0x400 0x01>;
  817. dma-names = "rx";
  818. status = "disabled";
  819. };
  820. dfsdm1: filter@1 {
  821. compatible = "st,stm32-dfsdm-adc";
  822. #io-channel-cells = <1>;
  823. reg = <1>;
  824. interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
  825. dmas = <&dmamux1 102 0x400 0x01>;
  826. dma-names = "rx";
  827. status = "disabled";
  828. };
  829. dfsdm2: filter@2 {
  830. compatible = "st,stm32-dfsdm-adc";
  831. #io-channel-cells = <1>;
  832. reg = <2>;
  833. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  834. dmas = <&dmamux1 103 0x400 0x01>;
  835. dma-names = "rx";
  836. status = "disabled";
  837. };
  838. dfsdm3: filter@3 {
  839. compatible = "st,stm32-dfsdm-adc";
  840. #io-channel-cells = <1>;
  841. reg = <3>;
  842. interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  843. dmas = <&dmamux1 104 0x400 0x01>;
  844. dma-names = "rx";
  845. status = "disabled";
  846. };
  847. dfsdm4: filter@4 {
  848. compatible = "st,stm32-dfsdm-adc";
  849. #io-channel-cells = <1>;
  850. reg = <4>;
  851. interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  852. dmas = <&dmamux1 91 0x400 0x01>;
  853. dma-names = "rx";
  854. status = "disabled";
  855. };
  856. dfsdm5: filter@5 {
  857. compatible = "st,stm32-dfsdm-adc";
  858. #io-channel-cells = <1>;
  859. reg = <5>;
  860. interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
  861. dmas = <&dmamux1 92 0x400 0x01>;
  862. dma-names = "rx";
  863. status = "disabled";
  864. };
  865. };
  866. dma1: dma-controller@48000000 {
  867. compatible = "st,stm32-dma";
  868. reg = <0x48000000 0x400>;
  869. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  870. <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  871. <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  872. <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  873. <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  874. <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  875. <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  876. <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
  877. clocks = <&rcc DMA1>;
  878. resets = <&rcc DMA1_R>;
  879. #dma-cells = <4>;
  880. st,mem2mem;
  881. dma-requests = <8>;
  882. };
  883. dma2: dma-controller@48001000 {
  884. compatible = "st,stm32-dma";
  885. reg = <0x48001000 0x400>;
  886. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  887. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  888. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  889. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  890. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  891. <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  892. <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
  893. <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  894. clocks = <&rcc DMA2>;
  895. resets = <&rcc DMA2_R>;
  896. #dma-cells = <4>;
  897. st,mem2mem;
  898. dma-requests = <8>;
  899. };
  900. dmamux1: dma-router@48002000 {
  901. compatible = "st,stm32h7-dmamux";
  902. reg = <0x48002000 0x1c>;
  903. #dma-cells = <3>;
  904. dma-requests = <128>;
  905. dma-masters = <&dma1 &dma2>;
  906. dma-channels = <16>;
  907. clocks = <&rcc DMAMUX>;
  908. resets = <&rcc DMAMUX_R>;
  909. };
  910. adc: adc@48003000 {
  911. compatible = "st,stm32mp1-adc-core";
  912. reg = <0x48003000 0x400>;
  913. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  914. <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  915. clocks = <&rcc ADC12>, <&rcc ADC12_K>;
  916. clock-names = "bus", "adc";
  917. interrupt-controller;
  918. st,syscfg = <&syscfg>;
  919. #interrupt-cells = <1>;
  920. #address-cells = <1>;
  921. #size-cells = <0>;
  922. status = "disabled";
  923. adc1: adc@0 {
  924. compatible = "st,stm32mp1-adc";
  925. #io-channel-cells = <1>;
  926. reg = <0x0>;
  927. interrupt-parent = <&adc>;
  928. interrupts = <0>;
  929. dmas = <&dmamux1 9 0x400 0x01>;
  930. dma-names = "rx";
  931. status = "disabled";
  932. };
  933. adc2: adc@100 {
  934. compatible = "st,stm32mp1-adc";
  935. #io-channel-cells = <1>;
  936. reg = <0x100>;
  937. interrupt-parent = <&adc>;
  938. interrupts = <1>;
  939. dmas = <&dmamux1 10 0x400 0x01>;
  940. dma-names = "rx";
  941. status = "disabled";
  942. };
  943. };
  944. sdmmc3: sdmmc@48004000 {
  945. compatible = "arm,pl18x", "arm,primecell";
  946. arm,primecell-periphid = <0x10153180>;
  947. reg = <0x48004000 0x400>;
  948. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
  949. interrupt-names = "cmd_irq";
  950. clocks = <&rcc SDMMC3_K>;
  951. clock-names = "apb_pclk";
  952. resets = <&rcc SDMMC3_R>;
  953. cap-sd-highspeed;
  954. cap-mmc-highspeed;
  955. max-frequency = <120000000>;
  956. status = "disabled";
  957. };
  958. usbotg_hs: usb-otg@49000000 {
  959. compatible = "st,stm32mp15-hsotg", "snps,dwc2";
  960. reg = <0x49000000 0x10000>;
  961. clocks = <&rcc USBO_K>;
  962. clock-names = "otg";
  963. resets = <&rcc USBO_R>;
  964. reset-names = "dwc2";
  965. interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  966. g-rx-fifo-size = <256>;
  967. g-np-tx-fifo-size = <32>;
  968. g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
  969. dr_mode = "otg";
  970. usb33d-supply = <&usb33>;
  971. status = "disabled";
  972. };
  973. hwspinlock: hwspinlock@4c000000 {
  974. compatible = "st,stm32-hwspinlock";
  975. #hwlock-cells = <1>;
  976. reg = <0x4c000000 0x400>;
  977. clocks = <&rcc HSEM>;
  978. clock-names = "hwspinlock";
  979. };
  980. ipcc: mailbox@4c001000 {
  981. compatible = "st,stm32mp1-ipcc";
  982. #mbox-cells = <1>;
  983. reg = <0x4c001000 0x400>;
  984. st,proc-id = <0>;
  985. interrupts-extended =
  986. <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  987. <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
  988. <&exti 61 1>;
  989. interrupt-names = "rx", "tx", "wakeup";
  990. clocks = <&rcc IPCC>;
  991. wakeup-source;
  992. status = "disabled";
  993. };
  994. dcmi: dcmi@4c006000 {
  995. compatible = "st,stm32-dcmi";
  996. reg = <0x4c006000 0x400>;
  997. interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
  998. resets = <&rcc CAMITF_R>;
  999. clocks = <&rcc DCMI>;
  1000. clock-names = "mclk";
  1001. dmas = <&dmamux1 75 0x400 0x0d>;
  1002. dma-names = "tx";
  1003. status = "disabled";
  1004. };
  1005. rcc: rcc@50000000 {
  1006. compatible = "st,stm32mp1-rcc", "syscon";
  1007. reg = <0x50000000 0x1000>;
  1008. #clock-cells = <1>;
  1009. #reset-cells = <1>;
  1010. };
  1011. pwr_regulators: pwr@50001000 {
  1012. compatible = "st,stm32mp1,pwr-reg";
  1013. reg = <0x50001000 0x10>;
  1014. reg11: reg11 {
  1015. regulator-name = "reg11";
  1016. regulator-min-microvolt = <1100000>;
  1017. regulator-max-microvolt = <1100000>;
  1018. };
  1019. reg18: reg18 {
  1020. regulator-name = "reg18";
  1021. regulator-min-microvolt = <1800000>;
  1022. regulator-max-microvolt = <1800000>;
  1023. };
  1024. usb33: usb33 {
  1025. regulator-name = "usb33";
  1026. regulator-min-microvolt = <3300000>;
  1027. regulator-max-microvolt = <3300000>;
  1028. };
  1029. };
  1030. pwr_mcu: pwr_mcu@50001014 {
  1031. compatible = "st,stm32mp151-pwr-mcu", "syscon";
  1032. reg = <0x50001014 0x4>;
  1033. };
  1034. exti: interrupt-controller@5000d000 {
  1035. compatible = "st,stm32mp1-exti", "syscon";
  1036. interrupt-controller;
  1037. #interrupt-cells = <2>;
  1038. reg = <0x5000d000 0x400>;
  1039. };
  1040. syscfg: syscon@50020000 {
  1041. compatible = "st,stm32mp157-syscfg", "syscon";
  1042. reg = <0x50020000 0x400>;
  1043. clocks = <&rcc SYSCFG>;
  1044. };
  1045. lptimer2: timer@50021000 {
  1046. #address-cells = <1>;
  1047. #size-cells = <0>;
  1048. compatible = "st,stm32-lptimer";
  1049. reg = <0x50021000 0x400>;
  1050. clocks = <&rcc LPTIM2_K>;
  1051. clock-names = "mux";
  1052. status = "disabled";
  1053. pwm {
  1054. compatible = "st,stm32-pwm-lp";
  1055. #pwm-cells = <3>;
  1056. status = "disabled";
  1057. };
  1058. trigger@1 {
  1059. compatible = "st,stm32-lptimer-trigger";
  1060. reg = <1>;
  1061. status = "disabled";
  1062. };
  1063. counter {
  1064. compatible = "st,stm32-lptimer-counter";
  1065. status = "disabled";
  1066. };
  1067. };
  1068. lptimer3: timer@50022000 {
  1069. #address-cells = <1>;
  1070. #size-cells = <0>;
  1071. compatible = "st,stm32-lptimer";
  1072. reg = <0x50022000 0x400>;
  1073. clocks = <&rcc LPTIM3_K>;
  1074. clock-names = "mux";
  1075. status = "disabled";
  1076. pwm {
  1077. compatible = "st,stm32-pwm-lp";
  1078. #pwm-cells = <3>;
  1079. status = "disabled";
  1080. };
  1081. trigger@2 {
  1082. compatible = "st,stm32-lptimer-trigger";
  1083. reg = <2>;
  1084. status = "disabled";
  1085. };
  1086. };
  1087. lptimer4: timer@50023000 {
  1088. compatible = "st,stm32-lptimer";
  1089. reg = <0x50023000 0x400>;
  1090. clocks = <&rcc LPTIM4_K>;
  1091. clock-names = "mux";
  1092. status = "disabled";
  1093. pwm {
  1094. compatible = "st,stm32-pwm-lp";
  1095. #pwm-cells = <3>;
  1096. status = "disabled";
  1097. };
  1098. };
  1099. lptimer5: timer@50024000 {
  1100. compatible = "st,stm32-lptimer";
  1101. reg = <0x50024000 0x400>;
  1102. clocks = <&rcc LPTIM5_K>;
  1103. clock-names = "mux";
  1104. status = "disabled";
  1105. pwm {
  1106. compatible = "st,stm32-pwm-lp";
  1107. #pwm-cells = <3>;
  1108. status = "disabled";
  1109. };
  1110. };
  1111. vrefbuf: vrefbuf@50025000 {
  1112. compatible = "st,stm32-vrefbuf";
  1113. reg = <0x50025000 0x8>;
  1114. regulator-min-microvolt = <1500000>;
  1115. regulator-max-microvolt = <2500000>;
  1116. clocks = <&rcc VREF>;
  1117. status = "disabled";
  1118. };
  1119. sai4: sai@50027000 {
  1120. compatible = "st,stm32h7-sai";
  1121. #address-cells = <1>;
  1122. #size-cells = <1>;
  1123. ranges = <0 0x50027000 0x400>;
  1124. reg = <0x50027000 0x4>, <0x500273f0 0x10>;
  1125. interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  1126. resets = <&rcc SAI4_R>;
  1127. status = "disabled";
  1128. sai4a: audio-controller@50027004 {
  1129. #sound-dai-cells = <0>;
  1130. compatible = "st,stm32-sai-sub-a";
  1131. reg = <0x04 0x1c>;
  1132. clocks = <&rcc SAI4_K>;
  1133. clock-names = "sai_ck";
  1134. dmas = <&dmamux1 99 0x400 0x01>;
  1135. status = "disabled";
  1136. };
  1137. sai4b: audio-controller@50027024 {
  1138. #sound-dai-cells = <0>;
  1139. compatible = "st,stm32-sai-sub-b";
  1140. reg = <0x24 0x1c>;
  1141. clocks = <&rcc SAI4_K>;
  1142. clock-names = "sai_ck";
  1143. dmas = <&dmamux1 100 0x400 0x01>;
  1144. status = "disabled";
  1145. };
  1146. };
  1147. dts: thermal@50028000 {
  1148. compatible = "st,stm32-thermal";
  1149. reg = <0x50028000 0x100>;
  1150. interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
  1151. clocks = <&rcc TMPSENS>;
  1152. clock-names = "pclk";
  1153. #thermal-sensor-cells = <0>;
  1154. status = "disabled";
  1155. };
  1156. hash1: hash@54002000 {
  1157. compatible = "st,stm32f756-hash";
  1158. reg = <0x54002000 0x400>;
  1159. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  1160. clocks = <&rcc HASH1>;
  1161. resets = <&rcc HASH1_R>;
  1162. dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
  1163. dma-names = "in";
  1164. dma-maxburst = <2>;
  1165. status = "disabled";
  1166. };
  1167. rng1: rng@54003000 {
  1168. compatible = "st,stm32-rng";
  1169. reg = <0x54003000 0x400>;
  1170. clocks = <&rcc RNG1_K>;
  1171. resets = <&rcc RNG1_R>;
  1172. status = "disabled";
  1173. };
  1174. mdma1: dma-controller@58000000 {
  1175. compatible = "st,stm32h7-mdma";
  1176. reg = <0x58000000 0x1000>;
  1177. interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  1178. clocks = <&rcc MDMA>;
  1179. resets = <&rcc MDMA_R>;
  1180. #dma-cells = <5>;
  1181. dma-channels = <32>;
  1182. dma-requests = <48>;
  1183. };
  1184. fmc: memory-controller@58002000 {
  1185. #address-cells = <2>;
  1186. #size-cells = <1>;
  1187. compatible = "st,stm32mp1-fmc2-ebi";
  1188. reg = <0x58002000 0x1000>;
  1189. clocks = <&rcc FMC_K>;
  1190. resets = <&rcc FMC_R>;
  1191. status = "disabled";
  1192. ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
  1193. <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
  1194. <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
  1195. <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
  1196. <4 0 0x80000000 0x10000000>; /* NAND */
  1197. nand-controller@4,0 {
  1198. #address-cells = <1>;
  1199. #size-cells = <0>;
  1200. compatible = "st,stm32mp1-fmc2-nfc";
  1201. reg = <4 0x00000000 0x1000>,
  1202. <4 0x08010000 0x1000>,
  1203. <4 0x08020000 0x1000>,
  1204. <4 0x01000000 0x1000>,
  1205. <4 0x09010000 0x1000>,
  1206. <4 0x09020000 0x1000>;
  1207. interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
  1208. dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
  1209. <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
  1210. <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
  1211. dma-names = "tx", "rx", "ecc";
  1212. status = "disabled";
  1213. };
  1214. };
  1215. qspi: spi@58003000 {
  1216. compatible = "st,stm32f469-qspi";
  1217. reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
  1218. reg-names = "qspi", "qspi_mm";
  1219. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  1220. dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
  1221. <&mdma1 22 0x10 0x100008 0x0 0x0>;
  1222. dma-names = "tx", "rx";
  1223. clocks = <&rcc QSPI_K>;
  1224. resets = <&rcc QSPI_R>;
  1225. #address-cells = <1>;
  1226. #size-cells = <0>;
  1227. status = "disabled";
  1228. };
  1229. sdmmc1: sdmmc@58005000 {
  1230. compatible = "arm,pl18x", "arm,primecell";
  1231. arm,primecell-periphid = <0x10153180>;
  1232. reg = <0x58005000 0x1000>;
  1233. interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  1234. interrupt-names = "cmd_irq";
  1235. clocks = <&rcc SDMMC1_K>;
  1236. clock-names = "apb_pclk";
  1237. resets = <&rcc SDMMC1_R>;
  1238. cap-sd-highspeed;
  1239. cap-mmc-highspeed;
  1240. max-frequency = <120000000>;
  1241. status = "disabled";
  1242. };
  1243. sdmmc2: sdmmc@58007000 {
  1244. compatible = "arm,pl18x", "arm,primecell";
  1245. arm,primecell-periphid = <0x10153180>;
  1246. reg = <0x58007000 0x1000>;
  1247. interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
  1248. interrupt-names = "cmd_irq";
  1249. clocks = <&rcc SDMMC2_K>;
  1250. clock-names = "apb_pclk";
  1251. resets = <&rcc SDMMC2_R>;
  1252. cap-sd-highspeed;
  1253. cap-mmc-highspeed;
  1254. max-frequency = <120000000>;
  1255. status = "disabled";
  1256. };
  1257. crc1: crc@58009000 {
  1258. compatible = "st,stm32f7-crc";
  1259. reg = <0x58009000 0x400>;
  1260. clocks = <&rcc CRC1>;
  1261. status = "disabled";
  1262. };
  1263. stmmac_axi_config_0: stmmac-axi-config {
  1264. snps,wr_osr_lmt = <0x7>;
  1265. snps,rd_osr_lmt = <0x7>;
  1266. snps,blen = <0 0 0 0 16 8 4>;
  1267. };
  1268. ethernet0: ethernet@5800a000 {
  1269. compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
  1270. reg = <0x5800a000 0x2000>;
  1271. reg-names = "stmmaceth";
  1272. interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  1273. interrupt-names = "macirq";
  1274. clock-names = "stmmaceth",
  1275. "mac-clk-tx",
  1276. "mac-clk-rx",
  1277. "eth-ck",
  1278. "ethstp";
  1279. clocks = <&rcc ETHMAC>,
  1280. <&rcc ETHTX>,
  1281. <&rcc ETHRX>,
  1282. <&rcc ETHCK_K>,
  1283. <&rcc ETHSTP>;
  1284. st,syscon = <&syscfg 0x4>;
  1285. snps,mixed-burst;
  1286. snps,pbl = <2>;
  1287. snps,en-tx-lpi-clockgating;
  1288. snps,axi-config = <&stmmac_axi_config_0>;
  1289. snps,tso;
  1290. status = "disabled";
  1291. };
  1292. usbh_ohci: usbh-ohci@5800c000 {
  1293. compatible = "generic-ohci";
  1294. reg = <0x5800c000 0x1000>;
  1295. clocks = <&rcc USBH>;
  1296. resets = <&rcc USBH_R>;
  1297. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  1298. status = "disabled";
  1299. };
  1300. usbh_ehci: usbh-ehci@5800d000 {
  1301. compatible = "generic-ehci";
  1302. reg = <0x5800d000 0x1000>;
  1303. clocks = <&rcc USBH>;
  1304. resets = <&rcc USBH_R>;
  1305. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  1306. companion = <&usbh_ohci>;
  1307. status = "disabled";
  1308. };
  1309. ltdc: display-controller@5a001000 {
  1310. compatible = "st,stm32-ltdc";
  1311. reg = <0x5a001000 0x400>;
  1312. interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
  1313. <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
  1314. clocks = <&rcc LTDC_PX>;
  1315. clock-names = "lcd";
  1316. resets = <&rcc LTDC_R>;
  1317. status = "disabled";
  1318. port {
  1319. #address-cells = <1>;
  1320. #size-cells = <0>;
  1321. };
  1322. };
  1323. iwdg2: watchdog@5a002000 {
  1324. compatible = "st,stm32mp1-iwdg";
  1325. reg = <0x5a002000 0x400>;
  1326. clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
  1327. clock-names = "pclk", "lsi";
  1328. status = "disabled";
  1329. };
  1330. usbphyc: usbphyc@5a006000 {
  1331. #address-cells = <1>;
  1332. #size-cells = <0>;
  1333. compatible = "st,stm32mp1-usbphyc";
  1334. reg = <0x5a006000 0x1000>;
  1335. clocks = <&rcc USBPHY_K>;
  1336. resets = <&rcc USBPHY_R>;
  1337. vdda1v1-supply = <&reg11>;
  1338. vdda1v8-supply = <&reg18>;
  1339. status = "disabled";
  1340. usbphyc_port0: usb-phy@0 {
  1341. #phy-cells = <0>;
  1342. reg = <0>;
  1343. };
  1344. usbphyc_port1: usb-phy@1 {
  1345. #phy-cells = <1>;
  1346. reg = <1>;
  1347. };
  1348. };
  1349. usart1: serial@5c000000 {
  1350. compatible = "st,stm32h7-uart";
  1351. reg = <0x5c000000 0x400>;
  1352. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  1353. clocks = <&rcc USART1_K>;
  1354. status = "disabled";
  1355. };
  1356. spi6: spi@5c001000 {
  1357. #address-cells = <1>;
  1358. #size-cells = <0>;
  1359. compatible = "st,stm32h7-spi";
  1360. reg = <0x5c001000 0x400>;
  1361. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  1362. clocks = <&rcc SPI6_K>;
  1363. resets = <&rcc SPI6_R>;
  1364. dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
  1365. <&mdma1 35 0x0 0x40002 0x0 0x0>;
  1366. dma-names = "rx", "tx";
  1367. status = "disabled";
  1368. };
  1369. i2c4: i2c@5c002000 {
  1370. compatible = "st,stm32mp15-i2c";
  1371. reg = <0x5c002000 0x400>;
  1372. interrupt-names = "event", "error";
  1373. interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
  1374. <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  1375. clocks = <&rcc I2C4_K>;
  1376. resets = <&rcc I2C4_R>;
  1377. #address-cells = <1>;
  1378. #size-cells = <0>;
  1379. st,syscfg-fmp = <&syscfg 0x4 0x8>;
  1380. wakeup-source;
  1381. status = "disabled";
  1382. };
  1383. rtc: rtc@5c004000 {
  1384. compatible = "st,stm32mp1-rtc";
  1385. reg = <0x5c004000 0x400>;
  1386. clocks = <&rcc RTCAPB>, <&rcc RTC>;
  1387. clock-names = "pclk", "rtc_ck";
  1388. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  1389. status = "disabled";
  1390. };
  1391. bsec: efuse@5c005000 {
  1392. compatible = "st,stm32mp15-bsec";
  1393. reg = <0x5c005000 0x400>;
  1394. #address-cells = <1>;
  1395. #size-cells = <1>;
  1396. part_number_otp: part_number_otp@4 {
  1397. reg = <0x4 0x1>;
  1398. };
  1399. ts_cal1: calib@5c {
  1400. reg = <0x5c 0x2>;
  1401. };
  1402. ts_cal2: calib@5e {
  1403. reg = <0x5e 0x2>;
  1404. };
  1405. };
  1406. i2c6: i2c@5c009000 {
  1407. compatible = "st,stm32mp15-i2c";
  1408. reg = <0x5c009000 0x400>;
  1409. interrupt-names = "event", "error";
  1410. interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
  1411. <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
  1412. clocks = <&rcc I2C6_K>;
  1413. resets = <&rcc I2C6_R>;
  1414. #address-cells = <1>;
  1415. #size-cells = <0>;
  1416. st,syscfg-fmp = <&syscfg 0x4 0x20>;
  1417. wakeup-source;
  1418. status = "disabled";
  1419. };
  1420. /*
  1421. * Break node order to solve dependency probe issue between
  1422. * pinctrl and exti.
  1423. */
  1424. pinctrl: pin-controller@50002000 {
  1425. #address-cells = <1>;
  1426. #size-cells = <1>;
  1427. compatible = "st,stm32mp157-pinctrl";
  1428. ranges = <0 0x50002000 0xa400>;
  1429. interrupt-parent = <&exti>;
  1430. st,syscfg = <&exti 0x60 0xff>;
  1431. hwlocks = <&hwspinlock 0>;
  1432. pins-are-numbered;
  1433. gpioa: gpio@50002000 {
  1434. gpio-controller;
  1435. #gpio-cells = <2>;
  1436. interrupt-controller;
  1437. #interrupt-cells = <2>;
  1438. reg = <0x0 0x400>;
  1439. clocks = <&rcc GPIOA>;
  1440. st,bank-name = "GPIOA";
  1441. status = "disabled";
  1442. };
  1443. gpiob: gpio@50003000 {
  1444. gpio-controller;
  1445. #gpio-cells = <2>;
  1446. interrupt-controller;
  1447. #interrupt-cells = <2>;
  1448. reg = <0x1000 0x400>;
  1449. clocks = <&rcc GPIOB>;
  1450. st,bank-name = "GPIOB";
  1451. status = "disabled";
  1452. };
  1453. gpioc: gpio@50004000 {
  1454. gpio-controller;
  1455. #gpio-cells = <2>;
  1456. interrupt-controller;
  1457. #interrupt-cells = <2>;
  1458. reg = <0x2000 0x400>;
  1459. clocks = <&rcc GPIOC>;
  1460. st,bank-name = "GPIOC";
  1461. status = "disabled";
  1462. };
  1463. gpiod: gpio@50005000 {
  1464. gpio-controller;
  1465. #gpio-cells = <2>;
  1466. interrupt-controller;
  1467. #interrupt-cells = <2>;
  1468. reg = <0x3000 0x400>;
  1469. clocks = <&rcc GPIOD>;
  1470. st,bank-name = "GPIOD";
  1471. status = "disabled";
  1472. };
  1473. gpioe: gpio@50006000 {
  1474. gpio-controller;
  1475. #gpio-cells = <2>;
  1476. interrupt-controller;
  1477. #interrupt-cells = <2>;
  1478. reg = <0x4000 0x400>;
  1479. clocks = <&rcc GPIOE>;
  1480. st,bank-name = "GPIOE";
  1481. status = "disabled";
  1482. };
  1483. gpiof: gpio@50007000 {
  1484. gpio-controller;
  1485. #gpio-cells = <2>;
  1486. interrupt-controller;
  1487. #interrupt-cells = <2>;
  1488. reg = <0x5000 0x400>;
  1489. clocks = <&rcc GPIOF>;
  1490. st,bank-name = "GPIOF";
  1491. status = "disabled";
  1492. };
  1493. gpiog: gpio@50008000 {
  1494. gpio-controller;
  1495. #gpio-cells = <2>;
  1496. interrupt-controller;
  1497. #interrupt-cells = <2>;
  1498. reg = <0x6000 0x400>;
  1499. clocks = <&rcc GPIOG>;
  1500. st,bank-name = "GPIOG";
  1501. status = "disabled";
  1502. };
  1503. gpioh: gpio@50009000 {
  1504. gpio-controller;
  1505. #gpio-cells = <2>;
  1506. interrupt-controller;
  1507. #interrupt-cells = <2>;
  1508. reg = <0x7000 0x400>;
  1509. clocks = <&rcc GPIOH>;
  1510. st,bank-name = "GPIOH";
  1511. status = "disabled";
  1512. };
  1513. gpioi: gpio@5000a000 {
  1514. gpio-controller;
  1515. #gpio-cells = <2>;
  1516. interrupt-controller;
  1517. #interrupt-cells = <2>;
  1518. reg = <0x8000 0x400>;
  1519. clocks = <&rcc GPIOI>;
  1520. st,bank-name = "GPIOI";
  1521. status = "disabled";
  1522. };
  1523. gpioj: gpio@5000b000 {
  1524. gpio-controller;
  1525. #gpio-cells = <2>;
  1526. interrupt-controller;
  1527. #interrupt-cells = <2>;
  1528. reg = <0x9000 0x400>;
  1529. clocks = <&rcc GPIOJ>;
  1530. st,bank-name = "GPIOJ";
  1531. status = "disabled";
  1532. };
  1533. gpiok: gpio@5000c000 {
  1534. gpio-controller;
  1535. #gpio-cells = <2>;
  1536. interrupt-controller;
  1537. #interrupt-cells = <2>;
  1538. reg = <0xa000 0x400>;
  1539. clocks = <&rcc GPIOK>;
  1540. st,bank-name = "GPIOK";
  1541. status = "disabled";
  1542. };
  1543. };
  1544. pinctrl_z: pin-controller-z@54004000 {
  1545. #address-cells = <1>;
  1546. #size-cells = <1>;
  1547. compatible = "st,stm32mp157-z-pinctrl";
  1548. ranges = <0 0x54004000 0x400>;
  1549. pins-are-numbered;
  1550. interrupt-parent = <&exti>;
  1551. st,syscfg = <&exti 0x60 0xff>;
  1552. hwlocks = <&hwspinlock 0>;
  1553. gpioz: gpio@54004000 {
  1554. gpio-controller;
  1555. #gpio-cells = <2>;
  1556. interrupt-controller;
  1557. #interrupt-cells = <2>;
  1558. reg = <0 0x400>;
  1559. clocks = <&rcc GPIOZ>;
  1560. st,bank-name = "GPIOZ";
  1561. st,bank-ioport = <11>;
  1562. status = "disabled";
  1563. };
  1564. };
  1565. };
  1566. mlahb: ahb {
  1567. compatible = "st,mlahb", "simple-bus";
  1568. #address-cells = <1>;
  1569. #size-cells = <1>;
  1570. ranges;
  1571. dma-ranges = <0x00000000 0x38000000 0x10000>,
  1572. <0x10000000 0x10000000 0x60000>,
  1573. <0x30000000 0x30000000 0x60000>;
  1574. m4_rproc: m4@10000000 {
  1575. compatible = "st,stm32mp1-m4";
  1576. reg = <0x10000000 0x40000>,
  1577. <0x30000000 0x40000>,
  1578. <0x38000000 0x10000>;
  1579. resets = <&rcc MCU_R>;
  1580. st,syscfg-holdboot = <&rcc 0x10C 0x1>;
  1581. st,syscfg-tz = <&rcc 0x000 0x1>;
  1582. st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
  1583. status = "disabled";
  1584. };
  1585. };
  1586. };