r8a774e1.dtsi 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the r8a774e1 SoC
  4. *
  5. * Copyright (C) 2020 Renesas Electronics Corp.
  6. */
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
  10. #include <dt-bindings/power/r8a774e1-sysc.h>
  11. #define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4
  12. / {
  13. compatible = "renesas,r8a774e1";
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. /*
  17. * The external audio clocks are configured as 0 Hz fixed frequency
  18. * clocks by default.
  19. * Boards that provide audio clocks should override them.
  20. */
  21. audio_clk_a: audio_clk_a {
  22. compatible = "fixed-clock";
  23. #clock-cells = <0>;
  24. clock-frequency = <0>;
  25. };
  26. audio_clk_c: audio_clk_c {
  27. compatible = "fixed-clock";
  28. #clock-cells = <0>;
  29. clock-frequency = <0>;
  30. };
  31. /* External CAN clock - to be overridden by boards that provide it */
  32. can_clk: can {
  33. compatible = "fixed-clock";
  34. #clock-cells = <0>;
  35. clock-frequency = <0>;
  36. };
  37. cluster0_opp: opp_table0 {
  38. compatible = "operating-points-v2";
  39. opp-shared;
  40. opp-500000000 {
  41. opp-hz = /bits/ 64 <500000000>;
  42. opp-microvolt = <820000>;
  43. clock-latency-ns = <300000>;
  44. };
  45. opp-1000000000 {
  46. opp-hz = /bits/ 64 <1000000000>;
  47. opp-microvolt = <820000>;
  48. clock-latency-ns = <300000>;
  49. };
  50. opp-1500000000 {
  51. opp-hz = /bits/ 64 <1500000000>;
  52. opp-microvolt = <820000>;
  53. clock-latency-ns = <300000>;
  54. opp-suspend;
  55. };
  56. };
  57. cluster1_opp: opp_table1 {
  58. compatible = "operating-points-v2";
  59. opp-shared;
  60. opp-800000000 {
  61. opp-hz = /bits/ 64 <800000000>;
  62. opp-microvolt = <820000>;
  63. clock-latency-ns = <300000>;
  64. };
  65. opp-1000000000 {
  66. opp-hz = /bits/ 64 <1000000000>;
  67. opp-microvolt = <820000>;
  68. clock-latency-ns = <300000>;
  69. };
  70. opp-1200000000 {
  71. opp-hz = /bits/ 64 <1200000000>;
  72. opp-microvolt = <820000>;
  73. clock-latency-ns = <300000>;
  74. };
  75. };
  76. cpus {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. cpu-map {
  80. cluster0 {
  81. core0 {
  82. cpu = <&a57_0>;
  83. };
  84. core1 {
  85. cpu = <&a57_1>;
  86. };
  87. core2 {
  88. cpu = <&a57_2>;
  89. };
  90. core3 {
  91. cpu = <&a57_3>;
  92. };
  93. };
  94. cluster1 {
  95. core0 {
  96. cpu = <&a53_0>;
  97. };
  98. core1 {
  99. cpu = <&a53_1>;
  100. };
  101. core2 {
  102. cpu = <&a53_2>;
  103. };
  104. core3 {
  105. cpu = <&a53_3>;
  106. };
  107. };
  108. };
  109. a57_0: cpu@0 {
  110. compatible = "arm,cortex-a57";
  111. reg = <0x0>;
  112. device_type = "cpu";
  113. power-domains = <&sysc R8A774E1_PD_CA57_CPU0>;
  114. next-level-cache = <&L2_CA57>;
  115. enable-method = "psci";
  116. dynamic-power-coefficient = <854>;
  117. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
  118. operating-points-v2 = <&cluster0_opp>;
  119. capacity-dmips-mhz = <1024>;
  120. #cooling-cells = <2>;
  121. };
  122. a57_1: cpu@1 {
  123. compatible = "arm,cortex-a57";
  124. reg = <0x1>;
  125. device_type = "cpu";
  126. power-domains = <&sysc R8A774E1_PD_CA57_CPU1>;
  127. next-level-cache = <&L2_CA57>;
  128. enable-method = "psci";
  129. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
  130. operating-points-v2 = <&cluster0_opp>;
  131. capacity-dmips-mhz = <1024>;
  132. #cooling-cells = <2>;
  133. };
  134. a57_2: cpu@2 {
  135. compatible = "arm,cortex-a57";
  136. reg = <0x2>;
  137. device_type = "cpu";
  138. power-domains = <&sysc R8A774E1_PD_CA57_CPU2>;
  139. next-level-cache = <&L2_CA57>;
  140. enable-method = "psci";
  141. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
  142. operating-points-v2 = <&cluster0_opp>;
  143. capacity-dmips-mhz = <1024>;
  144. #cooling-cells = <2>;
  145. };
  146. a57_3: cpu@3 {
  147. compatible = "arm,cortex-a57";
  148. reg = <0x3>;
  149. device_type = "cpu";
  150. power-domains = <&sysc R8A774E1_PD_CA57_CPU3>;
  151. next-level-cache = <&L2_CA57>;
  152. enable-method = "psci";
  153. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>;
  154. operating-points-v2 = <&cluster0_opp>;
  155. capacity-dmips-mhz = <1024>;
  156. #cooling-cells = <2>;
  157. };
  158. a53_0: cpu@100 {
  159. compatible = "arm,cortex-a53";
  160. reg = <0x100>;
  161. device_type = "cpu";
  162. power-domains = <&sysc R8A774E1_PD_CA53_CPU0>;
  163. next-level-cache = <&L2_CA53>;
  164. enable-method = "psci";
  165. #cooling-cells = <2>;
  166. dynamic-power-coefficient = <277>;
  167. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
  168. operating-points-v2 = <&cluster1_opp>;
  169. capacity-dmips-mhz = <535>;
  170. };
  171. a53_1: cpu@101 {
  172. compatible = "arm,cortex-a53";
  173. reg = <0x101>;
  174. device_type = "cpu";
  175. power-domains = <&sysc R8A774E1_PD_CA53_CPU1>;
  176. next-level-cache = <&L2_CA53>;
  177. enable-method = "psci";
  178. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
  179. operating-points-v2 = <&cluster1_opp>;
  180. capacity-dmips-mhz = <535>;
  181. };
  182. a53_2: cpu@102 {
  183. compatible = "arm,cortex-a53";
  184. reg = <0x102>;
  185. device_type = "cpu";
  186. power-domains = <&sysc R8A774E1_PD_CA53_CPU2>;
  187. next-level-cache = <&L2_CA53>;
  188. enable-method = "psci";
  189. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
  190. operating-points-v2 = <&cluster1_opp>;
  191. capacity-dmips-mhz = <535>;
  192. };
  193. a53_3: cpu@103 {
  194. compatible = "arm,cortex-a53";
  195. reg = <0x103>;
  196. device_type = "cpu";
  197. power-domains = <&sysc R8A774E1_PD_CA53_CPU3>;
  198. next-level-cache = <&L2_CA53>;
  199. enable-method = "psci";
  200. clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>;
  201. operating-points-v2 = <&cluster1_opp>;
  202. capacity-dmips-mhz = <535>;
  203. };
  204. L2_CA57: cache-controller-0 {
  205. compatible = "cache";
  206. power-domains = <&sysc R8A774E1_PD_CA57_SCU>;
  207. cache-unified;
  208. cache-level = <2>;
  209. };
  210. L2_CA53: cache-controller-1 {
  211. compatible = "cache";
  212. power-domains = <&sysc R8A774E1_PD_CA53_SCU>;
  213. cache-unified;
  214. cache-level = <2>;
  215. };
  216. };
  217. extal_clk: extal {
  218. compatible = "fixed-clock";
  219. #clock-cells = <0>;
  220. /* This value must be overridden by the board */
  221. clock-frequency = <0>;
  222. };
  223. extalr_clk: extalr {
  224. compatible = "fixed-clock";
  225. #clock-cells = <0>;
  226. /* This value must be overridden by the board */
  227. clock-frequency = <0>;
  228. };
  229. /* External PCIe clock - can be overridden by the board */
  230. pcie_bus_clk: pcie_bus {
  231. compatible = "fixed-clock";
  232. #clock-cells = <0>;
  233. clock-frequency = <0>;
  234. };
  235. pmu_a53 {
  236. compatible = "arm,cortex-a53-pmu";
  237. interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  238. <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  239. <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
  240. <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  241. interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
  242. };
  243. pmu_a57 {
  244. compatible = "arm,cortex-a57-pmu";
  245. interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  246. <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
  247. <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
  248. <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  249. interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>;
  250. };
  251. psci {
  252. compatible = "arm,psci-1.0", "arm,psci-0.2";
  253. method = "smc";
  254. };
  255. /* External SCIF clock - to be overridden by boards that provide it */
  256. scif_clk: scif {
  257. compatible = "fixed-clock";
  258. #clock-cells = <0>;
  259. clock-frequency = <0>;
  260. };
  261. soc {
  262. compatible = "simple-bus";
  263. interrupt-parent = <&gic>;
  264. #address-cells = <2>;
  265. #size-cells = <2>;
  266. ranges;
  267. rwdt: watchdog@e6020000 {
  268. compatible = "renesas,r8a774e1-wdt",
  269. "renesas,rcar-gen3-wdt";
  270. reg = <0 0xe6020000 0 0x0c>;
  271. interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  272. clocks = <&cpg CPG_MOD 402>;
  273. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  274. resets = <&cpg 402>;
  275. status = "disabled";
  276. };
  277. gpio0: gpio@e6050000 {
  278. compatible = "renesas,gpio-r8a774e1",
  279. "renesas,rcar-gen3-gpio";
  280. reg = <0 0xe6050000 0 0x50>;
  281. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  282. #gpio-cells = <2>;
  283. gpio-controller;
  284. gpio-ranges = <&pfc 0 0 16>;
  285. #interrupt-cells = <2>;
  286. interrupt-controller;
  287. clocks = <&cpg CPG_MOD 912>;
  288. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  289. resets = <&cpg 912>;
  290. };
  291. gpio1: gpio@e6051000 {
  292. compatible = "renesas,gpio-r8a774e1",
  293. "renesas,rcar-gen3-gpio";
  294. reg = <0 0xe6051000 0 0x50>;
  295. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  296. #gpio-cells = <2>;
  297. gpio-controller;
  298. gpio-ranges = <&pfc 0 32 29>;
  299. #interrupt-cells = <2>;
  300. interrupt-controller;
  301. clocks = <&cpg CPG_MOD 911>;
  302. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  303. resets = <&cpg 911>;
  304. };
  305. gpio2: gpio@e6052000 {
  306. compatible = "renesas,gpio-r8a774e1",
  307. "renesas,rcar-gen3-gpio";
  308. reg = <0 0xe6052000 0 0x50>;
  309. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  310. #gpio-cells = <2>;
  311. gpio-controller;
  312. gpio-ranges = <&pfc 0 64 15>;
  313. #interrupt-cells = <2>;
  314. interrupt-controller;
  315. clocks = <&cpg CPG_MOD 910>;
  316. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  317. resets = <&cpg 910>;
  318. };
  319. gpio3: gpio@e6053000 {
  320. compatible = "renesas,gpio-r8a774e1",
  321. "renesas,rcar-gen3-gpio";
  322. reg = <0 0xe6053000 0 0x50>;
  323. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  324. #gpio-cells = <2>;
  325. gpio-controller;
  326. gpio-ranges = <&pfc 0 96 16>;
  327. #interrupt-cells = <2>;
  328. interrupt-controller;
  329. clocks = <&cpg CPG_MOD 909>;
  330. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  331. resets = <&cpg 909>;
  332. };
  333. gpio4: gpio@e6054000 {
  334. compatible = "renesas,gpio-r8a774e1",
  335. "renesas,rcar-gen3-gpio";
  336. reg = <0 0xe6054000 0 0x50>;
  337. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  338. #gpio-cells = <2>;
  339. gpio-controller;
  340. gpio-ranges = <&pfc 0 128 18>;
  341. #interrupt-cells = <2>;
  342. interrupt-controller;
  343. clocks = <&cpg CPG_MOD 908>;
  344. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  345. resets = <&cpg 908>;
  346. };
  347. gpio5: gpio@e6055000 {
  348. compatible = "renesas,gpio-r8a774e1",
  349. "renesas,rcar-gen3-gpio";
  350. reg = <0 0xe6055000 0 0x50>;
  351. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  352. #gpio-cells = <2>;
  353. gpio-controller;
  354. gpio-ranges = <&pfc 0 160 26>;
  355. #interrupt-cells = <2>;
  356. interrupt-controller;
  357. clocks = <&cpg CPG_MOD 907>;
  358. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  359. resets = <&cpg 907>;
  360. };
  361. gpio6: gpio@e6055400 {
  362. compatible = "renesas,gpio-r8a774e1",
  363. "renesas,rcar-gen3-gpio";
  364. reg = <0 0xe6055400 0 0x50>;
  365. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  366. #gpio-cells = <2>;
  367. gpio-controller;
  368. gpio-ranges = <&pfc 0 192 32>;
  369. #interrupt-cells = <2>;
  370. interrupt-controller;
  371. clocks = <&cpg CPG_MOD 906>;
  372. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  373. resets = <&cpg 906>;
  374. };
  375. gpio7: gpio@e6055800 {
  376. compatible = "renesas,gpio-r8a774e1",
  377. "renesas,rcar-gen3-gpio";
  378. reg = <0 0xe6055800 0 0x50>;
  379. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  380. #gpio-cells = <2>;
  381. gpio-controller;
  382. gpio-ranges = <&pfc 0 224 4>;
  383. #interrupt-cells = <2>;
  384. interrupt-controller;
  385. clocks = <&cpg CPG_MOD 905>;
  386. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  387. resets = <&cpg 905>;
  388. };
  389. pfc: pin-controller@e6060000 {
  390. compatible = "renesas,pfc-r8a774e1";
  391. reg = <0 0xe6060000 0 0x50c>;
  392. };
  393. cmt0: timer@e60f0000 {
  394. compatible = "renesas,r8a774e1-cmt0",
  395. "renesas,rcar-gen3-cmt0";
  396. reg = <0 0xe60f0000 0 0x1004>;
  397. interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  398. <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  399. clocks = <&cpg CPG_MOD 303>;
  400. clock-names = "fck";
  401. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  402. resets = <&cpg 303>;
  403. status = "disabled";
  404. };
  405. cmt1: timer@e6130000 {
  406. compatible = "renesas,r8a774e1-cmt1",
  407. "renesas,rcar-gen3-cmt1";
  408. reg = <0 0xe6130000 0 0x1004>;
  409. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  410. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  411. <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  412. <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  413. <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  414. <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  415. <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  416. <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  417. clocks = <&cpg CPG_MOD 302>;
  418. clock-names = "fck";
  419. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  420. resets = <&cpg 302>;
  421. status = "disabled";
  422. };
  423. cmt2: timer@e6140000 {
  424. compatible = "renesas,r8a774e1-cmt1",
  425. "renesas,rcar-gen3-cmt1";
  426. reg = <0 0xe6140000 0 0x1004>;
  427. interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
  428. <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
  429. <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
  430. <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
  431. <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
  432. <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
  433. <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
  434. <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
  435. clocks = <&cpg CPG_MOD 301>;
  436. clock-names = "fck";
  437. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  438. resets = <&cpg 301>;
  439. status = "disabled";
  440. };
  441. cmt3: timer@e6148000 {
  442. compatible = "renesas,r8a774e1-cmt1",
  443. "renesas,rcar-gen3-cmt1";
  444. reg = <0 0xe6148000 0 0x1004>;
  445. interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
  446. <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
  447. <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
  448. <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
  449. <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
  450. <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
  451. <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
  452. <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
  453. clocks = <&cpg CPG_MOD 300>;
  454. clock-names = "fck";
  455. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  456. resets = <&cpg 300>;
  457. status = "disabled";
  458. };
  459. cpg: clock-controller@e6150000 {
  460. compatible = "renesas,r8a774e1-cpg-mssr";
  461. reg = <0 0xe6150000 0 0x1000>;
  462. clocks = <&extal_clk>, <&extalr_clk>;
  463. clock-names = "extal", "extalr";
  464. #clock-cells = <2>;
  465. #power-domain-cells = <0>;
  466. #reset-cells = <1>;
  467. };
  468. rst: reset-controller@e6160000 {
  469. compatible = "renesas,r8a774e1-rst";
  470. reg = <0 0xe6160000 0 0x0200>;
  471. };
  472. sysc: system-controller@e6180000 {
  473. compatible = "renesas,r8a774e1-sysc";
  474. reg = <0 0xe6180000 0 0x0400>;
  475. #power-domain-cells = <1>;
  476. };
  477. tsc: thermal@e6198000 {
  478. compatible = "renesas,r8a774e1-thermal";
  479. reg = <0 0xe6198000 0 0x100>,
  480. <0 0xe61a0000 0 0x100>,
  481. <0 0xe61a8000 0 0x100>;
  482. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
  483. <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  484. <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  485. clocks = <&cpg CPG_MOD 522>;
  486. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  487. resets = <&cpg 522>;
  488. #thermal-sensor-cells = <1>;
  489. };
  490. intc_ex: interrupt-controller@e61c0000 {
  491. compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc";
  492. #interrupt-cells = <2>;
  493. interrupt-controller;
  494. reg = <0 0xe61c0000 0 0x200>;
  495. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  496. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  497. <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  498. <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  499. <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  500. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
  501. clocks = <&cpg CPG_MOD 407>;
  502. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  503. resets = <&cpg 407>;
  504. };
  505. tmu0: timer@e61e0000 {
  506. compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
  507. reg = <0 0xe61e0000 0 0x30>;
  508. interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  509. <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  510. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  511. clocks = <&cpg CPG_MOD 125>;
  512. clock-names = "fck";
  513. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  514. resets = <&cpg 125>;
  515. status = "disabled";
  516. };
  517. tmu1: timer@e6fc0000 {
  518. compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
  519. reg = <0 0xe6fc0000 0 0x30>;
  520. interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  521. <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
  522. <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  523. clocks = <&cpg CPG_MOD 124>;
  524. clock-names = "fck";
  525. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  526. resets = <&cpg 124>;
  527. status = "disabled";
  528. };
  529. tmu2: timer@e6fd0000 {
  530. compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
  531. reg = <0 0xe6fd0000 0 0x30>;
  532. interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
  533. <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  534. <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
  535. clocks = <&cpg CPG_MOD 123>;
  536. clock-names = "fck";
  537. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  538. resets = <&cpg 123>;
  539. status = "disabled";
  540. };
  541. tmu3: timer@e6fe0000 {
  542. compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
  543. reg = <0 0xe6fe0000 0 0x30>;
  544. interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  545. <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
  546. <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  547. clocks = <&cpg CPG_MOD 122>;
  548. clock-names = "fck";
  549. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  550. resets = <&cpg 122>;
  551. status = "disabled";
  552. };
  553. tmu4: timer@ffc00000 {
  554. compatible = "renesas,tmu-r8a774e1", "renesas,tmu";
  555. reg = <0 0xffc00000 0 0x30>;
  556. interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
  557. <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
  558. <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
  559. clocks = <&cpg CPG_MOD 121>;
  560. clock-names = "fck";
  561. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  562. resets = <&cpg 121>;
  563. status = "disabled";
  564. };
  565. i2c0: i2c@e6500000 {
  566. #address-cells = <1>;
  567. #size-cells = <0>;
  568. compatible = "renesas,i2c-r8a774e1",
  569. "renesas,rcar-gen3-i2c";
  570. reg = <0 0xe6500000 0 0x40>;
  571. interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
  572. clocks = <&cpg CPG_MOD 931>;
  573. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  574. resets = <&cpg 931>;
  575. dmas = <&dmac1 0x91>, <&dmac1 0x90>,
  576. <&dmac2 0x91>, <&dmac2 0x90>;
  577. dma-names = "tx", "rx", "tx", "rx";
  578. i2c-scl-internal-delay-ns = <110>;
  579. status = "disabled";
  580. };
  581. i2c1: i2c@e6508000 {
  582. #address-cells = <1>;
  583. #size-cells = <0>;
  584. compatible = "renesas,i2c-r8a774e1",
  585. "renesas,rcar-gen3-i2c";
  586. reg = <0 0xe6508000 0 0x40>;
  587. interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
  588. clocks = <&cpg CPG_MOD 930>;
  589. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  590. resets = <&cpg 930>;
  591. dmas = <&dmac1 0x93>, <&dmac1 0x92>,
  592. <&dmac2 0x93>, <&dmac2 0x92>;
  593. dma-names = "tx", "rx", "tx", "rx";
  594. i2c-scl-internal-delay-ns = <6>;
  595. status = "disabled";
  596. };
  597. i2c2: i2c@e6510000 {
  598. #address-cells = <1>;
  599. #size-cells = <0>;
  600. compatible = "renesas,i2c-r8a774e1",
  601. "renesas,rcar-gen3-i2c";
  602. reg = <0 0xe6510000 0 0x40>;
  603. interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
  604. clocks = <&cpg CPG_MOD 929>;
  605. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  606. resets = <&cpg 929>;
  607. dmas = <&dmac1 0x95>, <&dmac1 0x94>,
  608. <&dmac2 0x95>, <&dmac2 0x94>;
  609. dma-names = "tx", "rx", "tx", "rx";
  610. i2c-scl-internal-delay-ns = <6>;
  611. status = "disabled";
  612. };
  613. i2c3: i2c@e66d0000 {
  614. #address-cells = <1>;
  615. #size-cells = <0>;
  616. compatible = "renesas,i2c-r8a774e1",
  617. "renesas,rcar-gen3-i2c";
  618. reg = <0 0xe66d0000 0 0x40>;
  619. interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
  620. clocks = <&cpg CPG_MOD 928>;
  621. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  622. resets = <&cpg 928>;
  623. dmas = <&dmac0 0x97>, <&dmac0 0x96>;
  624. dma-names = "tx", "rx";
  625. i2c-scl-internal-delay-ns = <110>;
  626. status = "disabled";
  627. };
  628. i2c4: i2c@e66d8000 {
  629. #address-cells = <1>;
  630. #size-cells = <0>;
  631. compatible = "renesas,i2c-r8a774e1",
  632. "renesas,rcar-gen3-i2c";
  633. reg = <0 0xe66d8000 0 0x40>;
  634. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  635. clocks = <&cpg CPG_MOD 927>;
  636. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  637. resets = <&cpg 927>;
  638. dmas = <&dmac0 0x99>, <&dmac0 0x98>;
  639. dma-names = "tx", "rx";
  640. i2c-scl-internal-delay-ns = <110>;
  641. status = "disabled";
  642. };
  643. i2c5: i2c@e66e0000 {
  644. #address-cells = <1>;
  645. #size-cells = <0>;
  646. compatible = "renesas,i2c-r8a774e1",
  647. "renesas,rcar-gen3-i2c";
  648. reg = <0 0xe66e0000 0 0x40>;
  649. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  650. clocks = <&cpg CPG_MOD 919>;
  651. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  652. resets = <&cpg 919>;
  653. dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
  654. dma-names = "tx", "rx";
  655. i2c-scl-internal-delay-ns = <110>;
  656. status = "disabled";
  657. };
  658. i2c6: i2c@e66e8000 {
  659. #address-cells = <1>;
  660. #size-cells = <0>;
  661. compatible = "renesas,i2c-r8a774e1",
  662. "renesas,rcar-gen3-i2c";
  663. reg = <0 0xe66e8000 0 0x40>;
  664. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  665. clocks = <&cpg CPG_MOD 918>;
  666. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  667. resets = <&cpg 918>;
  668. dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
  669. dma-names = "tx", "rx";
  670. i2c-scl-internal-delay-ns = <6>;
  671. status = "disabled";
  672. };
  673. i2c_dvfs: i2c@e60b0000 {
  674. #address-cells = <1>;
  675. #size-cells = <0>;
  676. compatible = "renesas,iic-r8a774e1",
  677. "renesas,rcar-gen3-iic",
  678. "renesas,rmobile-iic";
  679. reg = <0 0xe60b0000 0 0x425>;
  680. interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
  681. clocks = <&cpg CPG_MOD 926>;
  682. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  683. resets = <&cpg 926>;
  684. dmas = <&dmac0 0x11>, <&dmac0 0x10>;
  685. dma-names = "tx", "rx";
  686. status = "disabled";
  687. };
  688. hscif0: serial@e6540000 {
  689. compatible = "renesas,hscif-r8a774e1",
  690. "renesas,rcar-gen3-hscif",
  691. "renesas,hscif";
  692. reg = <0 0xe6540000 0 0x60>;
  693. interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  694. clocks = <&cpg CPG_MOD 520>,
  695. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  696. <&scif_clk>;
  697. clock-names = "fck", "brg_int", "scif_clk";
  698. dmas = <&dmac1 0x31>, <&dmac1 0x30>,
  699. <&dmac2 0x31>, <&dmac2 0x30>;
  700. dma-names = "tx", "rx", "tx", "rx";
  701. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  702. resets = <&cpg 520>;
  703. status = "disabled";
  704. };
  705. hscif1: serial@e6550000 {
  706. compatible = "renesas,hscif-r8a774e1",
  707. "renesas,rcar-gen3-hscif",
  708. "renesas,hscif";
  709. reg = <0 0xe6550000 0 0x60>;
  710. interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  711. clocks = <&cpg CPG_MOD 519>,
  712. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  713. <&scif_clk>;
  714. clock-names = "fck", "brg_int", "scif_clk";
  715. dmas = <&dmac1 0x33>, <&dmac1 0x32>,
  716. <&dmac2 0x33>, <&dmac2 0x32>;
  717. dma-names = "tx", "rx", "tx", "rx";
  718. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  719. resets = <&cpg 519>;
  720. status = "disabled";
  721. };
  722. hscif2: serial@e6560000 {
  723. compatible = "renesas,hscif-r8a774e1",
  724. "renesas,rcar-gen3-hscif",
  725. "renesas,hscif";
  726. reg = <0 0xe6560000 0 0x60>;
  727. interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
  728. clocks = <&cpg CPG_MOD 518>,
  729. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  730. <&scif_clk>;
  731. clock-names = "fck", "brg_int", "scif_clk";
  732. dmas = <&dmac1 0x35>, <&dmac1 0x34>,
  733. <&dmac2 0x35>, <&dmac2 0x34>;
  734. dma-names = "tx", "rx", "tx", "rx";
  735. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  736. resets = <&cpg 518>;
  737. status = "disabled";
  738. };
  739. hscif3: serial@e66a0000 {
  740. compatible = "renesas,hscif-r8a774e1",
  741. "renesas,rcar-gen3-hscif",
  742. "renesas,hscif";
  743. reg = <0 0xe66a0000 0 0x60>;
  744. interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
  745. clocks = <&cpg CPG_MOD 517>,
  746. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  747. <&scif_clk>;
  748. clock-names = "fck", "brg_int", "scif_clk";
  749. dmas = <&dmac0 0x37>, <&dmac0 0x36>;
  750. dma-names = "tx", "rx";
  751. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  752. resets = <&cpg 517>;
  753. status = "disabled";
  754. };
  755. hscif4: serial@e66b0000 {
  756. compatible = "renesas,hscif-r8a774e1",
  757. "renesas,rcar-gen3-hscif",
  758. "renesas,hscif";
  759. reg = <0 0xe66b0000 0 0x60>;
  760. interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  761. clocks = <&cpg CPG_MOD 516>,
  762. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  763. <&scif_clk>;
  764. clock-names = "fck", "brg_int", "scif_clk";
  765. dmas = <&dmac0 0x39>, <&dmac0 0x38>;
  766. dma-names = "tx", "rx";
  767. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  768. resets = <&cpg 516>;
  769. status = "disabled";
  770. };
  771. hsusb: usb@e6590000 {
  772. reg = <0 0xe6590000 0 0x200>;
  773. status = "disabled";
  774. /* placeholder */
  775. };
  776. usb3_phy0: usb-phy@e65ee000 {
  777. reg = <0 0xe65ee000 0 0x90>;
  778. #phy-cells = <0>;
  779. status = "disabled";
  780. /* placeholder */
  781. };
  782. dmac0: dma-controller@e6700000 {
  783. compatible = "renesas,dmac-r8a774e1",
  784. "renesas,rcar-dmac";
  785. reg = <0 0xe6700000 0 0x10000>;
  786. interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
  787. <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
  788. <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
  789. <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
  790. <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
  791. <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
  792. <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
  793. <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
  794. <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
  795. <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
  796. <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
  797. <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
  798. <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
  799. <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
  800. <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
  801. <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
  802. <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
  803. interrupt-names = "error",
  804. "ch0", "ch1", "ch2", "ch3",
  805. "ch4", "ch5", "ch6", "ch7",
  806. "ch8", "ch9", "ch10", "ch11",
  807. "ch12", "ch13", "ch14", "ch15";
  808. clocks = <&cpg CPG_MOD 219>;
  809. clock-names = "fck";
  810. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  811. resets = <&cpg 219>;
  812. #dma-cells = <1>;
  813. dma-channels = <16>;
  814. iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
  815. <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
  816. <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
  817. <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
  818. <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
  819. <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
  820. <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
  821. <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
  822. };
  823. dmac1: dma-controller@e7300000 {
  824. compatible = "renesas,dmac-r8a774e1",
  825. "renesas,rcar-dmac";
  826. reg = <0 0xe7300000 0 0x10000>;
  827. interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
  828. <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
  829. <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
  830. <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
  831. <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
  832. <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
  833. <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  834. <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  835. <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  836. <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  837. <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
  838. <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
  839. <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
  840. <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
  841. <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
  842. <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
  843. <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
  844. interrupt-names = "error",
  845. "ch0", "ch1", "ch2", "ch3",
  846. "ch4", "ch5", "ch6", "ch7",
  847. "ch8", "ch9", "ch10", "ch11",
  848. "ch12", "ch13", "ch14", "ch15";
  849. clocks = <&cpg CPG_MOD 218>;
  850. clock-names = "fck";
  851. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  852. resets = <&cpg 218>;
  853. #dma-cells = <1>;
  854. dma-channels = <16>;
  855. iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
  856. <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
  857. <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
  858. <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
  859. <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
  860. <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
  861. <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
  862. <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
  863. };
  864. dmac2: dma-controller@e7310000 {
  865. compatible = "renesas,dmac-r8a774e1",
  866. "renesas,rcar-dmac";
  867. reg = <0 0xe7310000 0 0x10000>;
  868. interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
  869. <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
  870. <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
  871. <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
  872. <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
  873. <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
  874. <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
  875. <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
  876. <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
  877. <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
  878. <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
  879. <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
  880. <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
  881. <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
  882. <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
  883. <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
  884. <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
  885. interrupt-names = "error",
  886. "ch0", "ch1", "ch2", "ch3",
  887. "ch4", "ch5", "ch6", "ch7",
  888. "ch8", "ch9", "ch10", "ch11",
  889. "ch12", "ch13", "ch14", "ch15";
  890. clocks = <&cpg CPG_MOD 217>;
  891. clock-names = "fck";
  892. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  893. resets = <&cpg 217>;
  894. #dma-cells = <1>;
  895. dma-channels = <16>;
  896. iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
  897. <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
  898. <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
  899. <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
  900. <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
  901. <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
  902. <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
  903. <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
  904. };
  905. ipmmu_ds0: iommu@e6740000 {
  906. compatible = "renesas,ipmmu-r8a774e1";
  907. reg = <0 0xe6740000 0 0x1000>;
  908. renesas,ipmmu-main = <&ipmmu_mm 0>;
  909. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  910. #iommu-cells = <1>;
  911. };
  912. ipmmu_ds1: iommu@e7740000 {
  913. compatible = "renesas,ipmmu-r8a774e1";
  914. reg = <0 0xe7740000 0 0x1000>;
  915. renesas,ipmmu-main = <&ipmmu_mm 1>;
  916. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  917. #iommu-cells = <1>;
  918. };
  919. ipmmu_hc: iommu@e6570000 {
  920. compatible = "renesas,ipmmu-r8a774e1";
  921. reg = <0 0xe6570000 0 0x1000>;
  922. renesas,ipmmu-main = <&ipmmu_mm 2>;
  923. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  924. #iommu-cells = <1>;
  925. };
  926. ipmmu_mm: iommu@e67b0000 {
  927. compatible = "renesas,ipmmu-r8a774e1";
  928. reg = <0 0xe67b0000 0 0x1000>;
  929. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
  930. <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
  931. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  932. #iommu-cells = <1>;
  933. };
  934. ipmmu_mp0: iommu@ec670000 {
  935. compatible = "renesas,ipmmu-r8a774e1";
  936. reg = <0 0xec670000 0 0x1000>;
  937. renesas,ipmmu-main = <&ipmmu_mm 4>;
  938. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  939. #iommu-cells = <1>;
  940. };
  941. ipmmu_pv0: iommu@fd800000 {
  942. compatible = "renesas,ipmmu-r8a774e1";
  943. reg = <0 0xfd800000 0 0x1000>;
  944. renesas,ipmmu-main = <&ipmmu_mm 6>;
  945. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  946. #iommu-cells = <1>;
  947. };
  948. ipmmu_pv1: iommu@fd950000 {
  949. compatible = "renesas,ipmmu-r8a774e1";
  950. reg = <0 0xfd950000 0 0x1000>;
  951. renesas,ipmmu-main = <&ipmmu_mm 7>;
  952. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  953. #iommu-cells = <1>;
  954. };
  955. ipmmu_pv2: iommu@fd960000 {
  956. compatible = "renesas,ipmmu-r8a774e1";
  957. reg = <0 0xfd960000 0 0x1000>;
  958. renesas,ipmmu-main = <&ipmmu_mm 8>;
  959. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  960. #iommu-cells = <1>;
  961. };
  962. ipmmu_pv3: iommu@fd970000 {
  963. compatible = "renesas,ipmmu-r8a774e1";
  964. reg = <0 0xfd970000 0 0x1000>;
  965. renesas,ipmmu-main = <&ipmmu_mm 9>;
  966. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  967. #iommu-cells = <1>;
  968. };
  969. ipmmu_vc0: iommu@fe6b0000 {
  970. compatible = "renesas,ipmmu-r8a774e1";
  971. reg = <0 0xfe6b0000 0 0x1000>;
  972. renesas,ipmmu-main = <&ipmmu_mm 12>;
  973. power-domains = <&sysc R8A774E1_PD_A3VC>;
  974. #iommu-cells = <1>;
  975. };
  976. ipmmu_vc1: iommu@fe6f0000 {
  977. compatible = "renesas,ipmmu-r8a774e1";
  978. reg = <0 0xfe6f0000 0 0x1000>;
  979. renesas,ipmmu-main = <&ipmmu_mm 13>;
  980. power-domains = <&sysc R8A774E1_PD_A3VC>;
  981. #iommu-cells = <1>;
  982. };
  983. ipmmu_vi0: iommu@febd0000 {
  984. compatible = "renesas,ipmmu-r8a774e1";
  985. reg = <0 0xfebd0000 0 0x1000>;
  986. renesas,ipmmu-main = <&ipmmu_mm 14>;
  987. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  988. #iommu-cells = <1>;
  989. };
  990. ipmmu_vi1: iommu@febe0000 {
  991. compatible = "renesas,ipmmu-r8a774e1";
  992. reg = <0 0xfebe0000 0 0x1000>;
  993. renesas,ipmmu-main = <&ipmmu_mm 15>;
  994. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  995. #iommu-cells = <1>;
  996. };
  997. ipmmu_vp0: iommu@fe990000 {
  998. compatible = "renesas,ipmmu-r8a774e1";
  999. reg = <0 0xfe990000 0 0x1000>;
  1000. renesas,ipmmu-main = <&ipmmu_mm 16>;
  1001. power-domains = <&sysc R8A774E1_PD_A3VP>;
  1002. #iommu-cells = <1>;
  1003. };
  1004. ipmmu_vp1: iommu@fe980000 {
  1005. compatible = "renesas,ipmmu-r8a774e1";
  1006. reg = <0 0xfe980000 0 0x1000>;
  1007. renesas,ipmmu-main = <&ipmmu_mm 17>;
  1008. power-domains = <&sysc R8A774E1_PD_A3VP>;
  1009. #iommu-cells = <1>;
  1010. };
  1011. avb: ethernet@e6800000 {
  1012. compatible = "renesas,etheravb-r8a774e1",
  1013. "renesas,etheravb-rcar-gen3";
  1014. reg = <0 0xe6800000 0 0x800>;
  1015. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
  1016. <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  1017. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  1018. <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  1019. <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
  1020. <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
  1021. <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
  1022. <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
  1023. <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  1024. <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
  1025. <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
  1026. <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
  1027. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  1028. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  1029. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  1030. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  1031. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  1032. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  1033. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  1034. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  1035. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  1036. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  1037. <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  1038. <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  1039. <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  1040. interrupt-names = "ch0", "ch1", "ch2", "ch3",
  1041. "ch4", "ch5", "ch6", "ch7",
  1042. "ch8", "ch9", "ch10", "ch11",
  1043. "ch12", "ch13", "ch14", "ch15",
  1044. "ch16", "ch17", "ch18", "ch19",
  1045. "ch20", "ch21", "ch22", "ch23",
  1046. "ch24";
  1047. clocks = <&cpg CPG_MOD 812>;
  1048. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1049. resets = <&cpg 812>;
  1050. phy-mode = "rgmii";
  1051. iommus = <&ipmmu_ds0 16>;
  1052. #address-cells = <1>;
  1053. #size-cells = <0>;
  1054. status = "disabled";
  1055. };
  1056. can0: can@e6c30000 {
  1057. compatible = "renesas,can-r8a774e1",
  1058. "renesas,rcar-gen3-can";
  1059. reg = <0 0xe6c30000 0 0x1000>;
  1060. interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
  1061. clocks = <&cpg CPG_MOD 916>,
  1062. <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
  1063. <&can_clk>;
  1064. clock-names = "clkp1", "clkp2", "can_clk";
  1065. assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
  1066. assigned-clock-rates = <40000000>;
  1067. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1068. resets = <&cpg 916>;
  1069. status = "disabled";
  1070. };
  1071. can1: can@e6c38000 {
  1072. compatible = "renesas,can-r8a774e1",
  1073. "renesas,rcar-gen3-can";
  1074. reg = <0 0xe6c38000 0 0x1000>;
  1075. interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
  1076. clocks = <&cpg CPG_MOD 915>,
  1077. <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
  1078. <&can_clk>;
  1079. clock-names = "clkp1", "clkp2", "can_clk";
  1080. assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
  1081. assigned-clock-rates = <40000000>;
  1082. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1083. resets = <&cpg 915>;
  1084. status = "disabled";
  1085. };
  1086. canfd: can@e66c0000 {
  1087. compatible = "renesas,r8a774e1-canfd",
  1088. "renesas,rcar-gen3-canfd";
  1089. reg = <0 0xe66c0000 0 0x8000>;
  1090. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  1091. <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  1092. clocks = <&cpg CPG_MOD 914>,
  1093. <&cpg CPG_CORE R8A774E1_CLK_CANFD>,
  1094. <&can_clk>;
  1095. clock-names = "fck", "canfd", "can_clk";
  1096. assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
  1097. assigned-clock-rates = <40000000>;
  1098. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1099. resets = <&cpg 914>;
  1100. status = "disabled";
  1101. channel0 {
  1102. status = "disabled";
  1103. };
  1104. channel1 {
  1105. status = "disabled";
  1106. };
  1107. };
  1108. pwm0: pwm@e6e30000 {
  1109. reg = <0 0xe6e30000 0 0x8>;
  1110. #pwm-cells = <2>;
  1111. status = "disabled";
  1112. /* placeholder */
  1113. };
  1114. scif0: serial@e6e60000 {
  1115. compatible = "renesas,scif-r8a774e1",
  1116. "renesas,rcar-gen3-scif", "renesas,scif";
  1117. reg = <0 0xe6e60000 0 0x40>;
  1118. interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
  1119. clocks = <&cpg CPG_MOD 207>,
  1120. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  1121. <&scif_clk>;
  1122. clock-names = "fck", "brg_int", "scif_clk";
  1123. dmas = <&dmac1 0x51>, <&dmac1 0x50>,
  1124. <&dmac2 0x51>, <&dmac2 0x50>;
  1125. dma-names = "tx", "rx", "tx", "rx";
  1126. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1127. resets = <&cpg 207>;
  1128. status = "disabled";
  1129. };
  1130. scif1: serial@e6e68000 {
  1131. compatible = "renesas,scif-r8a774e1",
  1132. "renesas,rcar-gen3-scif", "renesas,scif";
  1133. reg = <0 0xe6e68000 0 0x40>;
  1134. interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  1135. clocks = <&cpg CPG_MOD 206>,
  1136. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  1137. <&scif_clk>;
  1138. clock-names = "fck", "brg_int", "scif_clk";
  1139. dmas = <&dmac1 0x53>, <&dmac1 0x52>,
  1140. <&dmac2 0x53>, <&dmac2 0x52>;
  1141. dma-names = "tx", "rx", "tx", "rx";
  1142. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1143. resets = <&cpg 206>;
  1144. status = "disabled";
  1145. };
  1146. scif2: serial@e6e88000 {
  1147. compatible = "renesas,scif-r8a774e1",
  1148. "renesas,rcar-gen3-scif", "renesas,scif";
  1149. reg = <0 0xe6e88000 0 0x40>;
  1150. interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  1151. clocks = <&cpg CPG_MOD 310>,
  1152. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  1153. <&scif_clk>;
  1154. clock-names = "fck", "brg_int", "scif_clk";
  1155. dmas = <&dmac1 0x13>, <&dmac1 0x12>,
  1156. <&dmac2 0x13>, <&dmac2 0x12>;
  1157. dma-names = "tx", "rx", "tx", "rx";
  1158. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1159. resets = <&cpg 310>;
  1160. status = "disabled";
  1161. };
  1162. scif3: serial@e6c50000 {
  1163. compatible = "renesas,scif-r8a774e1",
  1164. "renesas,rcar-gen3-scif", "renesas,scif";
  1165. reg = <0 0xe6c50000 0 0x40>;
  1166. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  1167. clocks = <&cpg CPG_MOD 204>,
  1168. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  1169. <&scif_clk>;
  1170. clock-names = "fck", "brg_int", "scif_clk";
  1171. dmas = <&dmac0 0x57>, <&dmac0 0x56>;
  1172. dma-names = "tx", "rx";
  1173. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1174. resets = <&cpg 204>;
  1175. status = "disabled";
  1176. };
  1177. scif4: serial@e6c40000 {
  1178. compatible = "renesas,scif-r8a774e1",
  1179. "renesas,rcar-gen3-scif", "renesas,scif";
  1180. reg = <0 0xe6c40000 0 0x40>;
  1181. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  1182. clocks = <&cpg CPG_MOD 203>,
  1183. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  1184. <&scif_clk>;
  1185. clock-names = "fck", "brg_int", "scif_clk";
  1186. dmas = <&dmac0 0x59>, <&dmac0 0x58>;
  1187. dma-names = "tx", "rx";
  1188. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1189. resets = <&cpg 203>;
  1190. status = "disabled";
  1191. };
  1192. scif5: serial@e6f30000 {
  1193. compatible = "renesas,scif-r8a774e1",
  1194. "renesas,rcar-gen3-scif", "renesas,scif";
  1195. reg = <0 0xe6f30000 0 0x40>;
  1196. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  1197. clocks = <&cpg CPG_MOD 202>,
  1198. <&cpg CPG_CORE R8A774E1_CLK_S3D1>,
  1199. <&scif_clk>;
  1200. clock-names = "fck", "brg_int", "scif_clk";
  1201. dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
  1202. <&dmac2 0x5b>, <&dmac2 0x5a>;
  1203. dma-names = "tx", "rx", "tx", "rx";
  1204. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1205. resets = <&cpg 202>;
  1206. status = "disabled";
  1207. };
  1208. msiof0: spi@e6e90000 {
  1209. compatible = "renesas,msiof-r8a774e1",
  1210. "renesas,rcar-gen3-msiof";
  1211. reg = <0 0xe6e90000 0 0x0064>;
  1212. interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
  1213. clocks = <&cpg CPG_MOD 211>;
  1214. dmas = <&dmac1 0x41>, <&dmac1 0x40>,
  1215. <&dmac2 0x41>, <&dmac2 0x40>;
  1216. dma-names = "tx", "rx", "tx", "rx";
  1217. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1218. resets = <&cpg 211>;
  1219. #address-cells = <1>;
  1220. #size-cells = <0>;
  1221. status = "disabled";
  1222. };
  1223. msiof1: spi@e6ea0000 {
  1224. compatible = "renesas,msiof-r8a774e1",
  1225. "renesas,rcar-gen3-msiof";
  1226. reg = <0 0xe6ea0000 0 0x0064>;
  1227. interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  1228. clocks = <&cpg CPG_MOD 210>;
  1229. dmas = <&dmac1 0x43>, <&dmac1 0x42>,
  1230. <&dmac2 0x43>, <&dmac2 0x42>;
  1231. dma-names = "tx", "rx", "tx", "rx";
  1232. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1233. resets = <&cpg 210>;
  1234. #address-cells = <1>;
  1235. #size-cells = <0>;
  1236. status = "disabled";
  1237. };
  1238. msiof2: spi@e6c00000 {
  1239. compatible = "renesas,msiof-r8a774e1",
  1240. "renesas,rcar-gen3-msiof";
  1241. reg = <0 0xe6c00000 0 0x0064>;
  1242. interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
  1243. clocks = <&cpg CPG_MOD 209>;
  1244. dmas = <&dmac0 0x45>, <&dmac0 0x44>;
  1245. dma-names = "tx", "rx";
  1246. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1247. resets = <&cpg 209>;
  1248. #address-cells = <1>;
  1249. #size-cells = <0>;
  1250. status = "disabled";
  1251. };
  1252. msiof3: spi@e6c10000 {
  1253. compatible = "renesas,msiof-r8a774e1",
  1254. "renesas,rcar-gen3-msiof";
  1255. reg = <0 0xe6c10000 0 0x0064>;
  1256. interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  1257. clocks = <&cpg CPG_MOD 208>;
  1258. dmas = <&dmac0 0x47>, <&dmac0 0x46>;
  1259. dma-names = "tx", "rx";
  1260. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1261. resets = <&cpg 208>;
  1262. #address-cells = <1>;
  1263. #size-cells = <0>;
  1264. status = "disabled";
  1265. };
  1266. rcar_sound: sound@ec500000 {
  1267. reg = <0 0xec500000 0 0x1000>, /* SCU */
  1268. <0 0xec5a0000 0 0x100>, /* ADG */
  1269. <0 0xec540000 0 0x1000>, /* SSIU */
  1270. <0 0xec541000 0 0x280>, /* SSI */
  1271. <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
  1272. reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
  1273. status = "disabled";
  1274. /* placeholder */
  1275. rcar_sound,ssi {
  1276. ssi2: ssi-2 {
  1277. /* placeholder */
  1278. };
  1279. };
  1280. };
  1281. xhci0: usb@ee000000 {
  1282. reg = <0 0xee000000 0 0xc00>;
  1283. status = "disabled";
  1284. /* placeholder */
  1285. };
  1286. usb3_peri0: usb@ee020000 {
  1287. reg = <0 0xee020000 0 0x400>;
  1288. status = "disabled";
  1289. /* placeholder */
  1290. };
  1291. ohci0: usb@ee080000 {
  1292. reg = <0 0xee080000 0 0x100>;
  1293. status = "disabled";
  1294. /* placeholder */
  1295. };
  1296. ohci1: usb@ee0a0000 {
  1297. reg = <0 0xee0a0000 0 0x100>;
  1298. status = "disabled";
  1299. /* placeholder */
  1300. };
  1301. ehci0: usb@ee080100 {
  1302. reg = <0 0xee080100 0 0x100>;
  1303. status = "disabled";
  1304. /* placeholder */
  1305. };
  1306. ehci1: usb@ee0a0100 {
  1307. reg = <0 0xee0a0100 0 0x100>;
  1308. status = "disabled";
  1309. /* placeholder */
  1310. };
  1311. usb2_phy0: usb-phy@ee080200 {
  1312. reg = <0 0xee080200 0 0x700>;
  1313. status = "disabled";
  1314. /* placeholder */
  1315. };
  1316. usb2_phy1: usb-phy@ee0a0200 {
  1317. reg = <0 0xee0a0200 0 0x700>;
  1318. status = "disabled";
  1319. /* placeholder */
  1320. };
  1321. sdhi0: mmc@ee100000 {
  1322. compatible = "renesas,sdhi-r8a774e1",
  1323. "renesas,rcar-gen3-sdhi";
  1324. reg = <0 0xee100000 0 0x2000>;
  1325. interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
  1326. clocks = <&cpg CPG_MOD 314>;
  1327. max-frequency = <200000000>;
  1328. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1329. resets = <&cpg 314>;
  1330. iommus = <&ipmmu_ds1 32>;
  1331. status = "disabled";
  1332. };
  1333. sdhi1: mmc@ee120000 {
  1334. compatible = "renesas,sdhi-r8a774e1",
  1335. "renesas,rcar-gen3-sdhi";
  1336. reg = <0 0xee120000 0 0x2000>;
  1337. interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
  1338. clocks = <&cpg CPG_MOD 313>;
  1339. max-frequency = <200000000>;
  1340. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1341. resets = <&cpg 313>;
  1342. iommus = <&ipmmu_ds1 33>;
  1343. status = "disabled";
  1344. };
  1345. sdhi2: mmc@ee140000 {
  1346. compatible = "renesas,sdhi-r8a774e1",
  1347. "renesas,rcar-gen3-sdhi";
  1348. reg = <0 0xee140000 0 0x2000>;
  1349. interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
  1350. clocks = <&cpg CPG_MOD 312>;
  1351. max-frequency = <200000000>;
  1352. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1353. resets = <&cpg 312>;
  1354. iommus = <&ipmmu_ds1 34>;
  1355. status = "disabled";
  1356. };
  1357. sdhi3: mmc@ee160000 {
  1358. compatible = "renesas,sdhi-r8a774e1",
  1359. "renesas,rcar-gen3-sdhi";
  1360. reg = <0 0xee160000 0 0x2000>;
  1361. interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
  1362. clocks = <&cpg CPG_MOD 311>;
  1363. max-frequency = <200000000>;
  1364. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1365. resets = <&cpg 311>;
  1366. iommus = <&ipmmu_ds1 35>;
  1367. status = "disabled";
  1368. };
  1369. gic: interrupt-controller@f1010000 {
  1370. compatible = "arm,gic-400";
  1371. #interrupt-cells = <3>;
  1372. #address-cells = <0>;
  1373. interrupt-controller;
  1374. reg = <0x0 0xf1010000 0 0x1000>,
  1375. <0x0 0xf1020000 0 0x20000>,
  1376. <0x0 0xf1040000 0 0x20000>,
  1377. <0x0 0xf1060000 0 0x20000>;
  1378. interrupts = <GIC_PPI 9
  1379. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  1380. clocks = <&cpg CPG_MOD 408>;
  1381. clock-names = "clk";
  1382. power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
  1383. resets = <&cpg 408>;
  1384. };
  1385. pciec0: pcie@fe000000 {
  1386. reg = <0 0xfe000000 0 0x80000>;
  1387. #address-cells = <3>;
  1388. #size-cells = <2>;
  1389. status = "disabled";
  1390. /* placeholder */
  1391. };
  1392. hdmi0: hdmi@fead0000 {
  1393. reg = <0 0xfead0000 0 0x10000>;
  1394. status = "disabled";
  1395. /* placeholder */
  1396. ports {
  1397. #address-cells = <1>;
  1398. #size-cells = <0>;
  1399. port@0 {
  1400. reg = <0>;
  1401. };
  1402. port@1 {
  1403. reg = <1>;
  1404. };
  1405. port@2 {
  1406. reg = <2>;
  1407. };
  1408. };
  1409. };
  1410. du: display@feb00000 {
  1411. reg = <0 0xfeb00000 0 0x80000>;
  1412. status = "disabled";
  1413. /* placeholder */
  1414. ports {
  1415. #address-cells = <1>;
  1416. #size-cells = <0>;
  1417. port@0 {
  1418. reg = <0>;
  1419. };
  1420. port@1 {
  1421. reg = <1>;
  1422. };
  1423. port@2 {
  1424. reg = <2>;
  1425. };
  1426. };
  1427. };
  1428. prr: chipid@fff00044 {
  1429. compatible = "renesas,prr";
  1430. reg = <0 0xfff00044 0 4>;
  1431. };
  1432. };
  1433. thermal-zones {
  1434. sensor_thermal1: sensor-thermal1 {
  1435. polling-delay-passive = <250>;
  1436. polling-delay = <1000>;
  1437. thermal-sensors = <&tsc 0>;
  1438. sustainable-power = <6313>;
  1439. trips {
  1440. sensor1_crit: sensor1-crit {
  1441. temperature = <120000>;
  1442. hysteresis = <1000>;
  1443. type = "critical";
  1444. };
  1445. };
  1446. };
  1447. sensor_thermal2: sensor-thermal2 {
  1448. polling-delay-passive = <250>;
  1449. polling-delay = <1000>;
  1450. thermal-sensors = <&tsc 1>;
  1451. sustainable-power = <6313>;
  1452. trips {
  1453. sensor2_crit: sensor2-crit {
  1454. temperature = <120000>;
  1455. hysteresis = <1000>;
  1456. type = "critical";
  1457. };
  1458. };
  1459. };
  1460. sensor_thermal3: sensor-thermal3 {
  1461. polling-delay-passive = <250>;
  1462. polling-delay = <1000>;
  1463. thermal-sensors = <&tsc 2>;
  1464. sustainable-power = <6313>;
  1465. trips {
  1466. target: trip-point1 {
  1467. temperature = <100000>;
  1468. hysteresis = <1000>;
  1469. type = "passive";
  1470. };
  1471. sensor3_crit: sensor3-crit {
  1472. temperature = <120000>;
  1473. hysteresis = <1000>;
  1474. type = "critical";
  1475. };
  1476. };
  1477. cooling-maps {
  1478. map0 {
  1479. trip = <&target>;
  1480. cooling-device = <&a57_0 0 2>;
  1481. contribution = <1024>;
  1482. };
  1483. map1 {
  1484. trip = <&target>;
  1485. cooling-device = <&a53_0 0 2>;
  1486. contribution = <1024>;
  1487. };
  1488. };
  1489. };
  1490. };
  1491. timer {
  1492. compatible = "arm,armv8-timer";
  1493. interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  1494. <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  1495. <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  1496. <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
  1497. };
  1498. /* External USB clocks - can be overridden by the board */
  1499. usb3s0_clk: usb3s0 {
  1500. compatible = "fixed-clock";
  1501. #clock-cells = <0>;
  1502. clock-frequency = <0>;
  1503. };
  1504. usb_extal_clk: usb_extal {
  1505. compatible = "fixed-clock";
  1506. #clock-cells = <0>;
  1507. clock-frequency = <0>;
  1508. };
  1509. };