r8a774b1.dtsi 72 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the r8a774b1 SoC
  4. *
  5. * Copyright (C) 2020 Renesas Electronics Corp.
  6. */
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
  10. #include <dt-bindings/power/r8a774b1-sysc.h>
  11. #define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4
  12. / {
  13. compatible = "renesas,r8a774b1";
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. /*
  17. * The external audio clocks are configured as 0 Hz fixed frequency
  18. * clocks by default.
  19. * Boards that provide audio clocks should override them.
  20. */
  21. audio_clk_a: audio_clk_a {
  22. compatible = "fixed-clock";
  23. #clock-cells = <0>;
  24. clock-frequency = <0>;
  25. };
  26. audio_clk_b: audio_clk_b {
  27. compatible = "fixed-clock";
  28. #clock-cells = <0>;
  29. clock-frequency = <0>;
  30. };
  31. audio_clk_c: audio_clk_c {
  32. compatible = "fixed-clock";
  33. #clock-cells = <0>;
  34. clock-frequency = <0>;
  35. };
  36. /* External CAN clock - to be overridden by boards that provide it */
  37. can_clk: can {
  38. compatible = "fixed-clock";
  39. #clock-cells = <0>;
  40. clock-frequency = <0>;
  41. };
  42. cluster0_opp: opp_table0 {
  43. compatible = "operating-points-v2";
  44. opp-shared;
  45. opp-500000000 {
  46. opp-hz = /bits/ 64 <500000000>;
  47. opp-microvolt = <830000>;
  48. clock-latency-ns = <300000>;
  49. };
  50. opp-1000000000 {
  51. opp-hz = /bits/ 64 <1000000000>;
  52. opp-microvolt = <830000>;
  53. clock-latency-ns = <300000>;
  54. };
  55. opp-1500000000 {
  56. opp-hz = /bits/ 64 <1500000000>;
  57. opp-microvolt = <830000>;
  58. clock-latency-ns = <300000>;
  59. opp-suspend;
  60. };
  61. };
  62. cpus {
  63. #address-cells = <1>;
  64. #size-cells = <0>;
  65. a57_0: cpu@0 {
  66. compatible = "arm,cortex-a57";
  67. reg = <0x0>;
  68. device_type = "cpu";
  69. power-domains = <&sysc R8A774B1_PD_CA57_CPU0>;
  70. next-level-cache = <&L2_CA57>;
  71. enable-method = "psci";
  72. #cooling-cells = <2>;
  73. dynamic-power-coefficient = <854>;
  74. clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
  75. operating-points-v2 = <&cluster0_opp>;
  76. };
  77. a57_1: cpu@1 {
  78. compatible = "arm,cortex-a57";
  79. reg = <0x1>;
  80. device_type = "cpu";
  81. power-domains = <&sysc R8A774B1_PD_CA57_CPU1>;
  82. next-level-cache = <&L2_CA57>;
  83. enable-method = "psci";
  84. clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
  85. operating-points-v2 = <&cluster0_opp>;
  86. };
  87. L2_CA57: cache-controller-0 {
  88. compatible = "cache";
  89. power-domains = <&sysc R8A774B1_PD_CA57_SCU>;
  90. cache-unified;
  91. cache-level = <2>;
  92. };
  93. };
  94. extal_clk: extal {
  95. compatible = "fixed-clock";
  96. #clock-cells = <0>;
  97. /* This value must be overridden by the board */
  98. clock-frequency = <0>;
  99. };
  100. extalr_clk: extalr {
  101. compatible = "fixed-clock";
  102. #clock-cells = <0>;
  103. /* This value must be overridden by the board */
  104. clock-frequency = <0>;
  105. };
  106. /* External PCIe clock - can be overridden by the board */
  107. pcie_bus_clk: pcie_bus {
  108. compatible = "fixed-clock";
  109. #clock-cells = <0>;
  110. clock-frequency = <0>;
  111. };
  112. pmu_a57 {
  113. compatible = "arm,cortex-a57-pmu";
  114. interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  115. <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  116. interrupt-affinity = <&a57_0>, <&a57_1>;
  117. };
  118. psci {
  119. compatible = "arm,psci-1.0", "arm,psci-0.2";
  120. method = "smc";
  121. };
  122. /* External SCIF clock - to be overridden by boards that provide it */
  123. scif_clk: scif {
  124. compatible = "fixed-clock";
  125. #clock-cells = <0>;
  126. clock-frequency = <0>;
  127. };
  128. soc {
  129. compatible = "simple-bus";
  130. interrupt-parent = <&gic>;
  131. #address-cells = <2>;
  132. #size-cells = <2>;
  133. ranges;
  134. rwdt: watchdog@e6020000 {
  135. compatible = "renesas,r8a774b1-wdt",
  136. "renesas,rcar-gen3-wdt";
  137. reg = <0 0xe6020000 0 0x0c>;
  138. clocks = <&cpg CPG_MOD 402>;
  139. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  140. resets = <&cpg 402>;
  141. status = "disabled";
  142. };
  143. gpio0: gpio@e6050000 {
  144. compatible = "renesas,gpio-r8a774b1",
  145. "renesas,rcar-gen3-gpio";
  146. reg = <0 0xe6050000 0 0x50>;
  147. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  148. #gpio-cells = <2>;
  149. gpio-controller;
  150. gpio-ranges = <&pfc 0 0 16>;
  151. #interrupt-cells = <2>;
  152. interrupt-controller;
  153. clocks = <&cpg CPG_MOD 912>;
  154. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  155. resets = <&cpg 912>;
  156. };
  157. gpio1: gpio@e6051000 {
  158. compatible = "renesas,gpio-r8a774b1",
  159. "renesas,rcar-gen3-gpio";
  160. reg = <0 0xe6051000 0 0x50>;
  161. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  162. #gpio-cells = <2>;
  163. gpio-controller;
  164. gpio-ranges = <&pfc 0 32 29>;
  165. #interrupt-cells = <2>;
  166. interrupt-controller;
  167. clocks = <&cpg CPG_MOD 911>;
  168. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  169. resets = <&cpg 911>;
  170. };
  171. gpio2: gpio@e6052000 {
  172. compatible = "renesas,gpio-r8a774b1",
  173. "renesas,rcar-gen3-gpio";
  174. reg = <0 0xe6052000 0 0x50>;
  175. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  176. #gpio-cells = <2>;
  177. gpio-controller;
  178. gpio-ranges = <&pfc 0 64 15>;
  179. #interrupt-cells = <2>;
  180. interrupt-controller;
  181. clocks = <&cpg CPG_MOD 910>;
  182. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  183. resets = <&cpg 910>;
  184. };
  185. gpio3: gpio@e6053000 {
  186. compatible = "renesas,gpio-r8a774b1",
  187. "renesas,rcar-gen3-gpio";
  188. reg = <0 0xe6053000 0 0x50>;
  189. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  190. #gpio-cells = <2>;
  191. gpio-controller;
  192. gpio-ranges = <&pfc 0 96 16>;
  193. #interrupt-cells = <2>;
  194. interrupt-controller;
  195. clocks = <&cpg CPG_MOD 909>;
  196. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  197. resets = <&cpg 909>;
  198. };
  199. gpio4: gpio@e6054000 {
  200. compatible = "renesas,gpio-r8a774b1",
  201. "renesas,rcar-gen3-gpio";
  202. reg = <0 0xe6054000 0 0x50>;
  203. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  204. #gpio-cells = <2>;
  205. gpio-controller;
  206. gpio-ranges = <&pfc 0 128 18>;
  207. #interrupt-cells = <2>;
  208. interrupt-controller;
  209. clocks = <&cpg CPG_MOD 908>;
  210. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  211. resets = <&cpg 908>;
  212. };
  213. gpio5: gpio@e6055000 {
  214. compatible = "renesas,gpio-r8a774b1",
  215. "renesas,rcar-gen3-gpio";
  216. reg = <0 0xe6055000 0 0x50>;
  217. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  218. #gpio-cells = <2>;
  219. gpio-controller;
  220. gpio-ranges = <&pfc 0 160 26>;
  221. #interrupt-cells = <2>;
  222. interrupt-controller;
  223. clocks = <&cpg CPG_MOD 907>;
  224. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  225. resets = <&cpg 907>;
  226. };
  227. gpio6: gpio@e6055400 {
  228. compatible = "renesas,gpio-r8a774b1",
  229. "renesas,rcar-gen3-gpio";
  230. reg = <0 0xe6055400 0 0x50>;
  231. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  232. #gpio-cells = <2>;
  233. gpio-controller;
  234. gpio-ranges = <&pfc 0 192 32>;
  235. #interrupt-cells = <2>;
  236. interrupt-controller;
  237. clocks = <&cpg CPG_MOD 906>;
  238. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  239. resets = <&cpg 906>;
  240. };
  241. gpio7: gpio@e6055800 {
  242. compatible = "renesas,gpio-r8a774b1",
  243. "renesas,rcar-gen3-gpio";
  244. reg = <0 0xe6055800 0 0x50>;
  245. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  246. #gpio-cells = <2>;
  247. gpio-controller;
  248. gpio-ranges = <&pfc 0 224 4>;
  249. #interrupt-cells = <2>;
  250. interrupt-controller;
  251. clocks = <&cpg CPG_MOD 905>;
  252. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  253. resets = <&cpg 905>;
  254. };
  255. pfc: pin-controller@e6060000 {
  256. compatible = "renesas,pfc-r8a774b1";
  257. reg = <0 0xe6060000 0 0x50c>;
  258. };
  259. cmt0: timer@e60f0000 {
  260. compatible = "renesas,r8a774b1-cmt0",
  261. "renesas,rcar-gen3-cmt0";
  262. reg = <0 0xe60f0000 0 0x1004>;
  263. interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  264. <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  265. clocks = <&cpg CPG_MOD 303>;
  266. clock-names = "fck";
  267. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  268. resets = <&cpg 303>;
  269. status = "disabled";
  270. };
  271. cmt1: timer@e6130000 {
  272. compatible = "renesas,r8a774b1-cmt1",
  273. "renesas,rcar-gen3-cmt1";
  274. reg = <0 0xe6130000 0 0x1004>;
  275. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  276. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  277. <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  278. <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  279. <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  280. <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  281. <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  282. <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  283. clocks = <&cpg CPG_MOD 302>;
  284. clock-names = "fck";
  285. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  286. resets = <&cpg 302>;
  287. status = "disabled";
  288. };
  289. cmt2: timer@e6140000 {
  290. compatible = "renesas,r8a774b1-cmt1",
  291. "renesas,rcar-gen3-cmt1";
  292. reg = <0 0xe6140000 0 0x1004>;
  293. interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
  294. <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
  295. <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
  296. <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
  297. <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
  298. <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
  299. <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
  300. <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
  301. clocks = <&cpg CPG_MOD 301>;
  302. clock-names = "fck";
  303. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  304. resets = <&cpg 301>;
  305. status = "disabled";
  306. };
  307. cmt3: timer@e6148000 {
  308. compatible = "renesas,r8a774b1-cmt1",
  309. "renesas,rcar-gen3-cmt1";
  310. reg = <0 0xe6148000 0 0x1004>;
  311. interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
  312. <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
  313. <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
  314. <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
  315. <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
  316. <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
  317. <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
  318. <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
  319. clocks = <&cpg CPG_MOD 300>;
  320. clock-names = "fck";
  321. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  322. resets = <&cpg 300>;
  323. status = "disabled";
  324. };
  325. cpg: clock-controller@e6150000 {
  326. compatible = "renesas,r8a774b1-cpg-mssr";
  327. reg = <0 0xe6150000 0 0x1000>;
  328. clocks = <&extal_clk>, <&extalr_clk>;
  329. clock-names = "extal", "extalr";
  330. #clock-cells = <2>;
  331. #power-domain-cells = <0>;
  332. #reset-cells = <1>;
  333. };
  334. rst: reset-controller@e6160000 {
  335. compatible = "renesas,r8a774b1-rst";
  336. reg = <0 0xe6160000 0 0x0200>;
  337. };
  338. sysc: system-controller@e6180000 {
  339. compatible = "renesas,r8a774b1-sysc";
  340. reg = <0 0xe6180000 0 0x0400>;
  341. #power-domain-cells = <1>;
  342. };
  343. tsc: thermal@e6198000 {
  344. compatible = "renesas,r8a774b1-thermal";
  345. reg = <0 0xe6198000 0 0x100>,
  346. <0 0xe61a0000 0 0x100>,
  347. <0 0xe61a8000 0 0x100>;
  348. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
  349. <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  350. <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  351. clocks = <&cpg CPG_MOD 522>;
  352. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  353. resets = <&cpg 522>;
  354. #thermal-sensor-cells = <1>;
  355. };
  356. intc_ex: interrupt-controller@e61c0000 {
  357. compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
  358. #interrupt-cells = <2>;
  359. interrupt-controller;
  360. reg = <0 0xe61c0000 0 0x200>;
  361. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  362. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  363. <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  364. <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  365. <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  366. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
  367. clocks = <&cpg CPG_MOD 407>;
  368. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  369. resets = <&cpg 407>;
  370. };
  371. tmu0: timer@e61e0000 {
  372. compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
  373. reg = <0 0xe61e0000 0 0x30>;
  374. interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  375. <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  376. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  377. clocks = <&cpg CPG_MOD 125>;
  378. clock-names = "fck";
  379. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  380. resets = <&cpg 125>;
  381. status = "disabled";
  382. };
  383. tmu1: timer@e6fc0000 {
  384. compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
  385. reg = <0 0xe6fc0000 0 0x30>;
  386. interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  387. <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
  388. <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  389. clocks = <&cpg CPG_MOD 124>;
  390. clock-names = "fck";
  391. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  392. resets = <&cpg 124>;
  393. status = "disabled";
  394. };
  395. tmu2: timer@e6fd0000 {
  396. compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
  397. reg = <0 0xe6fd0000 0 0x30>;
  398. interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
  399. <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  400. <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
  401. clocks = <&cpg CPG_MOD 123>;
  402. clock-names = "fck";
  403. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  404. resets = <&cpg 123>;
  405. status = "disabled";
  406. };
  407. tmu3: timer@e6fe0000 {
  408. compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
  409. reg = <0 0xe6fe0000 0 0x30>;
  410. interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  411. <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
  412. <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  413. clocks = <&cpg CPG_MOD 122>;
  414. clock-names = "fck";
  415. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  416. resets = <&cpg 122>;
  417. status = "disabled";
  418. };
  419. tmu4: timer@ffc00000 {
  420. compatible = "renesas,tmu-r8a774b1", "renesas,tmu";
  421. reg = <0 0xffc00000 0 0x30>;
  422. interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
  423. <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
  424. <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
  425. clocks = <&cpg CPG_MOD 121>;
  426. clock-names = "fck";
  427. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  428. resets = <&cpg 121>;
  429. status = "disabled";
  430. };
  431. i2c0: i2c@e6500000 {
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. compatible = "renesas,i2c-r8a774b1",
  435. "renesas,rcar-gen3-i2c";
  436. reg = <0 0xe6500000 0 0x40>;
  437. interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
  438. clocks = <&cpg CPG_MOD 931>;
  439. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  440. resets = <&cpg 931>;
  441. dmas = <&dmac1 0x91>, <&dmac1 0x90>,
  442. <&dmac2 0x91>, <&dmac2 0x90>;
  443. dma-names = "tx", "rx", "tx", "rx";
  444. i2c-scl-internal-delay-ns = <110>;
  445. status = "disabled";
  446. };
  447. i2c1: i2c@e6508000 {
  448. #address-cells = <1>;
  449. #size-cells = <0>;
  450. compatible = "renesas,i2c-r8a774b1",
  451. "renesas,rcar-gen3-i2c";
  452. reg = <0 0xe6508000 0 0x40>;
  453. interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
  454. clocks = <&cpg CPG_MOD 930>;
  455. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  456. resets = <&cpg 930>;
  457. dmas = <&dmac1 0x93>, <&dmac1 0x92>,
  458. <&dmac2 0x93>, <&dmac2 0x92>;
  459. dma-names = "tx", "rx", "tx", "rx";
  460. i2c-scl-internal-delay-ns = <6>;
  461. status = "disabled";
  462. };
  463. i2c2: i2c@e6510000 {
  464. #address-cells = <1>;
  465. #size-cells = <0>;
  466. compatible = "renesas,i2c-r8a774b1",
  467. "renesas,rcar-gen3-i2c";
  468. reg = <0 0xe6510000 0 0x40>;
  469. interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
  470. clocks = <&cpg CPG_MOD 929>;
  471. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  472. resets = <&cpg 929>;
  473. dmas = <&dmac1 0x95>, <&dmac1 0x94>,
  474. <&dmac2 0x95>, <&dmac2 0x94>;
  475. dma-names = "tx", "rx", "tx", "rx";
  476. i2c-scl-internal-delay-ns = <6>;
  477. status = "disabled";
  478. };
  479. i2c3: i2c@e66d0000 {
  480. #address-cells = <1>;
  481. #size-cells = <0>;
  482. compatible = "renesas,i2c-r8a774b1",
  483. "renesas,rcar-gen3-i2c";
  484. reg = <0 0xe66d0000 0 0x40>;
  485. interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
  486. clocks = <&cpg CPG_MOD 928>;
  487. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  488. resets = <&cpg 928>;
  489. dmas = <&dmac0 0x97>, <&dmac0 0x96>;
  490. dma-names = "tx", "rx";
  491. i2c-scl-internal-delay-ns = <110>;
  492. status = "disabled";
  493. };
  494. i2c4: i2c@e66d8000 {
  495. #address-cells = <1>;
  496. #size-cells = <0>;
  497. compatible = "renesas,i2c-r8a774b1",
  498. "renesas,rcar-gen3-i2c";
  499. reg = <0 0xe66d8000 0 0x40>;
  500. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  501. clocks = <&cpg CPG_MOD 927>;
  502. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  503. resets = <&cpg 927>;
  504. dmas = <&dmac0 0x99>, <&dmac0 0x98>;
  505. dma-names = "tx", "rx";
  506. i2c-scl-internal-delay-ns = <110>;
  507. status = "disabled";
  508. };
  509. i2c5: i2c@e66e0000 {
  510. #address-cells = <1>;
  511. #size-cells = <0>;
  512. compatible = "renesas,i2c-r8a774b1",
  513. "renesas,rcar-gen3-i2c";
  514. reg = <0 0xe66e0000 0 0x40>;
  515. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  516. clocks = <&cpg CPG_MOD 919>;
  517. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  518. resets = <&cpg 919>;
  519. dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
  520. dma-names = "tx", "rx";
  521. i2c-scl-internal-delay-ns = <110>;
  522. status = "disabled";
  523. };
  524. i2c6: i2c@e66e8000 {
  525. #address-cells = <1>;
  526. #size-cells = <0>;
  527. compatible = "renesas,i2c-r8a774b1",
  528. "renesas,rcar-gen3-i2c";
  529. reg = <0 0xe66e8000 0 0x40>;
  530. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  531. clocks = <&cpg CPG_MOD 918>;
  532. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  533. resets = <&cpg 918>;
  534. dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
  535. dma-names = "tx", "rx";
  536. i2c-scl-internal-delay-ns = <6>;
  537. status = "disabled";
  538. };
  539. i2c_dvfs: i2c@e60b0000 {
  540. #address-cells = <1>;
  541. #size-cells = <0>;
  542. compatible = "renesas,iic-r8a774b1",
  543. "renesas,rcar-gen3-iic",
  544. "renesas,rmobile-iic";
  545. reg = <0 0xe60b0000 0 0x425>;
  546. interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
  547. clocks = <&cpg CPG_MOD 926>;
  548. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  549. resets = <&cpg 926>;
  550. dmas = <&dmac0 0x11>, <&dmac0 0x10>;
  551. dma-names = "tx", "rx";
  552. status = "disabled";
  553. };
  554. hscif0: serial@e6540000 {
  555. compatible = "renesas,hscif-r8a774b1",
  556. "renesas,rcar-gen3-hscif",
  557. "renesas,hscif";
  558. reg = <0 0xe6540000 0 0x60>;
  559. interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  560. clocks = <&cpg CPG_MOD 520>,
  561. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  562. <&scif_clk>;
  563. clock-names = "fck", "brg_int", "scif_clk";
  564. dmas = <&dmac1 0x31>, <&dmac1 0x30>,
  565. <&dmac2 0x31>, <&dmac2 0x30>;
  566. dma-names = "tx", "rx", "tx", "rx";
  567. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  568. resets = <&cpg 520>;
  569. status = "disabled";
  570. };
  571. hscif1: serial@e6550000 {
  572. compatible = "renesas,hscif-r8a774b1",
  573. "renesas,rcar-gen3-hscif",
  574. "renesas,hscif";
  575. reg = <0 0xe6550000 0 0x60>;
  576. interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  577. clocks = <&cpg CPG_MOD 519>,
  578. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  579. <&scif_clk>;
  580. clock-names = "fck", "brg_int", "scif_clk";
  581. dmas = <&dmac1 0x33>, <&dmac1 0x32>,
  582. <&dmac2 0x33>, <&dmac2 0x32>;
  583. dma-names = "tx", "rx", "tx", "rx";
  584. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  585. resets = <&cpg 519>;
  586. status = "disabled";
  587. };
  588. hscif2: serial@e6560000 {
  589. compatible = "renesas,hscif-r8a774b1",
  590. "renesas,rcar-gen3-hscif",
  591. "renesas,hscif";
  592. reg = <0 0xe6560000 0 0x60>;
  593. interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
  594. clocks = <&cpg CPG_MOD 518>,
  595. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  596. <&scif_clk>;
  597. clock-names = "fck", "brg_int", "scif_clk";
  598. dmas = <&dmac1 0x35>, <&dmac1 0x34>,
  599. <&dmac2 0x35>, <&dmac2 0x34>;
  600. dma-names = "tx", "rx", "tx", "rx";
  601. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  602. resets = <&cpg 518>;
  603. status = "disabled";
  604. };
  605. hscif3: serial@e66a0000 {
  606. compatible = "renesas,hscif-r8a774b1",
  607. "renesas,rcar-gen3-hscif",
  608. "renesas,hscif";
  609. reg = <0 0xe66a0000 0 0x60>;
  610. interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
  611. clocks = <&cpg CPG_MOD 517>,
  612. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  613. <&scif_clk>;
  614. clock-names = "fck", "brg_int", "scif_clk";
  615. dmas = <&dmac0 0x37>, <&dmac0 0x36>;
  616. dma-names = "tx", "rx";
  617. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  618. resets = <&cpg 517>;
  619. status = "disabled";
  620. };
  621. hscif4: serial@e66b0000 {
  622. compatible = "renesas,hscif-r8a774b1",
  623. "renesas,rcar-gen3-hscif",
  624. "renesas,hscif";
  625. reg = <0 0xe66b0000 0 0x60>;
  626. interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  627. clocks = <&cpg CPG_MOD 516>,
  628. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  629. <&scif_clk>;
  630. clock-names = "fck", "brg_int", "scif_clk";
  631. dmas = <&dmac0 0x39>, <&dmac0 0x38>;
  632. dma-names = "tx", "rx";
  633. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  634. resets = <&cpg 516>;
  635. status = "disabled";
  636. };
  637. hsusb: usb@e6590000 {
  638. compatible = "renesas,usbhs-r8a774b1",
  639. "renesas,rcar-gen3-usbhs";
  640. reg = <0 0xe6590000 0 0x200>;
  641. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  642. clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
  643. dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
  644. <&usb_dmac1 0>, <&usb_dmac1 1>;
  645. dma-names = "ch0", "ch1", "ch2", "ch3";
  646. renesas,buswait = <11>;
  647. phys = <&usb2_phy0 3>;
  648. phy-names = "usb";
  649. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  650. resets = <&cpg 704>, <&cpg 703>;
  651. status = "disabled";
  652. };
  653. usb_dmac0: dma-controller@e65a0000 {
  654. compatible = "renesas,r8a774b1-usb-dmac",
  655. "renesas,usb-dmac";
  656. reg = <0 0xe65a0000 0 0x100>;
  657. interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  658. <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  659. interrupt-names = "ch0", "ch1";
  660. clocks = <&cpg CPG_MOD 330>;
  661. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  662. resets = <&cpg 330>;
  663. #dma-cells = <1>;
  664. dma-channels = <2>;
  665. };
  666. usb_dmac1: dma-controller@e65b0000 {
  667. compatible = "renesas,r8a774b1-usb-dmac",
  668. "renesas,usb-dmac";
  669. reg = <0 0xe65b0000 0 0x100>;
  670. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  671. <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  672. interrupt-names = "ch0", "ch1";
  673. clocks = <&cpg CPG_MOD 331>;
  674. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  675. resets = <&cpg 331>;
  676. #dma-cells = <1>;
  677. dma-channels = <2>;
  678. };
  679. usb3_phy0: usb-phy@e65ee000 {
  680. compatible = "renesas,r8a774b1-usb3-phy",
  681. "renesas,rcar-gen3-usb3-phy";
  682. reg = <0 0xe65ee000 0 0x90>;
  683. clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
  684. <&usb_extal_clk>;
  685. clock-names = "usb3-if", "usb3s_clk", "usb_extal";
  686. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  687. resets = <&cpg 328>;
  688. #phy-cells = <0>;
  689. status = "disabled";
  690. };
  691. dmac0: dma-controller@e6700000 {
  692. compatible = "renesas,dmac-r8a774b1",
  693. "renesas,rcar-dmac";
  694. reg = <0 0xe6700000 0 0x10000>;
  695. interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
  696. <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
  697. <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
  698. <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
  699. <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
  700. <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
  701. <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
  702. <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
  703. <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
  704. <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
  705. <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
  706. <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
  707. <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
  708. <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
  709. <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
  710. <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
  711. <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
  712. interrupt-names = "error",
  713. "ch0", "ch1", "ch2", "ch3",
  714. "ch4", "ch5", "ch6", "ch7",
  715. "ch8", "ch9", "ch10", "ch11",
  716. "ch12", "ch13", "ch14", "ch15";
  717. clocks = <&cpg CPG_MOD 219>;
  718. clock-names = "fck";
  719. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  720. resets = <&cpg 219>;
  721. #dma-cells = <1>;
  722. dma-channels = <16>;
  723. iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
  724. <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
  725. <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
  726. <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
  727. <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
  728. <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
  729. <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
  730. <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
  731. };
  732. dmac1: dma-controller@e7300000 {
  733. compatible = "renesas,dmac-r8a774b1",
  734. "renesas,rcar-dmac";
  735. reg = <0 0xe7300000 0 0x10000>;
  736. interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
  737. <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
  738. <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
  739. <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
  740. <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
  741. <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
  742. <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  743. <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  744. <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  745. <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  746. <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
  747. <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
  748. <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
  749. <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
  750. <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
  751. <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
  752. <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
  753. interrupt-names = "error",
  754. "ch0", "ch1", "ch2", "ch3",
  755. "ch4", "ch5", "ch6", "ch7",
  756. "ch8", "ch9", "ch10", "ch11",
  757. "ch12", "ch13", "ch14", "ch15";
  758. clocks = <&cpg CPG_MOD 218>;
  759. clock-names = "fck";
  760. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  761. resets = <&cpg 218>;
  762. #dma-cells = <1>;
  763. dma-channels = <16>;
  764. iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
  765. <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
  766. <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
  767. <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
  768. <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
  769. <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
  770. <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
  771. <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
  772. };
  773. dmac2: dma-controller@e7310000 {
  774. compatible = "renesas,dmac-r8a774b1",
  775. "renesas,rcar-dmac";
  776. reg = <0 0xe7310000 0 0x10000>;
  777. interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
  778. <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
  779. <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
  780. <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
  781. <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
  782. <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
  783. <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
  784. <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
  785. <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
  786. <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
  787. <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
  788. <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
  789. <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
  790. <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
  791. <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
  792. <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
  793. <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
  794. interrupt-names = "error",
  795. "ch0", "ch1", "ch2", "ch3",
  796. "ch4", "ch5", "ch6", "ch7",
  797. "ch8", "ch9", "ch10", "ch11",
  798. "ch12", "ch13", "ch14", "ch15";
  799. clocks = <&cpg CPG_MOD 217>;
  800. clock-names = "fck";
  801. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  802. resets = <&cpg 217>;
  803. #dma-cells = <1>;
  804. dma-channels = <16>;
  805. iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
  806. <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
  807. <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
  808. <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
  809. <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
  810. <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
  811. <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
  812. <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
  813. };
  814. ipmmu_ds0: iommu@e6740000 {
  815. compatible = "renesas,ipmmu-r8a774b1";
  816. reg = <0 0xe6740000 0 0x1000>;
  817. renesas,ipmmu-main = <&ipmmu_mm 0>;
  818. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  819. #iommu-cells = <1>;
  820. };
  821. ipmmu_ds1: iommu@e7740000 {
  822. compatible = "renesas,ipmmu-r8a774b1";
  823. reg = <0 0xe7740000 0 0x1000>;
  824. renesas,ipmmu-main = <&ipmmu_mm 1>;
  825. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  826. #iommu-cells = <1>;
  827. };
  828. ipmmu_hc: iommu@e6570000 {
  829. compatible = "renesas,ipmmu-r8a774b1";
  830. reg = <0 0xe6570000 0 0x1000>;
  831. renesas,ipmmu-main = <&ipmmu_mm 2>;
  832. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  833. #iommu-cells = <1>;
  834. };
  835. ipmmu_mm: iommu@e67b0000 {
  836. compatible = "renesas,ipmmu-r8a774b1";
  837. reg = <0 0xe67b0000 0 0x1000>;
  838. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
  839. <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
  840. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  841. #iommu-cells = <1>;
  842. };
  843. ipmmu_mp: iommu@ec670000 {
  844. compatible = "renesas,ipmmu-r8a774b1";
  845. reg = <0 0xec670000 0 0x1000>;
  846. renesas,ipmmu-main = <&ipmmu_mm 4>;
  847. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  848. #iommu-cells = <1>;
  849. };
  850. ipmmu_pv0: iommu@fd800000 {
  851. compatible = "renesas,ipmmu-r8a774b1";
  852. reg = <0 0xfd800000 0 0x1000>;
  853. renesas,ipmmu-main = <&ipmmu_mm 6>;
  854. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  855. #iommu-cells = <1>;
  856. };
  857. ipmmu_vc0: iommu@fe6b0000 {
  858. compatible = "renesas,ipmmu-r8a774b1";
  859. reg = <0 0xfe6b0000 0 0x1000>;
  860. renesas,ipmmu-main = <&ipmmu_mm 12>;
  861. power-domains = <&sysc R8A774B1_PD_A3VC>;
  862. #iommu-cells = <1>;
  863. };
  864. ipmmu_vi0: iommu@febd0000 {
  865. compatible = "renesas,ipmmu-r8a774b1";
  866. reg = <0 0xfebd0000 0 0x1000>;
  867. renesas,ipmmu-main = <&ipmmu_mm 14>;
  868. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  869. #iommu-cells = <1>;
  870. };
  871. ipmmu_vp0: iommu@fe990000 {
  872. compatible = "renesas,ipmmu-r8a774b1";
  873. reg = <0 0xfe990000 0 0x1000>;
  874. renesas,ipmmu-main = <&ipmmu_mm 16>;
  875. power-domains = <&sysc R8A774B1_PD_A3VP>;
  876. #iommu-cells = <1>;
  877. };
  878. avb: ethernet@e6800000 {
  879. compatible = "renesas,etheravb-r8a774b1",
  880. "renesas,etheravb-rcar-gen3";
  881. reg = <0 0xe6800000 0 0x800>;
  882. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
  883. <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  884. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  885. <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  886. <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
  887. <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
  888. <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
  889. <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
  890. <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  891. <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
  892. <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
  893. <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
  894. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  895. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  896. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  897. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  898. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  899. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  900. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  901. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  902. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  903. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  904. <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  905. <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  906. <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  907. interrupt-names = "ch0", "ch1", "ch2", "ch3",
  908. "ch4", "ch5", "ch6", "ch7",
  909. "ch8", "ch9", "ch10", "ch11",
  910. "ch12", "ch13", "ch14", "ch15",
  911. "ch16", "ch17", "ch18", "ch19",
  912. "ch20", "ch21", "ch22", "ch23",
  913. "ch24";
  914. clocks = <&cpg CPG_MOD 812>;
  915. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  916. resets = <&cpg 812>;
  917. phy-mode = "rgmii";
  918. iommus = <&ipmmu_ds0 16>;
  919. #address-cells = <1>;
  920. #size-cells = <0>;
  921. status = "disabled";
  922. };
  923. can0: can@e6c30000 {
  924. compatible = "renesas,can-r8a774b1",
  925. "renesas,rcar-gen3-can";
  926. reg = <0 0xe6c30000 0 0x1000>;
  927. interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
  928. clocks = <&cpg CPG_MOD 916>,
  929. <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
  930. <&can_clk>;
  931. clock-names = "clkp1", "clkp2", "can_clk";
  932. assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
  933. assigned-clock-rates = <40000000>;
  934. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  935. resets = <&cpg 916>;
  936. status = "disabled";
  937. };
  938. can1: can@e6c38000 {
  939. compatible = "renesas,can-r8a774b1",
  940. "renesas,rcar-gen3-can";
  941. reg = <0 0xe6c38000 0 0x1000>;
  942. interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
  943. clocks = <&cpg CPG_MOD 915>,
  944. <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
  945. <&can_clk>;
  946. clock-names = "clkp1", "clkp2", "can_clk";
  947. assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
  948. assigned-clock-rates = <40000000>;
  949. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  950. resets = <&cpg 915>;
  951. status = "disabled";
  952. };
  953. canfd: can@e66c0000 {
  954. compatible = "renesas,r8a774b1-canfd",
  955. "renesas,rcar-gen3-canfd";
  956. reg = <0 0xe66c0000 0 0x8000>;
  957. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  958. <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  959. clocks = <&cpg CPG_MOD 914>,
  960. <&cpg CPG_CORE R8A774B1_CLK_CANFD>,
  961. <&can_clk>;
  962. clock-names = "fck", "canfd", "can_clk";
  963. assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
  964. assigned-clock-rates = <40000000>;
  965. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  966. resets = <&cpg 914>;
  967. status = "disabled";
  968. channel0 {
  969. status = "disabled";
  970. };
  971. channel1 {
  972. status = "disabled";
  973. };
  974. };
  975. pwm0: pwm@e6e30000 {
  976. compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
  977. reg = <0 0xe6e30000 0 0x8>;
  978. #pwm-cells = <2>;
  979. clocks = <&cpg CPG_MOD 523>;
  980. resets = <&cpg 523>;
  981. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  982. status = "disabled";
  983. };
  984. pwm1: pwm@e6e31000 {
  985. compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
  986. reg = <0 0xe6e31000 0 0x8>;
  987. #pwm-cells = <2>;
  988. clocks = <&cpg CPG_MOD 523>;
  989. resets = <&cpg 523>;
  990. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  991. status = "disabled";
  992. };
  993. pwm2: pwm@e6e32000 {
  994. compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
  995. reg = <0 0xe6e32000 0 0x8>;
  996. #pwm-cells = <2>;
  997. clocks = <&cpg CPG_MOD 523>;
  998. resets = <&cpg 523>;
  999. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1000. status = "disabled";
  1001. };
  1002. pwm3: pwm@e6e33000 {
  1003. compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
  1004. reg = <0 0xe6e33000 0 0x8>;
  1005. #pwm-cells = <2>;
  1006. clocks = <&cpg CPG_MOD 523>;
  1007. resets = <&cpg 523>;
  1008. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1009. status = "disabled";
  1010. };
  1011. pwm4: pwm@e6e34000 {
  1012. compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
  1013. reg = <0 0xe6e34000 0 0x8>;
  1014. #pwm-cells = <2>;
  1015. clocks = <&cpg CPG_MOD 523>;
  1016. resets = <&cpg 523>;
  1017. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1018. status = "disabled";
  1019. };
  1020. pwm5: pwm@e6e35000 {
  1021. compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
  1022. reg = <0 0xe6e35000 0 0x8>;
  1023. #pwm-cells = <2>;
  1024. clocks = <&cpg CPG_MOD 523>;
  1025. resets = <&cpg 523>;
  1026. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1027. status = "disabled";
  1028. };
  1029. pwm6: pwm@e6e36000 {
  1030. compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar";
  1031. reg = <0 0xe6e36000 0 0x8>;
  1032. #pwm-cells = <2>;
  1033. clocks = <&cpg CPG_MOD 523>;
  1034. resets = <&cpg 523>;
  1035. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1036. status = "disabled";
  1037. };
  1038. scif0: serial@e6e60000 {
  1039. compatible = "renesas,scif-r8a774b1",
  1040. "renesas,rcar-gen3-scif", "renesas,scif";
  1041. reg = <0 0xe6e60000 0 0x40>;
  1042. interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
  1043. clocks = <&cpg CPG_MOD 207>,
  1044. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  1045. <&scif_clk>;
  1046. clock-names = "fck", "brg_int", "scif_clk";
  1047. dmas = <&dmac1 0x51>, <&dmac1 0x50>,
  1048. <&dmac2 0x51>, <&dmac2 0x50>;
  1049. dma-names = "tx", "rx", "tx", "rx";
  1050. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1051. resets = <&cpg 207>;
  1052. status = "disabled";
  1053. };
  1054. scif1: serial@e6e68000 {
  1055. compatible = "renesas,scif-r8a774b1",
  1056. "renesas,rcar-gen3-scif", "renesas,scif";
  1057. reg = <0 0xe6e68000 0 0x40>;
  1058. interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  1059. clocks = <&cpg CPG_MOD 206>,
  1060. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  1061. <&scif_clk>;
  1062. clock-names = "fck", "brg_int", "scif_clk";
  1063. dmas = <&dmac1 0x53>, <&dmac1 0x52>,
  1064. <&dmac2 0x53>, <&dmac2 0x52>;
  1065. dma-names = "tx", "rx", "tx", "rx";
  1066. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1067. resets = <&cpg 206>;
  1068. status = "disabled";
  1069. };
  1070. scif2: serial@e6e88000 {
  1071. compatible = "renesas,scif-r8a774b1",
  1072. "renesas,rcar-gen3-scif", "renesas,scif";
  1073. reg = <0 0xe6e88000 0 0x40>;
  1074. interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  1075. clocks = <&cpg CPG_MOD 310>,
  1076. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  1077. <&scif_clk>;
  1078. clock-names = "fck", "brg_int", "scif_clk";
  1079. dmas = <&dmac1 0x13>, <&dmac1 0x12>,
  1080. <&dmac2 0x13>, <&dmac2 0x12>;
  1081. dma-names = "tx", "rx", "tx", "rx";
  1082. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1083. resets = <&cpg 310>;
  1084. status = "disabled";
  1085. };
  1086. scif3: serial@e6c50000 {
  1087. compatible = "renesas,scif-r8a774b1",
  1088. "renesas,rcar-gen3-scif", "renesas,scif";
  1089. reg = <0 0xe6c50000 0 0x40>;
  1090. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  1091. clocks = <&cpg CPG_MOD 204>,
  1092. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  1093. <&scif_clk>;
  1094. clock-names = "fck", "brg_int", "scif_clk";
  1095. dmas = <&dmac0 0x57>, <&dmac0 0x56>;
  1096. dma-names = "tx", "rx";
  1097. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1098. resets = <&cpg 204>;
  1099. status = "disabled";
  1100. };
  1101. scif4: serial@e6c40000 {
  1102. compatible = "renesas,scif-r8a774b1",
  1103. "renesas,rcar-gen3-scif", "renesas,scif";
  1104. reg = <0 0xe6c40000 0 0x40>;
  1105. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  1106. clocks = <&cpg CPG_MOD 203>,
  1107. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  1108. <&scif_clk>;
  1109. clock-names = "fck", "brg_int", "scif_clk";
  1110. dmas = <&dmac0 0x59>, <&dmac0 0x58>;
  1111. dma-names = "tx", "rx";
  1112. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1113. resets = <&cpg 203>;
  1114. status = "disabled";
  1115. };
  1116. scif5: serial@e6f30000 {
  1117. compatible = "renesas,scif-r8a774b1",
  1118. "renesas,rcar-gen3-scif", "renesas,scif";
  1119. reg = <0 0xe6f30000 0 0x40>;
  1120. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  1121. clocks = <&cpg CPG_MOD 202>,
  1122. <&cpg CPG_CORE R8A774B1_CLK_S3D1>,
  1123. <&scif_clk>;
  1124. clock-names = "fck", "brg_int", "scif_clk";
  1125. dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
  1126. <&dmac2 0x5b>, <&dmac2 0x5a>;
  1127. dma-names = "tx", "rx", "tx", "rx";
  1128. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1129. resets = <&cpg 202>;
  1130. status = "disabled";
  1131. };
  1132. msiof0: spi@e6e90000 {
  1133. compatible = "renesas,msiof-r8a774b1",
  1134. "renesas,rcar-gen3-msiof";
  1135. reg = <0 0xe6e90000 0 0x0064>;
  1136. interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
  1137. clocks = <&cpg CPG_MOD 211>;
  1138. dmas = <&dmac1 0x41>, <&dmac1 0x40>,
  1139. <&dmac2 0x41>, <&dmac2 0x40>;
  1140. dma-names = "tx", "rx", "tx", "rx";
  1141. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1142. resets = <&cpg 211>;
  1143. #address-cells = <1>;
  1144. #size-cells = <0>;
  1145. status = "disabled";
  1146. };
  1147. msiof1: spi@e6ea0000 {
  1148. compatible = "renesas,msiof-r8a774b1",
  1149. "renesas,rcar-gen3-msiof";
  1150. reg = <0 0xe6ea0000 0 0x0064>;
  1151. interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  1152. clocks = <&cpg CPG_MOD 210>;
  1153. dmas = <&dmac1 0x43>, <&dmac1 0x42>,
  1154. <&dmac2 0x43>, <&dmac2 0x42>;
  1155. dma-names = "tx", "rx", "tx", "rx";
  1156. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1157. resets = <&cpg 210>;
  1158. #address-cells = <1>;
  1159. #size-cells = <0>;
  1160. status = "disabled";
  1161. };
  1162. msiof2: spi@e6c00000 {
  1163. compatible = "renesas,msiof-r8a774b1",
  1164. "renesas,rcar-gen3-msiof";
  1165. reg = <0 0xe6c00000 0 0x0064>;
  1166. interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
  1167. clocks = <&cpg CPG_MOD 209>;
  1168. dmas = <&dmac0 0x45>, <&dmac0 0x44>;
  1169. dma-names = "tx", "rx";
  1170. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1171. resets = <&cpg 209>;
  1172. #address-cells = <1>;
  1173. #size-cells = <0>;
  1174. status = "disabled";
  1175. };
  1176. msiof3: spi@e6c10000 {
  1177. compatible = "renesas,msiof-r8a774b1",
  1178. "renesas,rcar-gen3-msiof";
  1179. reg = <0 0xe6c10000 0 0x0064>;
  1180. interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  1181. clocks = <&cpg CPG_MOD 208>;
  1182. dmas = <&dmac0 0x47>, <&dmac0 0x46>;
  1183. dma-names = "tx", "rx";
  1184. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1185. resets = <&cpg 208>;
  1186. #address-cells = <1>;
  1187. #size-cells = <0>;
  1188. status = "disabled";
  1189. };
  1190. vin0: video@e6ef0000 {
  1191. compatible = "renesas,vin-r8a774b1";
  1192. reg = <0 0xe6ef0000 0 0x1000>;
  1193. interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
  1194. clocks = <&cpg CPG_MOD 811>;
  1195. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1196. resets = <&cpg 811>;
  1197. renesas,id = <0>;
  1198. status = "disabled";
  1199. ports {
  1200. #address-cells = <1>;
  1201. #size-cells = <0>;
  1202. port@1 {
  1203. #address-cells = <1>;
  1204. #size-cells = <0>;
  1205. reg = <1>;
  1206. vin0csi20: endpoint@0 {
  1207. reg = <0>;
  1208. remote-endpoint = <&csi20vin0>;
  1209. };
  1210. vin0csi40: endpoint@2 {
  1211. reg = <2>;
  1212. remote-endpoint = <&csi40vin0>;
  1213. };
  1214. };
  1215. };
  1216. };
  1217. vin1: video@e6ef1000 {
  1218. compatible = "renesas,vin-r8a774b1";
  1219. reg = <0 0xe6ef1000 0 0x1000>;
  1220. interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
  1221. clocks = <&cpg CPG_MOD 810>;
  1222. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1223. resets = <&cpg 810>;
  1224. renesas,id = <1>;
  1225. status = "disabled";
  1226. ports {
  1227. #address-cells = <1>;
  1228. #size-cells = <0>;
  1229. port@1 {
  1230. #address-cells = <1>;
  1231. #size-cells = <0>;
  1232. reg = <1>;
  1233. vin1csi20: endpoint@0 {
  1234. reg = <0>;
  1235. remote-endpoint = <&csi20vin1>;
  1236. };
  1237. vin1csi40: endpoint@2 {
  1238. reg = <2>;
  1239. remote-endpoint = <&csi40vin1>;
  1240. };
  1241. };
  1242. };
  1243. };
  1244. vin2: video@e6ef2000 {
  1245. compatible = "renesas,vin-r8a774b1";
  1246. reg = <0 0xe6ef2000 0 0x1000>;
  1247. interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
  1248. clocks = <&cpg CPG_MOD 809>;
  1249. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1250. resets = <&cpg 809>;
  1251. renesas,id = <2>;
  1252. status = "disabled";
  1253. ports {
  1254. #address-cells = <1>;
  1255. #size-cells = <0>;
  1256. port@1 {
  1257. #address-cells = <1>;
  1258. #size-cells = <0>;
  1259. reg = <1>;
  1260. vin2csi20: endpoint@0 {
  1261. reg = <0>;
  1262. remote-endpoint = <&csi20vin2>;
  1263. };
  1264. vin2csi40: endpoint@2 {
  1265. reg = <2>;
  1266. remote-endpoint = <&csi40vin2>;
  1267. };
  1268. };
  1269. };
  1270. };
  1271. vin3: video@e6ef3000 {
  1272. compatible = "renesas,vin-r8a774b1";
  1273. reg = <0 0xe6ef3000 0 0x1000>;
  1274. interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
  1275. clocks = <&cpg CPG_MOD 808>;
  1276. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1277. resets = <&cpg 808>;
  1278. renesas,id = <3>;
  1279. status = "disabled";
  1280. ports {
  1281. #address-cells = <1>;
  1282. #size-cells = <0>;
  1283. port@1 {
  1284. #address-cells = <1>;
  1285. #size-cells = <0>;
  1286. reg = <1>;
  1287. vin3csi20: endpoint@0 {
  1288. reg = <0>;
  1289. remote-endpoint = <&csi20vin3>;
  1290. };
  1291. vin3csi40: endpoint@2 {
  1292. reg = <2>;
  1293. remote-endpoint = <&csi40vin3>;
  1294. };
  1295. };
  1296. };
  1297. };
  1298. vin4: video@e6ef4000 {
  1299. compatible = "renesas,vin-r8a774b1";
  1300. reg = <0 0xe6ef4000 0 0x1000>;
  1301. interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
  1302. clocks = <&cpg CPG_MOD 807>;
  1303. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1304. resets = <&cpg 807>;
  1305. renesas,id = <4>;
  1306. status = "disabled";
  1307. ports {
  1308. #address-cells = <1>;
  1309. #size-cells = <0>;
  1310. port@1 {
  1311. #address-cells = <1>;
  1312. #size-cells = <0>;
  1313. reg = <1>;
  1314. vin4csi20: endpoint@0 {
  1315. reg = <0>;
  1316. remote-endpoint = <&csi20vin4>;
  1317. };
  1318. vin4csi40: endpoint@2 {
  1319. reg = <2>;
  1320. remote-endpoint = <&csi40vin4>;
  1321. };
  1322. };
  1323. };
  1324. };
  1325. vin5: video@e6ef5000 {
  1326. compatible = "renesas,vin-r8a774b1";
  1327. reg = <0 0xe6ef5000 0 0x1000>;
  1328. interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
  1329. clocks = <&cpg CPG_MOD 806>;
  1330. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1331. resets = <&cpg 806>;
  1332. renesas,id = <5>;
  1333. status = "disabled";
  1334. ports {
  1335. #address-cells = <1>;
  1336. #size-cells = <0>;
  1337. port@1 {
  1338. #address-cells = <1>;
  1339. #size-cells = <0>;
  1340. reg = <1>;
  1341. vin5csi20: endpoint@0 {
  1342. reg = <0>;
  1343. remote-endpoint = <&csi20vin5>;
  1344. };
  1345. vin5csi40: endpoint@2 {
  1346. reg = <2>;
  1347. remote-endpoint = <&csi40vin5>;
  1348. };
  1349. };
  1350. };
  1351. };
  1352. vin6: video@e6ef6000 {
  1353. compatible = "renesas,vin-r8a774b1";
  1354. reg = <0 0xe6ef6000 0 0x1000>;
  1355. interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
  1356. clocks = <&cpg CPG_MOD 805>;
  1357. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1358. resets = <&cpg 805>;
  1359. renesas,id = <6>;
  1360. status = "disabled";
  1361. ports {
  1362. #address-cells = <1>;
  1363. #size-cells = <0>;
  1364. port@1 {
  1365. #address-cells = <1>;
  1366. #size-cells = <0>;
  1367. reg = <1>;
  1368. vin6csi20: endpoint@0 {
  1369. reg = <0>;
  1370. remote-endpoint = <&csi20vin6>;
  1371. };
  1372. vin6csi40: endpoint@2 {
  1373. reg = <2>;
  1374. remote-endpoint = <&csi40vin6>;
  1375. };
  1376. };
  1377. };
  1378. };
  1379. vin7: video@e6ef7000 {
  1380. compatible = "renesas,vin-r8a774b1";
  1381. reg = <0 0xe6ef7000 0 0x1000>;
  1382. interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
  1383. clocks = <&cpg CPG_MOD 804>;
  1384. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1385. resets = <&cpg 804>;
  1386. renesas,id = <7>;
  1387. status = "disabled";
  1388. ports {
  1389. #address-cells = <1>;
  1390. #size-cells = <0>;
  1391. port@1 {
  1392. #address-cells = <1>;
  1393. #size-cells = <0>;
  1394. reg = <1>;
  1395. vin7csi20: endpoint@0 {
  1396. reg = <0>;
  1397. remote-endpoint = <&csi20vin7>;
  1398. };
  1399. vin7csi40: endpoint@2 {
  1400. reg = <2>;
  1401. remote-endpoint = <&csi40vin7>;
  1402. };
  1403. };
  1404. };
  1405. };
  1406. rcar_sound: sound@ec500000 {
  1407. /*
  1408. * #sound-dai-cells is required
  1409. *
  1410. * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
  1411. * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
  1412. */
  1413. /*
  1414. * #clock-cells is required for audio_clkout0/1/2/3
  1415. *
  1416. * clkout : #clock-cells = <0>; <&rcar_sound>;
  1417. * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
  1418. */
  1419. compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3";
  1420. reg = <0 0xec500000 0 0x1000>, /* SCU */
  1421. <0 0xec5a0000 0 0x100>, /* ADG */
  1422. <0 0xec540000 0 0x1000>, /* SSIU */
  1423. <0 0xec541000 0 0x280>, /* SSI */
  1424. <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
  1425. reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
  1426. clocks = <&cpg CPG_MOD 1005>,
  1427. <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
  1428. <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
  1429. <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
  1430. <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
  1431. <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
  1432. <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
  1433. <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
  1434. <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
  1435. <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
  1436. <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
  1437. <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
  1438. <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
  1439. <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
  1440. <&audio_clk_a>, <&audio_clk_b>,
  1441. <&audio_clk_c>,
  1442. <&cpg CPG_CORE R8A774B1_CLK_S0D4>;
  1443. clock-names = "ssi-all",
  1444. "ssi.9", "ssi.8", "ssi.7", "ssi.6",
  1445. "ssi.5", "ssi.4", "ssi.3", "ssi.2",
  1446. "ssi.1", "ssi.0",
  1447. "src.9", "src.8", "src.7", "src.6",
  1448. "src.5", "src.4", "src.3", "src.2",
  1449. "src.1", "src.0",
  1450. "mix.1", "mix.0",
  1451. "ctu.1", "ctu.0",
  1452. "dvc.0", "dvc.1",
  1453. "clk_a", "clk_b", "clk_c", "clk_i";
  1454. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1455. resets = <&cpg 1005>,
  1456. <&cpg 1006>, <&cpg 1007>,
  1457. <&cpg 1008>, <&cpg 1009>,
  1458. <&cpg 1010>, <&cpg 1011>,
  1459. <&cpg 1012>, <&cpg 1013>,
  1460. <&cpg 1014>, <&cpg 1015>;
  1461. reset-names = "ssi-all",
  1462. "ssi.9", "ssi.8", "ssi.7", "ssi.6",
  1463. "ssi.5", "ssi.4", "ssi.3", "ssi.2",
  1464. "ssi.1", "ssi.0";
  1465. status = "disabled";
  1466. rcar_sound,ctu {
  1467. ctu00: ctu-0 { };
  1468. ctu01: ctu-1 { };
  1469. ctu02: ctu-2 { };
  1470. ctu03: ctu-3 { };
  1471. ctu10: ctu-4 { };
  1472. ctu11: ctu-5 { };
  1473. ctu12: ctu-6 { };
  1474. ctu13: ctu-7 { };
  1475. };
  1476. rcar_sound,dvc {
  1477. dvc0: dvc-0 {
  1478. dmas = <&audma1 0xbc>;
  1479. dma-names = "tx";
  1480. };
  1481. dvc1: dvc-1 {
  1482. dmas = <&audma1 0xbe>;
  1483. dma-names = "tx";
  1484. };
  1485. };
  1486. rcar_sound,mix {
  1487. mix0: mix-0 { };
  1488. mix1: mix-1 { };
  1489. };
  1490. rcar_sound,src {
  1491. src0: src-0 {
  1492. interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
  1493. dmas = <&audma0 0x85>, <&audma1 0x9a>;
  1494. dma-names = "rx", "tx";
  1495. };
  1496. src1: src-1 {
  1497. interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
  1498. dmas = <&audma0 0x87>, <&audma1 0x9c>;
  1499. dma-names = "rx", "tx";
  1500. };
  1501. src2: src-2 {
  1502. interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
  1503. dmas = <&audma0 0x89>, <&audma1 0x9e>;
  1504. dma-names = "rx", "tx";
  1505. };
  1506. src3: src-3 {
  1507. interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
  1508. dmas = <&audma0 0x8b>, <&audma1 0xa0>;
  1509. dma-names = "rx", "tx";
  1510. };
  1511. src4: src-4 {
  1512. interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
  1513. dmas = <&audma0 0x8d>, <&audma1 0xb0>;
  1514. dma-names = "rx", "tx";
  1515. };
  1516. src5: src-5 {
  1517. interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
  1518. dmas = <&audma0 0x8f>, <&audma1 0xb2>;
  1519. dma-names = "rx", "tx";
  1520. };
  1521. src6: src-6 {
  1522. interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
  1523. dmas = <&audma0 0x91>, <&audma1 0xb4>;
  1524. dma-names = "rx", "tx";
  1525. };
  1526. src7: src-7 {
  1527. interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
  1528. dmas = <&audma0 0x93>, <&audma1 0xb6>;
  1529. dma-names = "rx", "tx";
  1530. };
  1531. src8: src-8 {
  1532. interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
  1533. dmas = <&audma0 0x95>, <&audma1 0xb8>;
  1534. dma-names = "rx", "tx";
  1535. };
  1536. src9: src-9 {
  1537. interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
  1538. dmas = <&audma0 0x97>, <&audma1 0xba>;
  1539. dma-names = "rx", "tx";
  1540. };
  1541. };
  1542. rcar_sound,ssi {
  1543. ssi0: ssi-0 {
  1544. interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
  1545. dmas = <&audma0 0x01>, <&audma1 0x02>;
  1546. dma-names = "rx", "tx";
  1547. };
  1548. ssi1: ssi-1 {
  1549. interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
  1550. dmas = <&audma0 0x03>, <&audma1 0x04>;
  1551. dma-names = "rx", "tx";
  1552. };
  1553. ssi2: ssi-2 {
  1554. interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
  1555. dmas = <&audma0 0x05>, <&audma1 0x06>;
  1556. dma-names = "rx", "tx";
  1557. };
  1558. ssi3: ssi-3 {
  1559. interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
  1560. dmas = <&audma0 0x07>, <&audma1 0x08>;
  1561. dma-names = "rx", "tx";
  1562. };
  1563. ssi4: ssi-4 {
  1564. interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
  1565. dmas = <&audma0 0x09>, <&audma1 0x0a>;
  1566. dma-names = "rx", "tx";
  1567. };
  1568. ssi5: ssi-5 {
  1569. interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
  1570. dmas = <&audma0 0x0b>, <&audma1 0x0c>;
  1571. dma-names = "rx", "tx";
  1572. };
  1573. ssi6: ssi-6 {
  1574. interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
  1575. dmas = <&audma0 0x0d>, <&audma1 0x0e>;
  1576. dma-names = "rx", "tx";
  1577. };
  1578. ssi7: ssi-7 {
  1579. interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
  1580. dmas = <&audma0 0x0f>, <&audma1 0x10>;
  1581. dma-names = "rx", "tx";
  1582. };
  1583. ssi8: ssi-8 {
  1584. interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
  1585. dmas = <&audma0 0x11>, <&audma1 0x12>;
  1586. dma-names = "rx", "tx";
  1587. };
  1588. ssi9: ssi-9 {
  1589. interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
  1590. dmas = <&audma0 0x13>, <&audma1 0x14>;
  1591. dma-names = "rx", "tx";
  1592. };
  1593. };
  1594. rcar_sound,ssiu {
  1595. ssiu00: ssiu-0 {
  1596. dmas = <&audma0 0x15>, <&audma1 0x16>;
  1597. dma-names = "rx", "tx";
  1598. };
  1599. ssiu01: ssiu-1 {
  1600. dmas = <&audma0 0x35>, <&audma1 0x36>;
  1601. dma-names = "rx", "tx";
  1602. };
  1603. ssiu02: ssiu-2 {
  1604. dmas = <&audma0 0x37>, <&audma1 0x38>;
  1605. dma-names = "rx", "tx";
  1606. };
  1607. ssiu03: ssiu-3 {
  1608. dmas = <&audma0 0x47>, <&audma1 0x48>;
  1609. dma-names = "rx", "tx";
  1610. };
  1611. ssiu04: ssiu-4 {
  1612. dmas = <&audma0 0x3F>, <&audma1 0x40>;
  1613. dma-names = "rx", "tx";
  1614. };
  1615. ssiu05: ssiu-5 {
  1616. dmas = <&audma0 0x43>, <&audma1 0x44>;
  1617. dma-names = "rx", "tx";
  1618. };
  1619. ssiu06: ssiu-6 {
  1620. dmas = <&audma0 0x4F>, <&audma1 0x50>;
  1621. dma-names = "rx", "tx";
  1622. };
  1623. ssiu07: ssiu-7 {
  1624. dmas = <&audma0 0x53>, <&audma1 0x54>;
  1625. dma-names = "rx", "tx";
  1626. };
  1627. ssiu10: ssiu-8 {
  1628. dmas = <&audma0 0x49>, <&audma1 0x4a>;
  1629. dma-names = "rx", "tx";
  1630. };
  1631. ssiu11: ssiu-9 {
  1632. dmas = <&audma0 0x4B>, <&audma1 0x4C>;
  1633. dma-names = "rx", "tx";
  1634. };
  1635. ssiu12: ssiu-10 {
  1636. dmas = <&audma0 0x57>, <&audma1 0x58>;
  1637. dma-names = "rx", "tx";
  1638. };
  1639. ssiu13: ssiu-11 {
  1640. dmas = <&audma0 0x59>, <&audma1 0x5A>;
  1641. dma-names = "rx", "tx";
  1642. };
  1643. ssiu14: ssiu-12 {
  1644. dmas = <&audma0 0x5F>, <&audma1 0x60>;
  1645. dma-names = "rx", "tx";
  1646. };
  1647. ssiu15: ssiu-13 {
  1648. dmas = <&audma0 0xC3>, <&audma1 0xC4>;
  1649. dma-names = "rx", "tx";
  1650. };
  1651. ssiu16: ssiu-14 {
  1652. dmas = <&audma0 0xC7>, <&audma1 0xC8>;
  1653. dma-names = "rx", "tx";
  1654. };
  1655. ssiu17: ssiu-15 {
  1656. dmas = <&audma0 0xCB>, <&audma1 0xCC>;
  1657. dma-names = "rx", "tx";
  1658. };
  1659. ssiu20: ssiu-16 {
  1660. dmas = <&audma0 0x63>, <&audma1 0x64>;
  1661. dma-names = "rx", "tx";
  1662. };
  1663. ssiu21: ssiu-17 {
  1664. dmas = <&audma0 0x67>, <&audma1 0x68>;
  1665. dma-names = "rx", "tx";
  1666. };
  1667. ssiu22: ssiu-18 {
  1668. dmas = <&audma0 0x6B>, <&audma1 0x6C>;
  1669. dma-names = "rx", "tx";
  1670. };
  1671. ssiu23: ssiu-19 {
  1672. dmas = <&audma0 0x6D>, <&audma1 0x6E>;
  1673. dma-names = "rx", "tx";
  1674. };
  1675. ssiu24: ssiu-20 {
  1676. dmas = <&audma0 0xCF>, <&audma1 0xCE>;
  1677. dma-names = "rx", "tx";
  1678. };
  1679. ssiu25: ssiu-21 {
  1680. dmas = <&audma0 0xEB>, <&audma1 0xEC>;
  1681. dma-names = "rx", "tx";
  1682. };
  1683. ssiu26: ssiu-22 {
  1684. dmas = <&audma0 0xED>, <&audma1 0xEE>;
  1685. dma-names = "rx", "tx";
  1686. };
  1687. ssiu27: ssiu-23 {
  1688. dmas = <&audma0 0xEF>, <&audma1 0xF0>;
  1689. dma-names = "rx", "tx";
  1690. };
  1691. ssiu30: ssiu-24 {
  1692. dmas = <&audma0 0x6f>, <&audma1 0x70>;
  1693. dma-names = "rx", "tx";
  1694. };
  1695. ssiu31: ssiu-25 {
  1696. dmas = <&audma0 0x21>, <&audma1 0x22>;
  1697. dma-names = "rx", "tx";
  1698. };
  1699. ssiu32: ssiu-26 {
  1700. dmas = <&audma0 0x23>, <&audma1 0x24>;
  1701. dma-names = "rx", "tx";
  1702. };
  1703. ssiu33: ssiu-27 {
  1704. dmas = <&audma0 0x25>, <&audma1 0x26>;
  1705. dma-names = "rx", "tx";
  1706. };
  1707. ssiu34: ssiu-28 {
  1708. dmas = <&audma0 0x27>, <&audma1 0x28>;
  1709. dma-names = "rx", "tx";
  1710. };
  1711. ssiu35: ssiu-29 {
  1712. dmas = <&audma0 0x29>, <&audma1 0x2A>;
  1713. dma-names = "rx", "tx";
  1714. };
  1715. ssiu36: ssiu-30 {
  1716. dmas = <&audma0 0x2B>, <&audma1 0x2C>;
  1717. dma-names = "rx", "tx";
  1718. };
  1719. ssiu37: ssiu-31 {
  1720. dmas = <&audma0 0x2D>, <&audma1 0x2E>;
  1721. dma-names = "rx", "tx";
  1722. };
  1723. ssiu40: ssiu-32 {
  1724. dmas = <&audma0 0x71>, <&audma1 0x72>;
  1725. dma-names = "rx", "tx";
  1726. };
  1727. ssiu41: ssiu-33 {
  1728. dmas = <&audma0 0x17>, <&audma1 0x18>;
  1729. dma-names = "rx", "tx";
  1730. };
  1731. ssiu42: ssiu-34 {
  1732. dmas = <&audma0 0x19>, <&audma1 0x1A>;
  1733. dma-names = "rx", "tx";
  1734. };
  1735. ssiu43: ssiu-35 {
  1736. dmas = <&audma0 0x1B>, <&audma1 0x1C>;
  1737. dma-names = "rx", "tx";
  1738. };
  1739. ssiu44: ssiu-36 {
  1740. dmas = <&audma0 0x1D>, <&audma1 0x1E>;
  1741. dma-names = "rx", "tx";
  1742. };
  1743. ssiu45: ssiu-37 {
  1744. dmas = <&audma0 0x1F>, <&audma1 0x20>;
  1745. dma-names = "rx", "tx";
  1746. };
  1747. ssiu46: ssiu-38 {
  1748. dmas = <&audma0 0x31>, <&audma1 0x32>;
  1749. dma-names = "rx", "tx";
  1750. };
  1751. ssiu47: ssiu-39 {
  1752. dmas = <&audma0 0x33>, <&audma1 0x34>;
  1753. dma-names = "rx", "tx";
  1754. };
  1755. ssiu50: ssiu-40 {
  1756. dmas = <&audma0 0x73>, <&audma1 0x74>;
  1757. dma-names = "rx", "tx";
  1758. };
  1759. ssiu60: ssiu-41 {
  1760. dmas = <&audma0 0x75>, <&audma1 0x76>;
  1761. dma-names = "rx", "tx";
  1762. };
  1763. ssiu70: ssiu-42 {
  1764. dmas = <&audma0 0x79>, <&audma1 0x7a>;
  1765. dma-names = "rx", "tx";
  1766. };
  1767. ssiu80: ssiu-43 {
  1768. dmas = <&audma0 0x7b>, <&audma1 0x7c>;
  1769. dma-names = "rx", "tx";
  1770. };
  1771. ssiu90: ssiu-44 {
  1772. dmas = <&audma0 0x7d>, <&audma1 0x7e>;
  1773. dma-names = "rx", "tx";
  1774. };
  1775. ssiu91: ssiu-45 {
  1776. dmas = <&audma0 0x7F>, <&audma1 0x80>;
  1777. dma-names = "rx", "tx";
  1778. };
  1779. ssiu92: ssiu-46 {
  1780. dmas = <&audma0 0x81>, <&audma1 0x82>;
  1781. dma-names = "rx", "tx";
  1782. };
  1783. ssiu93: ssiu-47 {
  1784. dmas = <&audma0 0x83>, <&audma1 0x84>;
  1785. dma-names = "rx", "tx";
  1786. };
  1787. ssiu94: ssiu-48 {
  1788. dmas = <&audma0 0xA3>, <&audma1 0xA4>;
  1789. dma-names = "rx", "tx";
  1790. };
  1791. ssiu95: ssiu-49 {
  1792. dmas = <&audma0 0xA5>, <&audma1 0xA6>;
  1793. dma-names = "rx", "tx";
  1794. };
  1795. ssiu96: ssiu-50 {
  1796. dmas = <&audma0 0xA7>, <&audma1 0xA8>;
  1797. dma-names = "rx", "tx";
  1798. };
  1799. ssiu97: ssiu-51 {
  1800. dmas = <&audma0 0xA9>, <&audma1 0xAA>;
  1801. dma-names = "rx", "tx";
  1802. };
  1803. };
  1804. };
  1805. audma0: dma-controller@ec700000 {
  1806. compatible = "renesas,dmac-r8a774b1",
  1807. "renesas,rcar-dmac";
  1808. reg = <0 0xec700000 0 0x10000>;
  1809. interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
  1810. <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  1811. <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
  1812. <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
  1813. <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
  1814. <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
  1815. <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
  1816. <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
  1817. <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
  1818. <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
  1819. <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
  1820. <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
  1821. <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
  1822. <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
  1823. <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
  1824. <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
  1825. <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
  1826. interrupt-names = "error",
  1827. "ch0", "ch1", "ch2", "ch3",
  1828. "ch4", "ch5", "ch6", "ch7",
  1829. "ch8", "ch9", "ch10", "ch11",
  1830. "ch12", "ch13", "ch14", "ch15";
  1831. clocks = <&cpg CPG_MOD 502>;
  1832. clock-names = "fck";
  1833. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1834. resets = <&cpg 502>;
  1835. #dma-cells = <1>;
  1836. dma-channels = <16>;
  1837. };
  1838. audma1: dma-controller@ec720000 {
  1839. compatible = "renesas,dmac-r8a774b1",
  1840. "renesas,rcar-dmac";
  1841. reg = <0 0xec720000 0 0x10000>;
  1842. interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
  1843. <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
  1844. <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
  1845. <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
  1846. <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
  1847. <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
  1848. <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
  1849. <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
  1850. <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
  1851. <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
  1852. <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  1853. <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
  1854. <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
  1855. <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
  1856. <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
  1857. <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
  1858. <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
  1859. interrupt-names = "error",
  1860. "ch0", "ch1", "ch2", "ch3",
  1861. "ch4", "ch5", "ch6", "ch7",
  1862. "ch8", "ch9", "ch10", "ch11",
  1863. "ch12", "ch13", "ch14", "ch15";
  1864. clocks = <&cpg CPG_MOD 501>;
  1865. clock-names = "fck";
  1866. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1867. resets = <&cpg 501>;
  1868. #dma-cells = <1>;
  1869. dma-channels = <16>;
  1870. };
  1871. xhci0: usb@ee000000 {
  1872. compatible = "renesas,xhci-r8a774b1",
  1873. "renesas,rcar-gen3-xhci";
  1874. reg = <0 0xee000000 0 0xc00>;
  1875. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  1876. clocks = <&cpg CPG_MOD 328>;
  1877. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1878. resets = <&cpg 328>;
  1879. status = "disabled";
  1880. };
  1881. usb3_peri0: usb@ee020000 {
  1882. compatible = "renesas,r8a774b1-usb3-peri",
  1883. "renesas,rcar-gen3-usb3-peri";
  1884. reg = <0 0xee020000 0 0x400>;
  1885. interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
  1886. clocks = <&cpg CPG_MOD 328>;
  1887. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1888. resets = <&cpg 328>;
  1889. status = "disabled";
  1890. };
  1891. ohci0: usb@ee080000 {
  1892. compatible = "generic-ohci";
  1893. reg = <0 0xee080000 0 0x100>;
  1894. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  1895. clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
  1896. phys = <&usb2_phy0 1>;
  1897. phy-names = "usb";
  1898. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1899. resets = <&cpg 703>, <&cpg 704>;
  1900. status = "disabled";
  1901. };
  1902. ohci1: usb@ee0a0000 {
  1903. compatible = "generic-ohci";
  1904. reg = <0 0xee0a0000 0 0x100>;
  1905. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  1906. clocks = <&cpg CPG_MOD 702>;
  1907. phys = <&usb2_phy1 1>;
  1908. phy-names = "usb";
  1909. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1910. resets = <&cpg 702>;
  1911. status = "disabled";
  1912. };
  1913. ehci0: usb@ee080100 {
  1914. compatible = "generic-ehci";
  1915. reg = <0 0xee080100 0 0x100>;
  1916. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  1917. clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
  1918. phys = <&usb2_phy0 2>;
  1919. phy-names = "usb";
  1920. companion = <&ohci0>;
  1921. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1922. resets = <&cpg 703>, <&cpg 704>;
  1923. status = "disabled";
  1924. };
  1925. ehci1: usb@ee0a0100 {
  1926. compatible = "generic-ehci";
  1927. reg = <0 0xee0a0100 0 0x100>;
  1928. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  1929. clocks = <&cpg CPG_MOD 702>;
  1930. phys = <&usb2_phy1 2>;
  1931. phy-names = "usb";
  1932. companion = <&ohci1>;
  1933. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1934. resets = <&cpg 702>;
  1935. status = "disabled";
  1936. };
  1937. usb2_phy0: usb-phy@ee080200 {
  1938. compatible = "renesas,usb2-phy-r8a774b1",
  1939. "renesas,rcar-gen3-usb2-phy";
  1940. reg = <0 0xee080200 0 0x700>;
  1941. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  1942. clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
  1943. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1944. resets = <&cpg 703>, <&cpg 704>;
  1945. #phy-cells = <1>;
  1946. status = "disabled";
  1947. };
  1948. usb2_phy1: usb-phy@ee0a0200 {
  1949. compatible = "renesas,usb2-phy-r8a774b1",
  1950. "renesas,rcar-gen3-usb2-phy";
  1951. reg = <0 0xee0a0200 0 0x700>;
  1952. clocks = <&cpg CPG_MOD 702>;
  1953. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1954. resets = <&cpg 702>;
  1955. #phy-cells = <1>;
  1956. status = "disabled";
  1957. };
  1958. sdhi0: mmc@ee100000 {
  1959. compatible = "renesas,sdhi-r8a774b1",
  1960. "renesas,rcar-gen3-sdhi";
  1961. reg = <0 0xee100000 0 0x2000>;
  1962. interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
  1963. clocks = <&cpg CPG_MOD 314>;
  1964. max-frequency = <200000000>;
  1965. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1966. resets = <&cpg 314>;
  1967. status = "disabled";
  1968. };
  1969. sdhi1: mmc@ee120000 {
  1970. compatible = "renesas,sdhi-r8a774b1",
  1971. "renesas,rcar-gen3-sdhi";
  1972. reg = <0 0xee120000 0 0x2000>;
  1973. interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
  1974. clocks = <&cpg CPG_MOD 313>;
  1975. max-frequency = <200000000>;
  1976. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1977. resets = <&cpg 313>;
  1978. status = "disabled";
  1979. };
  1980. sdhi2: mmc@ee140000 {
  1981. compatible = "renesas,sdhi-r8a774b1",
  1982. "renesas,rcar-gen3-sdhi";
  1983. reg = <0 0xee140000 0 0x2000>;
  1984. interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
  1985. clocks = <&cpg CPG_MOD 312>;
  1986. max-frequency = <200000000>;
  1987. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1988. resets = <&cpg 312>;
  1989. status = "disabled";
  1990. };
  1991. sdhi3: mmc@ee160000 {
  1992. compatible = "renesas,sdhi-r8a774b1",
  1993. "renesas,rcar-gen3-sdhi";
  1994. reg = <0 0xee160000 0 0x2000>;
  1995. interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
  1996. clocks = <&cpg CPG_MOD 311>;
  1997. max-frequency = <200000000>;
  1998. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  1999. resets = <&cpg 311>;
  2000. status = "disabled";
  2001. };
  2002. sata: sata@ee300000 {
  2003. compatible = "renesas,sata-r8a774b1",
  2004. "renesas,rcar-gen3-sata";
  2005. reg = <0 0xee300000 0 0x200000>;
  2006. interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  2007. clocks = <&cpg CPG_MOD 815>;
  2008. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2009. resets = <&cpg 815>;
  2010. status = "disabled";
  2011. };
  2012. gic: interrupt-controller@f1010000 {
  2013. compatible = "arm,gic-400";
  2014. #interrupt-cells = <3>;
  2015. #address-cells = <0>;
  2016. interrupt-controller;
  2017. reg = <0x0 0xf1010000 0 0x1000>,
  2018. <0x0 0xf1020000 0 0x20000>,
  2019. <0x0 0xf1040000 0 0x20000>,
  2020. <0x0 0xf1060000 0 0x20000>;
  2021. interrupts = <GIC_PPI 9
  2022. (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  2023. clocks = <&cpg CPG_MOD 408>;
  2024. clock-names = "clk";
  2025. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2026. resets = <&cpg 408>;
  2027. };
  2028. pciec0: pcie@fe000000 {
  2029. compatible = "renesas,pcie-r8a774b1",
  2030. "renesas,pcie-rcar-gen3";
  2031. reg = <0 0xfe000000 0 0x80000>;
  2032. #address-cells = <3>;
  2033. #size-cells = <2>;
  2034. bus-range = <0x00 0xff>;
  2035. device_type = "pci";
  2036. ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
  2037. <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
  2038. <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
  2039. <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
  2040. /* Map all possible DDR as inbound ranges */
  2041. dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
  2042. interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  2043. <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  2044. <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  2045. #interrupt-cells = <1>;
  2046. interrupt-map-mask = <0 0 0 0>;
  2047. interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
  2048. clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
  2049. clock-names = "pcie", "pcie_bus";
  2050. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2051. resets = <&cpg 319>;
  2052. status = "disabled";
  2053. };
  2054. pciec1: pcie@ee800000 {
  2055. compatible = "renesas,pcie-r8a774b1",
  2056. "renesas,pcie-rcar-gen3";
  2057. reg = <0 0xee800000 0 0x80000>;
  2058. #address-cells = <3>;
  2059. #size-cells = <2>;
  2060. bus-range = <0x00 0xff>;
  2061. device_type = "pci";
  2062. ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
  2063. <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
  2064. <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
  2065. <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
  2066. /* Map all possible DDR as inbound ranges */
  2067. dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
  2068. interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
  2069. <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
  2070. <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
  2071. #interrupt-cells = <1>;
  2072. interrupt-map-mask = <0 0 0 0>;
  2073. interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  2074. clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
  2075. clock-names = "pcie", "pcie_bus";
  2076. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2077. resets = <&cpg 318>;
  2078. status = "disabled";
  2079. };
  2080. fdp1@fe940000 {
  2081. compatible = "renesas,fdp1";
  2082. reg = <0 0xfe940000 0 0x2400>;
  2083. interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
  2084. clocks = <&cpg CPG_MOD 119>;
  2085. power-domains = <&sysc R8A774B1_PD_A3VP>;
  2086. resets = <&cpg 119>;
  2087. renesas,fcp = <&fcpf0>;
  2088. };
  2089. fcpf0: fcp@fe950000 {
  2090. compatible = "renesas,fcpf";
  2091. reg = <0 0xfe950000 0 0x200>;
  2092. clocks = <&cpg CPG_MOD 615>;
  2093. power-domains = <&sysc R8A774B1_PD_A3VP>;
  2094. resets = <&cpg 615>;
  2095. };
  2096. vspb: vsp@fe960000 {
  2097. compatible = "renesas,vsp2";
  2098. reg = <0 0xfe960000 0 0x8000>;
  2099. interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
  2100. clocks = <&cpg CPG_MOD 626>;
  2101. power-domains = <&sysc R8A774B1_PD_A3VP>;
  2102. resets = <&cpg 626>;
  2103. renesas,fcp = <&fcpvb0>;
  2104. };
  2105. vspi0: vsp@fe9a0000 {
  2106. compatible = "renesas,vsp2";
  2107. reg = <0 0xfe9a0000 0 0x8000>;
  2108. interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
  2109. clocks = <&cpg CPG_MOD 631>;
  2110. power-domains = <&sysc R8A774B1_PD_A3VP>;
  2111. resets = <&cpg 631>;
  2112. renesas,fcp = <&fcpvi0>;
  2113. };
  2114. vspd0: vsp@fea20000 {
  2115. compatible = "renesas,vsp2";
  2116. reg = <0 0xfea20000 0 0x5000>;
  2117. interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
  2118. clocks = <&cpg CPG_MOD 623>;
  2119. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2120. resets = <&cpg 623>;
  2121. renesas,fcp = <&fcpvd0>;
  2122. };
  2123. vspd1: vsp@fea28000 {
  2124. compatible = "renesas,vsp2";
  2125. reg = <0 0xfea28000 0 0x5000>;
  2126. interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
  2127. clocks = <&cpg CPG_MOD 622>;
  2128. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2129. resets = <&cpg 622>;
  2130. renesas,fcp = <&fcpvd1>;
  2131. };
  2132. fcpvb0: fcp@fe96f000 {
  2133. compatible = "renesas,fcpv";
  2134. reg = <0 0xfe96f000 0 0x200>;
  2135. clocks = <&cpg CPG_MOD 607>;
  2136. power-domains = <&sysc R8A774B1_PD_A3VP>;
  2137. resets = <&cpg 607>;
  2138. };
  2139. fcpvd0: fcp@fea27000 {
  2140. compatible = "renesas,fcpv";
  2141. reg = <0 0xfea27000 0 0x200>;
  2142. clocks = <&cpg CPG_MOD 603>;
  2143. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2144. resets = <&cpg 603>;
  2145. };
  2146. fcpvd1: fcp@fea2f000 {
  2147. compatible = "renesas,fcpv";
  2148. reg = <0 0xfea2f000 0 0x200>;
  2149. clocks = <&cpg CPG_MOD 602>;
  2150. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2151. resets = <&cpg 602>;
  2152. };
  2153. fcpvi0: fcp@fe9af000 {
  2154. compatible = "renesas,fcpv";
  2155. reg = <0 0xfe9af000 0 0x200>;
  2156. clocks = <&cpg CPG_MOD 611>;
  2157. power-domains = <&sysc R8A774B1_PD_A3VP>;
  2158. resets = <&cpg 611>;
  2159. };
  2160. csi20: csi2@fea80000 {
  2161. compatible = "renesas,r8a774b1-csi2";
  2162. reg = <0 0xfea80000 0 0x10000>;
  2163. interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  2164. clocks = <&cpg CPG_MOD 714>;
  2165. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2166. resets = <&cpg 714>;
  2167. status = "disabled";
  2168. ports {
  2169. #address-cells = <1>;
  2170. #size-cells = <0>;
  2171. port@1 {
  2172. #address-cells = <1>;
  2173. #size-cells = <0>;
  2174. reg = <1>;
  2175. csi20vin0: endpoint@0 {
  2176. reg = <0>;
  2177. remote-endpoint = <&vin0csi20>;
  2178. };
  2179. csi20vin1: endpoint@1 {
  2180. reg = <1>;
  2181. remote-endpoint = <&vin1csi20>;
  2182. };
  2183. csi20vin2: endpoint@2 {
  2184. reg = <2>;
  2185. remote-endpoint = <&vin2csi20>;
  2186. };
  2187. csi20vin3: endpoint@3 {
  2188. reg = <3>;
  2189. remote-endpoint = <&vin3csi20>;
  2190. };
  2191. csi20vin4: endpoint@4 {
  2192. reg = <4>;
  2193. remote-endpoint = <&vin4csi20>;
  2194. };
  2195. csi20vin5: endpoint@5 {
  2196. reg = <5>;
  2197. remote-endpoint = <&vin5csi20>;
  2198. };
  2199. csi20vin6: endpoint@6 {
  2200. reg = <6>;
  2201. remote-endpoint = <&vin6csi20>;
  2202. };
  2203. csi20vin7: endpoint@7 {
  2204. reg = <7>;
  2205. remote-endpoint = <&vin7csi20>;
  2206. };
  2207. };
  2208. };
  2209. };
  2210. csi40: csi2@feaa0000 {
  2211. compatible = "renesas,r8a774b1-csi2";
  2212. reg = <0 0xfeaa0000 0 0x10000>;
  2213. interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
  2214. clocks = <&cpg CPG_MOD 716>;
  2215. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2216. resets = <&cpg 716>;
  2217. status = "disabled";
  2218. ports {
  2219. #address-cells = <1>;
  2220. #size-cells = <0>;
  2221. port@1 {
  2222. #address-cells = <1>;
  2223. #size-cells = <0>;
  2224. reg = <1>;
  2225. csi40vin0: endpoint@0 {
  2226. reg = <0>;
  2227. remote-endpoint = <&vin0csi40>;
  2228. };
  2229. csi40vin1: endpoint@1 {
  2230. reg = <1>;
  2231. remote-endpoint = <&vin1csi40>;
  2232. };
  2233. csi40vin2: endpoint@2 {
  2234. reg = <2>;
  2235. remote-endpoint = <&vin2csi40>;
  2236. };
  2237. csi40vin3: endpoint@3 {
  2238. reg = <3>;
  2239. remote-endpoint = <&vin3csi40>;
  2240. };
  2241. csi40vin4: endpoint@4 {
  2242. reg = <4>;
  2243. remote-endpoint = <&vin4csi40>;
  2244. };
  2245. csi40vin5: endpoint@5 {
  2246. reg = <5>;
  2247. remote-endpoint = <&vin5csi40>;
  2248. };
  2249. csi40vin6: endpoint@6 {
  2250. reg = <6>;
  2251. remote-endpoint = <&vin6csi40>;
  2252. };
  2253. csi40vin7: endpoint@7 {
  2254. reg = <7>;
  2255. remote-endpoint = <&vin7csi40>;
  2256. };
  2257. };
  2258. };
  2259. };
  2260. hdmi0: hdmi@fead0000 {
  2261. compatible = "renesas,r8a774b1-hdmi",
  2262. "renesas,rcar-gen3-hdmi";
  2263. reg = <0 0xfead0000 0 0x10000>;
  2264. interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
  2265. clocks = <&cpg CPG_MOD 729>,
  2266. <&cpg CPG_CORE R8A774B1_CLK_HDMI>;
  2267. clock-names = "iahb", "isfr";
  2268. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2269. resets = <&cpg 729>;
  2270. status = "disabled";
  2271. ports {
  2272. #address-cells = <1>;
  2273. #size-cells = <0>;
  2274. port@0 {
  2275. reg = <0>;
  2276. dw_hdmi0_in: endpoint {
  2277. remote-endpoint = <&du_out_hdmi0>;
  2278. };
  2279. };
  2280. port@1 {
  2281. reg = <1>;
  2282. };
  2283. port@2 {
  2284. /* HDMI sound */
  2285. reg = <2>;
  2286. };
  2287. };
  2288. };
  2289. du: display@feb00000 {
  2290. compatible = "renesas,du-r8a774b1";
  2291. reg = <0 0xfeb00000 0 0x80000>;
  2292. interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
  2293. <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
  2294. <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
  2295. clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
  2296. <&cpg CPG_MOD 721>;
  2297. clock-names = "du.0", "du.1", "du.3";
  2298. resets = <&cpg 724>, <&cpg 722>;
  2299. reset-names = "du.0", "du.3";
  2300. status = "disabled";
  2301. renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
  2302. ports {
  2303. #address-cells = <1>;
  2304. #size-cells = <0>;
  2305. port@0 {
  2306. reg = <0>;
  2307. du_out_rgb: endpoint {
  2308. };
  2309. };
  2310. port@1 {
  2311. reg = <1>;
  2312. du_out_hdmi0: endpoint {
  2313. remote-endpoint = <&dw_hdmi0_in>;
  2314. };
  2315. };
  2316. port@2 {
  2317. reg = <2>;
  2318. du_out_lvds0: endpoint {
  2319. remote-endpoint = <&lvds0_in>;
  2320. };
  2321. };
  2322. };
  2323. };
  2324. lvds0: lvds@feb90000 {
  2325. compatible = "renesas,r8a774b1-lvds";
  2326. reg = <0 0xfeb90000 0 0x14>;
  2327. clocks = <&cpg CPG_MOD 727>;
  2328. power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
  2329. resets = <&cpg 727>;
  2330. status = "disabled";
  2331. ports {
  2332. #address-cells = <1>;
  2333. #size-cells = <0>;
  2334. port@0 {
  2335. reg = <0>;
  2336. lvds0_in: endpoint {
  2337. remote-endpoint = <&du_out_lvds0>;
  2338. };
  2339. };
  2340. port@1 {
  2341. reg = <1>;
  2342. lvds0_out: endpoint {
  2343. };
  2344. };
  2345. };
  2346. };
  2347. prr: chipid@fff00044 {
  2348. compatible = "renesas,prr";
  2349. reg = <0 0xfff00044 0 4>;
  2350. };
  2351. };
  2352. thermal-zones {
  2353. sensor_thermal1: sensor-thermal1 {
  2354. polling-delay-passive = <250>;
  2355. polling-delay = <1000>;
  2356. thermal-sensors = <&tsc 0>;
  2357. sustainable-power = <2439>;
  2358. trips {
  2359. sensor1_crit: sensor1-crit {
  2360. temperature = <120000>;
  2361. hysteresis = <1000>;
  2362. type = "critical";
  2363. };
  2364. };
  2365. };
  2366. sensor_thermal2: sensor-thermal2 {
  2367. polling-delay-passive = <250>;
  2368. polling-delay = <1000>;
  2369. thermal-sensors = <&tsc 1>;
  2370. sustainable-power = <2439>;
  2371. trips {
  2372. sensor2_crit: sensor2-crit {
  2373. temperature = <120000>;
  2374. hysteresis = <1000>;
  2375. type = "critical";
  2376. };
  2377. };
  2378. };
  2379. sensor_thermal3: sensor-thermal3 {
  2380. polling-delay-passive = <250>;
  2381. polling-delay = <1000>;
  2382. thermal-sensors = <&tsc 2>;
  2383. sustainable-power = <2439>;
  2384. cooling-maps {
  2385. map0 {
  2386. trip = <&target>;
  2387. cooling-device = <&a57_0 0 2>;
  2388. contribution = <1024>;
  2389. };
  2390. };
  2391. trips {
  2392. target: trip-point1 {
  2393. temperature = <100000>;
  2394. hysteresis = <1000>;
  2395. type = "passive";
  2396. };
  2397. sensor3_crit: sensor3-crit {
  2398. temperature = <120000>;
  2399. hysteresis = <1000>;
  2400. type = "critical";
  2401. };
  2402. };
  2403. };
  2404. };
  2405. timer {
  2406. compatible = "arm,armv8-timer";
  2407. interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  2408. <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  2409. <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  2410. <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  2411. };
  2412. /* External USB clocks - can be overridden by the board */
  2413. usb3s0_clk: usb3s0 {
  2414. compatible = "fixed-clock";
  2415. #clock-cells = <0>;
  2416. clock-frequency = <0>;
  2417. };
  2418. usb_extal_clk: usb_extal {
  2419. compatible = "fixed-clock";
  2420. #clock-cells = <0>;
  2421. clock-frequency = <0>;
  2422. };
  2423. };