r8a774a1.dtsi 76 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for the r8a774a1 SoC
  4. *
  5. * Copyright (C) 2018 Renesas Electronics Corp.
  6. */
  7. #include <dt-bindings/interrupt-controller/irq.h>
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
  10. #include <dt-bindings/power/r8a774a1-sysc.h>
  11. #define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4
  12. / {
  13. compatible = "renesas,r8a774a1";
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. aliases {
  17. i2c0 = &i2c0;
  18. i2c1 = &i2c1;
  19. i2c2 = &i2c2;
  20. i2c3 = &i2c3;
  21. i2c4 = &i2c4;
  22. i2c5 = &i2c5;
  23. i2c6 = &i2c6;
  24. i2c7 = &i2c_dvfs;
  25. };
  26. /*
  27. * The external audio clocks are configured as 0 Hz fixed frequency
  28. * clocks by default.
  29. * Boards that provide audio clocks should override them.
  30. */
  31. audio_clk_a: audio_clk_a {
  32. compatible = "fixed-clock";
  33. #clock-cells = <0>;
  34. clock-frequency = <0>;
  35. };
  36. audio_clk_b: audio_clk_b {
  37. compatible = "fixed-clock";
  38. #clock-cells = <0>;
  39. clock-frequency = <0>;
  40. };
  41. audio_clk_c: audio_clk_c {
  42. compatible = "fixed-clock";
  43. #clock-cells = <0>;
  44. clock-frequency = <0>;
  45. };
  46. /* External CAN clock - to be overridden by boards that provide it */
  47. can_clk: can {
  48. compatible = "fixed-clock";
  49. #clock-cells = <0>;
  50. clock-frequency = <0>;
  51. };
  52. cluster0_opp: opp_table0 {
  53. compatible = "operating-points-v2";
  54. opp-shared;
  55. opp-500000000 {
  56. opp-hz = /bits/ 64 <500000000>;
  57. opp-microvolt = <820000>;
  58. clock-latency-ns = <300000>;
  59. };
  60. opp-1000000000 {
  61. opp-hz = /bits/ 64 <1000000000>;
  62. opp-microvolt = <820000>;
  63. clock-latency-ns = <300000>;
  64. };
  65. opp-1500000000 {
  66. opp-hz = /bits/ 64 <1500000000>;
  67. opp-microvolt = <820000>;
  68. clock-latency-ns = <300000>;
  69. };
  70. };
  71. cluster1_opp: opp_table1 {
  72. compatible = "operating-points-v2";
  73. opp-shared;
  74. opp-800000000 {
  75. opp-hz = /bits/ 64 <800000000>;
  76. opp-microvolt = <820000>;
  77. clock-latency-ns = <300000>;
  78. };
  79. opp-1000000000 {
  80. opp-hz = /bits/ 64 <1000000000>;
  81. opp-microvolt = <820000>;
  82. clock-latency-ns = <300000>;
  83. };
  84. opp-1200000000 {
  85. opp-hz = /bits/ 64 <1200000000>;
  86. opp-microvolt = <820000>;
  87. clock-latency-ns = <300000>;
  88. };
  89. };
  90. cpus {
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. cpu-map {
  94. cluster0 {
  95. core0 {
  96. cpu = <&a57_0>;
  97. };
  98. core1 {
  99. cpu = <&a57_1>;
  100. };
  101. };
  102. cluster1 {
  103. core0 {
  104. cpu = <&a53_0>;
  105. };
  106. core1 {
  107. cpu = <&a53_1>;
  108. };
  109. core2 {
  110. cpu = <&a53_2>;
  111. };
  112. core3 {
  113. cpu = <&a53_3>;
  114. };
  115. };
  116. };
  117. a57_0: cpu@0 {
  118. compatible = "arm,cortex-a57";
  119. reg = <0x0>;
  120. device_type = "cpu";
  121. power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
  122. next-level-cache = <&L2_CA57>;
  123. enable-method = "psci";
  124. dynamic-power-coefficient = <854>;
  125. clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
  126. operating-points-v2 = <&cluster0_opp>;
  127. capacity-dmips-mhz = <1024>;
  128. #cooling-cells = <2>;
  129. };
  130. a57_1: cpu@1 {
  131. compatible = "arm,cortex-a57";
  132. reg = <0x1>;
  133. device_type = "cpu";
  134. power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
  135. next-level-cache = <&L2_CA57>;
  136. enable-method = "psci";
  137. clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
  138. operating-points-v2 = <&cluster0_opp>;
  139. capacity-dmips-mhz = <1024>;
  140. #cooling-cells = <2>;
  141. };
  142. a53_0: cpu@100 {
  143. compatible = "arm,cortex-a53";
  144. reg = <0x100>;
  145. device_type = "cpu";
  146. power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
  147. next-level-cache = <&L2_CA53>;
  148. enable-method = "psci";
  149. #cooling-cells = <2>;
  150. dynamic-power-coefficient = <277>;
  151. clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
  152. operating-points-v2 = <&cluster1_opp>;
  153. capacity-dmips-mhz = <560>;
  154. };
  155. a53_1: cpu@101 {
  156. compatible = "arm,cortex-a53";
  157. reg = <0x101>;
  158. device_type = "cpu";
  159. power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
  160. next-level-cache = <&L2_CA53>;
  161. enable-method = "psci";
  162. clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
  163. operating-points-v2 = <&cluster1_opp>;
  164. capacity-dmips-mhz = <560>;
  165. };
  166. a53_2: cpu@102 {
  167. compatible = "arm,cortex-a53";
  168. reg = <0x102>;
  169. device_type = "cpu";
  170. power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
  171. next-level-cache = <&L2_CA53>;
  172. enable-method = "psci";
  173. clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
  174. operating-points-v2 = <&cluster1_opp>;
  175. capacity-dmips-mhz = <560>;
  176. };
  177. a53_3: cpu@103 {
  178. compatible = "arm,cortex-a53";
  179. reg = <0x103>;
  180. device_type = "cpu";
  181. power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
  182. next-level-cache = <&L2_CA53>;
  183. enable-method = "psci";
  184. clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
  185. operating-points-v2 = <&cluster1_opp>;
  186. capacity-dmips-mhz = <560>;
  187. };
  188. L2_CA57: cache-controller-0 {
  189. compatible = "cache";
  190. power-domains = <&sysc R8A774A1_PD_CA57_SCU>;
  191. cache-unified;
  192. cache-level = <2>;
  193. };
  194. L2_CA53: cache-controller-1 {
  195. compatible = "cache";
  196. power-domains = <&sysc R8A774A1_PD_CA53_SCU>;
  197. cache-unified;
  198. cache-level = <2>;
  199. };
  200. };
  201. extal_clk: extal {
  202. compatible = "fixed-clock";
  203. #clock-cells = <0>;
  204. /* This value must be overridden by the board */
  205. clock-frequency = <0>;
  206. };
  207. extalr_clk: extalr {
  208. compatible = "fixed-clock";
  209. #clock-cells = <0>;
  210. /* This value must be overridden by the board */
  211. clock-frequency = <0>;
  212. };
  213. /* External PCIe clock - can be overridden by the board */
  214. pcie_bus_clk: pcie_bus {
  215. compatible = "fixed-clock";
  216. #clock-cells = <0>;
  217. clock-frequency = <0>;
  218. };
  219. pmu_a53 {
  220. compatible = "arm,cortex-a53-pmu";
  221. interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
  222. <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
  223. <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
  224. <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  225. interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
  226. };
  227. pmu_a57 {
  228. compatible = "arm,cortex-a57-pmu";
  229. interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  230. <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  231. interrupt-affinity = <&a57_0>, <&a57_1>;
  232. };
  233. psci {
  234. compatible = "arm,psci-1.0", "arm,psci-0.2";
  235. method = "smc";
  236. };
  237. /* External SCIF clock - to be overridden by boards that provide it */
  238. scif_clk: scif {
  239. compatible = "fixed-clock";
  240. #clock-cells = <0>;
  241. clock-frequency = <0>;
  242. };
  243. soc {
  244. compatible = "simple-bus";
  245. interrupt-parent = <&gic>;
  246. #address-cells = <2>;
  247. #size-cells = <2>;
  248. ranges;
  249. rwdt: watchdog@e6020000 {
  250. compatible = "renesas,r8a774a1-wdt",
  251. "renesas,rcar-gen3-wdt";
  252. reg = <0 0xe6020000 0 0x0c>;
  253. clocks = <&cpg CPG_MOD 402>;
  254. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  255. resets = <&cpg 402>;
  256. status = "disabled";
  257. };
  258. gpio0: gpio@e6050000 {
  259. compatible = "renesas,gpio-r8a774a1",
  260. "renesas,rcar-gen3-gpio";
  261. reg = <0 0xe6050000 0 0x50>;
  262. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  263. #gpio-cells = <2>;
  264. gpio-controller;
  265. gpio-ranges = <&pfc 0 0 16>;
  266. #interrupt-cells = <2>;
  267. interrupt-controller;
  268. clocks = <&cpg CPG_MOD 912>;
  269. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  270. resets = <&cpg 912>;
  271. };
  272. gpio1: gpio@e6051000 {
  273. compatible = "renesas,gpio-r8a774a1",
  274. "renesas,rcar-gen3-gpio";
  275. reg = <0 0xe6051000 0 0x50>;
  276. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  277. #gpio-cells = <2>;
  278. gpio-controller;
  279. gpio-ranges = <&pfc 0 32 29>;
  280. #interrupt-cells = <2>;
  281. interrupt-controller;
  282. clocks = <&cpg CPG_MOD 911>;
  283. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  284. resets = <&cpg 911>;
  285. };
  286. gpio2: gpio@e6052000 {
  287. compatible = "renesas,gpio-r8a774a1",
  288. "renesas,rcar-gen3-gpio";
  289. reg = <0 0xe6052000 0 0x50>;
  290. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  291. #gpio-cells = <2>;
  292. gpio-controller;
  293. gpio-ranges = <&pfc 0 64 15>;
  294. #interrupt-cells = <2>;
  295. interrupt-controller;
  296. clocks = <&cpg CPG_MOD 910>;
  297. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  298. resets = <&cpg 910>;
  299. };
  300. gpio3: gpio@e6053000 {
  301. compatible = "renesas,gpio-r8a774a1",
  302. "renesas,rcar-gen3-gpio";
  303. reg = <0 0xe6053000 0 0x50>;
  304. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  305. #gpio-cells = <2>;
  306. gpio-controller;
  307. gpio-ranges = <&pfc 0 96 16>;
  308. #interrupt-cells = <2>;
  309. interrupt-controller;
  310. clocks = <&cpg CPG_MOD 909>;
  311. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  312. resets = <&cpg 909>;
  313. };
  314. gpio4: gpio@e6054000 {
  315. compatible = "renesas,gpio-r8a774a1",
  316. "renesas,rcar-gen3-gpio";
  317. reg = <0 0xe6054000 0 0x50>;
  318. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  319. #gpio-cells = <2>;
  320. gpio-controller;
  321. gpio-ranges = <&pfc 0 128 18>;
  322. #interrupt-cells = <2>;
  323. interrupt-controller;
  324. clocks = <&cpg CPG_MOD 908>;
  325. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  326. resets = <&cpg 908>;
  327. };
  328. gpio5: gpio@e6055000 {
  329. compatible = "renesas,gpio-r8a774a1",
  330. "renesas,rcar-gen3-gpio";
  331. reg = <0 0xe6055000 0 0x50>;
  332. interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  333. #gpio-cells = <2>;
  334. gpio-controller;
  335. gpio-ranges = <&pfc 0 160 26>;
  336. #interrupt-cells = <2>;
  337. interrupt-controller;
  338. clocks = <&cpg CPG_MOD 907>;
  339. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  340. resets = <&cpg 907>;
  341. };
  342. gpio6: gpio@e6055400 {
  343. compatible = "renesas,gpio-r8a774a1",
  344. "renesas,rcar-gen3-gpio";
  345. reg = <0 0xe6055400 0 0x50>;
  346. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  347. #gpio-cells = <2>;
  348. gpio-controller;
  349. gpio-ranges = <&pfc 0 192 32>;
  350. #interrupt-cells = <2>;
  351. interrupt-controller;
  352. clocks = <&cpg CPG_MOD 906>;
  353. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  354. resets = <&cpg 906>;
  355. };
  356. gpio7: gpio@e6055800 {
  357. compatible = "renesas,gpio-r8a774a1",
  358. "renesas,rcar-gen3-gpio";
  359. reg = <0 0xe6055800 0 0x50>;
  360. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  361. #gpio-cells = <2>;
  362. gpio-controller;
  363. gpio-ranges = <&pfc 0 224 4>;
  364. #interrupt-cells = <2>;
  365. interrupt-controller;
  366. clocks = <&cpg CPG_MOD 905>;
  367. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  368. resets = <&cpg 905>;
  369. };
  370. pfc: pin-controller@e6060000 {
  371. compatible = "renesas,pfc-r8a774a1";
  372. reg = <0 0xe6060000 0 0x50c>;
  373. };
  374. cmt0: timer@e60f0000 {
  375. compatible = "renesas,r8a774a1-cmt0",
  376. "renesas,rcar-gen3-cmt0";
  377. reg = <0 0xe60f0000 0 0x1004>;
  378. interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  379. <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  380. clocks = <&cpg CPG_MOD 303>;
  381. clock-names = "fck";
  382. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  383. resets = <&cpg 303>;
  384. status = "disabled";
  385. };
  386. cmt1: timer@e6130000 {
  387. compatible = "renesas,r8a774a1-cmt1",
  388. "renesas,rcar-gen3-cmt1";
  389. reg = <0 0xe6130000 0 0x1004>;
  390. interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  391. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  392. <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  393. <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  394. <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  395. <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  396. <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  397. <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  398. clocks = <&cpg CPG_MOD 302>;
  399. clock-names = "fck";
  400. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  401. resets = <&cpg 302>;
  402. status = "disabled";
  403. };
  404. cmt2: timer@e6140000 {
  405. compatible = "renesas,r8a774a1-cmt1",
  406. "renesas,rcar-gen3-cmt1";
  407. reg = <0 0xe6140000 0 0x1004>;
  408. interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
  409. <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
  410. <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
  411. <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
  412. <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
  413. <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
  414. <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
  415. <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
  416. clocks = <&cpg CPG_MOD 301>;
  417. clock-names = "fck";
  418. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  419. resets = <&cpg 301>;
  420. status = "disabled";
  421. };
  422. cmt3: timer@e6148000 {
  423. compatible = "renesas,r8a774a1-cmt1",
  424. "renesas,rcar-gen3-cmt1";
  425. reg = <0 0xe6148000 0 0x1004>;
  426. interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
  427. <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
  428. <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
  429. <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
  430. <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
  431. <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
  432. <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
  433. <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
  434. clocks = <&cpg CPG_MOD 300>;
  435. clock-names = "fck";
  436. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  437. resets = <&cpg 300>;
  438. status = "disabled";
  439. };
  440. cpg: clock-controller@e6150000 {
  441. compatible = "renesas,r8a774a1-cpg-mssr";
  442. reg = <0 0xe6150000 0 0x0bb0>;
  443. clocks = <&extal_clk>, <&extalr_clk>;
  444. clock-names = "extal", "extalr";
  445. #clock-cells = <2>;
  446. #power-domain-cells = <0>;
  447. #reset-cells = <1>;
  448. };
  449. rst: reset-controller@e6160000 {
  450. compatible = "renesas,r8a774a1-rst";
  451. reg = <0 0xe6160000 0 0x018c>;
  452. };
  453. sysc: system-controller@e6180000 {
  454. compatible = "renesas,r8a774a1-sysc";
  455. reg = <0 0xe6180000 0 0x0400>;
  456. #power-domain-cells = <1>;
  457. };
  458. tsc: thermal@e6198000 {
  459. compatible = "renesas,r8a774a1-thermal";
  460. reg = <0 0xe6198000 0 0x100>,
  461. <0 0xe61a0000 0 0x100>,
  462. <0 0xe61a8000 0 0x100>;
  463. interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
  464. <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  465. <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  466. clocks = <&cpg CPG_MOD 522>;
  467. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  468. resets = <&cpg 522>;
  469. #thermal-sensor-cells = <1>;
  470. };
  471. intc_ex: interrupt-controller@e61c0000 {
  472. compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
  473. #interrupt-cells = <2>;
  474. interrupt-controller;
  475. reg = <0 0xe61c0000 0 0x200>;
  476. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  477. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  478. <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  479. <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  480. <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  481. <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
  482. clocks = <&cpg CPG_MOD 407>;
  483. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  484. resets = <&cpg 407>;
  485. };
  486. tmu0: timer@e61e0000 {
  487. compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
  488. reg = <0 0xe61e0000 0 0x30>;
  489. interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  490. <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  491. <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  492. clocks = <&cpg CPG_MOD 125>;
  493. clock-names = "fck";
  494. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  495. resets = <&cpg 125>;
  496. status = "disabled";
  497. };
  498. tmu1: timer@e6fc0000 {
  499. compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
  500. reg = <0 0xe6fc0000 0 0x30>;
  501. interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  502. <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
  503. <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  504. clocks = <&cpg CPG_MOD 124>;
  505. clock-names = "fck";
  506. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  507. resets = <&cpg 124>;
  508. status = "disabled";
  509. };
  510. tmu2: timer@e6fd0000 {
  511. compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
  512. reg = <0 0xe6fd0000 0 0x30>;
  513. interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
  514. <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  515. <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
  516. clocks = <&cpg CPG_MOD 123>;
  517. clock-names = "fck";
  518. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  519. resets = <&cpg 123>;
  520. status = "disabled";
  521. };
  522. tmu3: timer@e6fe0000 {
  523. compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
  524. reg = <0 0xe6fe0000 0 0x30>;
  525. interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  526. <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
  527. <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  528. clocks = <&cpg CPG_MOD 122>;
  529. clock-names = "fck";
  530. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  531. resets = <&cpg 122>;
  532. status = "disabled";
  533. };
  534. tmu4: timer@ffc00000 {
  535. compatible = "renesas,tmu-r8a774a1", "renesas,tmu";
  536. reg = <0 0xffc00000 0 0x30>;
  537. interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
  538. <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
  539. <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
  540. clocks = <&cpg CPG_MOD 121>;
  541. clock-names = "fck";
  542. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  543. resets = <&cpg 121>;
  544. status = "disabled";
  545. };
  546. i2c0: i2c@e6500000 {
  547. #address-cells = <1>;
  548. #size-cells = <0>;
  549. compatible = "renesas,i2c-r8a774a1",
  550. "renesas,rcar-gen3-i2c";
  551. reg = <0 0xe6500000 0 0x40>;
  552. interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
  553. clocks = <&cpg CPG_MOD 931>;
  554. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  555. resets = <&cpg 931>;
  556. dmas = <&dmac1 0x91>, <&dmac1 0x90>,
  557. <&dmac2 0x91>, <&dmac2 0x90>;
  558. dma-names = "tx", "rx", "tx", "rx";
  559. i2c-scl-internal-delay-ns = <110>;
  560. status = "disabled";
  561. };
  562. i2c1: i2c@e6508000 {
  563. #address-cells = <1>;
  564. #size-cells = <0>;
  565. compatible = "renesas,i2c-r8a774a1",
  566. "renesas,rcar-gen3-i2c";
  567. reg = <0 0xe6508000 0 0x40>;
  568. interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
  569. clocks = <&cpg CPG_MOD 930>;
  570. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  571. resets = <&cpg 930>;
  572. dmas = <&dmac1 0x93>, <&dmac1 0x92>,
  573. <&dmac2 0x93>, <&dmac2 0x92>;
  574. dma-names = "tx", "rx", "tx", "rx";
  575. i2c-scl-internal-delay-ns = <6>;
  576. status = "disabled";
  577. };
  578. i2c2: i2c@e6510000 {
  579. #address-cells = <1>;
  580. #size-cells = <0>;
  581. compatible = "renesas,i2c-r8a774a1",
  582. "renesas,rcar-gen3-i2c";
  583. reg = <0 0xe6510000 0 0x40>;
  584. interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
  585. clocks = <&cpg CPG_MOD 929>;
  586. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  587. resets = <&cpg 929>;
  588. dmas = <&dmac1 0x95>, <&dmac1 0x94>,
  589. <&dmac2 0x95>, <&dmac2 0x94>;
  590. dma-names = "tx", "rx", "tx", "rx";
  591. i2c-scl-internal-delay-ns = <6>;
  592. status = "disabled";
  593. };
  594. i2c3: i2c@e66d0000 {
  595. #address-cells = <1>;
  596. #size-cells = <0>;
  597. compatible = "renesas,i2c-r8a774a1",
  598. "renesas,rcar-gen3-i2c";
  599. reg = <0 0xe66d0000 0 0x40>;
  600. interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
  601. clocks = <&cpg CPG_MOD 928>;
  602. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  603. resets = <&cpg 928>;
  604. dmas = <&dmac0 0x97>, <&dmac0 0x96>;
  605. dma-names = "tx", "rx";
  606. i2c-scl-internal-delay-ns = <110>;
  607. status = "disabled";
  608. };
  609. i2c4: i2c@e66d8000 {
  610. #address-cells = <1>;
  611. #size-cells = <0>;
  612. compatible = "renesas,i2c-r8a774a1",
  613. "renesas,rcar-gen3-i2c";
  614. reg = <0 0xe66d8000 0 0x40>;
  615. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  616. clocks = <&cpg CPG_MOD 927>;
  617. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  618. resets = <&cpg 927>;
  619. dmas = <&dmac0 0x99>, <&dmac0 0x98>;
  620. dma-names = "tx", "rx";
  621. i2c-scl-internal-delay-ns = <110>;
  622. status = "disabled";
  623. };
  624. i2c5: i2c@e66e0000 {
  625. #address-cells = <1>;
  626. #size-cells = <0>;
  627. compatible = "renesas,i2c-r8a774a1",
  628. "renesas,rcar-gen3-i2c";
  629. reg = <0 0xe66e0000 0 0x40>;
  630. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  631. clocks = <&cpg CPG_MOD 919>;
  632. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  633. resets = <&cpg 919>;
  634. dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
  635. dma-names = "tx", "rx";
  636. i2c-scl-internal-delay-ns = <110>;
  637. status = "disabled";
  638. };
  639. i2c6: i2c@e66e8000 {
  640. #address-cells = <1>;
  641. #size-cells = <0>;
  642. compatible = "renesas,i2c-r8a774a1",
  643. "renesas,rcar-gen3-i2c";
  644. reg = <0 0xe66e8000 0 0x40>;
  645. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  646. clocks = <&cpg CPG_MOD 918>;
  647. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  648. resets = <&cpg 918>;
  649. dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
  650. dma-names = "tx", "rx";
  651. i2c-scl-internal-delay-ns = <6>;
  652. status = "disabled";
  653. };
  654. i2c_dvfs: i2c@e60b0000 {
  655. #address-cells = <1>;
  656. #size-cells = <0>;
  657. compatible = "renesas,iic-r8a774a1",
  658. "renesas,rcar-gen3-iic",
  659. "renesas,rmobile-iic";
  660. reg = <0 0xe60b0000 0 0x425>;
  661. interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
  662. clocks = <&cpg CPG_MOD 926>;
  663. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  664. resets = <&cpg 926>;
  665. dmas = <&dmac0 0x11>, <&dmac0 0x10>;
  666. dma-names = "tx", "rx";
  667. status = "disabled";
  668. };
  669. hscif0: serial@e6540000 {
  670. compatible = "renesas,hscif-r8a774a1",
  671. "renesas,rcar-gen3-hscif",
  672. "renesas,hscif";
  673. reg = <0 0xe6540000 0 0x60>;
  674. interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  675. clocks = <&cpg CPG_MOD 520>,
  676. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  677. <&scif_clk>;
  678. clock-names = "fck", "brg_int", "scif_clk";
  679. dmas = <&dmac1 0x31>, <&dmac1 0x30>,
  680. <&dmac2 0x31>, <&dmac2 0x30>;
  681. dma-names = "tx", "rx", "tx", "rx";
  682. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  683. resets = <&cpg 520>;
  684. status = "disabled";
  685. };
  686. hscif1: serial@e6550000 {
  687. compatible = "renesas,hscif-r8a774a1",
  688. "renesas,rcar-gen3-hscif",
  689. "renesas,hscif";
  690. reg = <0 0xe6550000 0 0x60>;
  691. interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  692. clocks = <&cpg CPG_MOD 519>,
  693. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  694. <&scif_clk>;
  695. clock-names = "fck", "brg_int", "scif_clk";
  696. dmas = <&dmac1 0x33>, <&dmac1 0x32>,
  697. <&dmac2 0x33>, <&dmac2 0x32>;
  698. dma-names = "tx", "rx", "tx", "rx";
  699. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  700. resets = <&cpg 519>;
  701. status = "disabled";
  702. };
  703. hscif2: serial@e6560000 {
  704. compatible = "renesas,hscif-r8a774a1",
  705. "renesas,rcar-gen3-hscif",
  706. "renesas,hscif";
  707. reg = <0 0xe6560000 0 0x60>;
  708. interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
  709. clocks = <&cpg CPG_MOD 518>,
  710. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  711. <&scif_clk>;
  712. clock-names = "fck", "brg_int", "scif_clk";
  713. dmas = <&dmac1 0x35>, <&dmac1 0x34>,
  714. <&dmac2 0x35>, <&dmac2 0x34>;
  715. dma-names = "tx", "rx", "tx", "rx";
  716. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  717. resets = <&cpg 518>;
  718. status = "disabled";
  719. };
  720. hscif3: serial@e66a0000 {
  721. compatible = "renesas,hscif-r8a774a1",
  722. "renesas,rcar-gen3-hscif",
  723. "renesas,hscif";
  724. reg = <0 0xe66a0000 0 0x60>;
  725. interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
  726. clocks = <&cpg CPG_MOD 517>,
  727. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  728. <&scif_clk>;
  729. clock-names = "fck", "brg_int", "scif_clk";
  730. dmas = <&dmac0 0x37>, <&dmac0 0x36>;
  731. dma-names = "tx", "rx";
  732. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  733. resets = <&cpg 517>;
  734. status = "disabled";
  735. };
  736. hscif4: serial@e66b0000 {
  737. compatible = "renesas,hscif-r8a774a1",
  738. "renesas,rcar-gen3-hscif",
  739. "renesas,hscif";
  740. reg = <0 0xe66b0000 0 0x60>;
  741. interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  742. clocks = <&cpg CPG_MOD 516>,
  743. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  744. <&scif_clk>;
  745. clock-names = "fck", "brg_int", "scif_clk";
  746. dmas = <&dmac0 0x39>, <&dmac0 0x38>;
  747. dma-names = "tx", "rx";
  748. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  749. resets = <&cpg 516>;
  750. status = "disabled";
  751. };
  752. hsusb: usb@e6590000 {
  753. compatible = "renesas,usbhs-r8a774a1",
  754. "renesas,rcar-gen3-usbhs";
  755. reg = <0 0xe6590000 0 0x200>;
  756. interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  757. clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
  758. dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
  759. <&usb_dmac1 0>, <&usb_dmac1 1>;
  760. dma-names = "ch0", "ch1", "ch2", "ch3";
  761. renesas,buswait = <11>;
  762. phys = <&usb2_phy0 3>;
  763. phy-names = "usb";
  764. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  765. resets = <&cpg 704>, <&cpg 703>;
  766. status = "disabled";
  767. };
  768. usb_dmac0: dma-controller@e65a0000 {
  769. compatible = "renesas,r8a774a1-usb-dmac",
  770. "renesas,usb-dmac";
  771. reg = <0 0xe65a0000 0 0x100>;
  772. interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  773. <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
  774. interrupt-names = "ch0", "ch1";
  775. clocks = <&cpg CPG_MOD 330>;
  776. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  777. resets = <&cpg 330>;
  778. #dma-cells = <1>;
  779. dma-channels = <2>;
  780. };
  781. usb_dmac1: dma-controller@e65b0000 {
  782. compatible = "renesas,r8a774a1-usb-dmac",
  783. "renesas,usb-dmac";
  784. reg = <0 0xe65b0000 0 0x100>;
  785. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  786. <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  787. interrupt-names = "ch0", "ch1";
  788. clocks = <&cpg CPG_MOD 331>;
  789. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  790. resets = <&cpg 331>;
  791. #dma-cells = <1>;
  792. dma-channels = <2>;
  793. };
  794. usb3_phy0: usb-phy@e65ee000 {
  795. compatible = "renesas,r8a774a1-usb3-phy",
  796. "renesas,rcar-gen3-usb3-phy";
  797. reg = <0 0xe65ee000 0 0x90>;
  798. clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
  799. <&usb_extal_clk>;
  800. clock-names = "usb3-if", "usb3s_clk", "usb_extal";
  801. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  802. resets = <&cpg 328>;
  803. #phy-cells = <0>;
  804. status = "disabled";
  805. };
  806. dmac0: dma-controller@e6700000 {
  807. compatible = "renesas,dmac-r8a774a1",
  808. "renesas,rcar-dmac";
  809. reg = <0 0xe6700000 0 0x10000>;
  810. interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
  811. <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
  812. <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
  813. <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
  814. <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
  815. <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
  816. <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
  817. <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
  818. <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
  819. <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
  820. <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
  821. <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
  822. <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
  823. <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
  824. <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
  825. <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
  826. <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
  827. interrupt-names = "error",
  828. "ch0", "ch1", "ch2", "ch3",
  829. "ch4", "ch5", "ch6", "ch7",
  830. "ch8", "ch9", "ch10", "ch11",
  831. "ch12", "ch13", "ch14", "ch15";
  832. clocks = <&cpg CPG_MOD 219>;
  833. clock-names = "fck";
  834. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  835. resets = <&cpg 219>;
  836. #dma-cells = <1>;
  837. dma-channels = <16>;
  838. iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
  839. <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
  840. <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
  841. <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
  842. <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
  843. <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
  844. <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
  845. <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
  846. };
  847. dmac1: dma-controller@e7300000 {
  848. compatible = "renesas,dmac-r8a774a1",
  849. "renesas,rcar-dmac";
  850. reg = <0 0xe7300000 0 0x10000>;
  851. interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
  852. <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
  853. <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
  854. <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
  855. <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
  856. <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
  857. <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  858. <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  859. <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  860. <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  861. <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
  862. <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
  863. <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
  864. <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
  865. <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
  866. <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
  867. <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
  868. interrupt-names = "error",
  869. "ch0", "ch1", "ch2", "ch3",
  870. "ch4", "ch5", "ch6", "ch7",
  871. "ch8", "ch9", "ch10", "ch11",
  872. "ch12", "ch13", "ch14", "ch15";
  873. clocks = <&cpg CPG_MOD 218>;
  874. clock-names = "fck";
  875. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  876. resets = <&cpg 218>;
  877. #dma-cells = <1>;
  878. dma-channels = <16>;
  879. iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
  880. <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
  881. <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
  882. <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
  883. <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
  884. <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
  885. <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
  886. <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
  887. };
  888. dmac2: dma-controller@e7310000 {
  889. compatible = "renesas,dmac-r8a774a1",
  890. "renesas,rcar-dmac";
  891. reg = <0 0xe7310000 0 0x10000>;
  892. interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
  893. <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
  894. <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
  895. <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
  896. <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
  897. <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
  898. <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
  899. <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
  900. <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
  901. <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
  902. <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
  903. <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
  904. <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
  905. <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
  906. <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
  907. <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
  908. <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
  909. interrupt-names = "error",
  910. "ch0", "ch1", "ch2", "ch3",
  911. "ch4", "ch5", "ch6", "ch7",
  912. "ch8", "ch9", "ch10", "ch11",
  913. "ch12", "ch13", "ch14", "ch15";
  914. clocks = <&cpg CPG_MOD 217>;
  915. clock-names = "fck";
  916. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  917. resets = <&cpg 217>;
  918. #dma-cells = <1>;
  919. dma-channels = <16>;
  920. iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
  921. <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
  922. <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
  923. <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
  924. <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
  925. <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
  926. <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
  927. <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
  928. };
  929. ipmmu_ds0: iommu@e6740000 {
  930. compatible = "renesas,ipmmu-r8a774a1";
  931. reg = <0 0xe6740000 0 0x1000>;
  932. renesas,ipmmu-main = <&ipmmu_mm 0>;
  933. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  934. #iommu-cells = <1>;
  935. };
  936. ipmmu_ds1: iommu@e7740000 {
  937. compatible = "renesas,ipmmu-r8a774a1";
  938. reg = <0 0xe7740000 0 0x1000>;
  939. renesas,ipmmu-main = <&ipmmu_mm 1>;
  940. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  941. #iommu-cells = <1>;
  942. };
  943. ipmmu_hc: iommu@e6570000 {
  944. compatible = "renesas,ipmmu-r8a774a1";
  945. reg = <0 0xe6570000 0 0x1000>;
  946. renesas,ipmmu-main = <&ipmmu_mm 2>;
  947. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  948. #iommu-cells = <1>;
  949. };
  950. ipmmu_mm: iommu@e67b0000 {
  951. compatible = "renesas,ipmmu-r8a774a1";
  952. reg = <0 0xe67b0000 0 0x1000>;
  953. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
  954. <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
  955. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  956. #iommu-cells = <1>;
  957. };
  958. ipmmu_mp: iommu@ec670000 {
  959. compatible = "renesas,ipmmu-r8a774a1";
  960. reg = <0 0xec670000 0 0x1000>;
  961. renesas,ipmmu-main = <&ipmmu_mm 4>;
  962. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  963. #iommu-cells = <1>;
  964. };
  965. ipmmu_pv0: iommu@fd800000 {
  966. compatible = "renesas,ipmmu-r8a774a1";
  967. reg = <0 0xfd800000 0 0x1000>;
  968. renesas,ipmmu-main = <&ipmmu_mm 5>;
  969. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  970. #iommu-cells = <1>;
  971. };
  972. ipmmu_pv1: iommu@fd950000 {
  973. compatible = "renesas,ipmmu-r8a774a1";
  974. reg = <0 0xfd950000 0 0x1000>;
  975. renesas,ipmmu-main = <&ipmmu_mm 6>;
  976. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  977. #iommu-cells = <1>;
  978. };
  979. ipmmu_vc0: iommu@fe6b0000 {
  980. compatible = "renesas,ipmmu-r8a774a1";
  981. reg = <0 0xfe6b0000 0 0x1000>;
  982. renesas,ipmmu-main = <&ipmmu_mm 8>;
  983. power-domains = <&sysc R8A774A1_PD_A3VC>;
  984. #iommu-cells = <1>;
  985. };
  986. ipmmu_vi0: iommu@febd0000 {
  987. compatible = "renesas,ipmmu-r8a774a1";
  988. reg = <0 0xfebd0000 0 0x1000>;
  989. renesas,ipmmu-main = <&ipmmu_mm 9>;
  990. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  991. #iommu-cells = <1>;
  992. };
  993. avb: ethernet@e6800000 {
  994. compatible = "renesas,etheravb-r8a774a1",
  995. "renesas,etheravb-rcar-gen3";
  996. reg = <0 0xe6800000 0 0x800>;
  997. interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
  998. <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  999. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  1000. <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  1001. <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
  1002. <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
  1003. <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
  1004. <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
  1005. <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  1006. <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
  1007. <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
  1008. <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
  1009. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  1010. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  1011. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  1012. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  1013. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  1014. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  1015. <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
  1016. <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
  1017. <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
  1018. <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
  1019. <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
  1020. <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
  1021. <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  1022. interrupt-names = "ch0", "ch1", "ch2", "ch3",
  1023. "ch4", "ch5", "ch6", "ch7",
  1024. "ch8", "ch9", "ch10", "ch11",
  1025. "ch12", "ch13", "ch14", "ch15",
  1026. "ch16", "ch17", "ch18", "ch19",
  1027. "ch20", "ch21", "ch22", "ch23",
  1028. "ch24";
  1029. clocks = <&cpg CPG_MOD 812>;
  1030. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1031. resets = <&cpg 812>;
  1032. phy-mode = "rgmii";
  1033. iommus = <&ipmmu_ds0 16>;
  1034. #address-cells = <1>;
  1035. #size-cells = <0>;
  1036. status = "disabled";
  1037. };
  1038. can0: can@e6c30000 {
  1039. compatible = "renesas,can-r8a774a1",
  1040. "renesas,rcar-gen3-can";
  1041. reg = <0 0xe6c30000 0 0x1000>;
  1042. interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
  1043. clocks = <&cpg CPG_MOD 916>,
  1044. <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
  1045. <&can_clk>;
  1046. clock-names = "clkp1", "clkp2", "can_clk";
  1047. assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
  1048. assigned-clock-rates = <40000000>;
  1049. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1050. resets = <&cpg 916>;
  1051. status = "disabled";
  1052. };
  1053. can1: can@e6c38000 {
  1054. compatible = "renesas,can-r8a774a1",
  1055. "renesas,rcar-gen3-can";
  1056. reg = <0 0xe6c38000 0 0x1000>;
  1057. interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
  1058. clocks = <&cpg CPG_MOD 915>,
  1059. <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
  1060. <&can_clk>;
  1061. clock-names = "clkp1", "clkp2", "can_clk";
  1062. assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
  1063. assigned-clock-rates = <40000000>;
  1064. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1065. resets = <&cpg 915>;
  1066. status = "disabled";
  1067. };
  1068. canfd: can@e66c0000 {
  1069. compatible = "renesas,r8a774a1-canfd",
  1070. "renesas,rcar-gen3-canfd";
  1071. reg = <0 0xe66c0000 0 0x8000>;
  1072. interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  1073. <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  1074. clocks = <&cpg CPG_MOD 914>,
  1075. <&cpg CPG_CORE R8A774A1_CLK_CANFD>,
  1076. <&can_clk>;
  1077. clock-names = "fck", "canfd", "can_clk";
  1078. assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
  1079. assigned-clock-rates = <40000000>;
  1080. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1081. resets = <&cpg 914>;
  1082. status = "disabled";
  1083. channel0 {
  1084. status = "disabled";
  1085. };
  1086. channel1 {
  1087. status = "disabled";
  1088. };
  1089. };
  1090. pwm0: pwm@e6e30000 {
  1091. compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
  1092. reg = <0 0xe6e30000 0 0x8>;
  1093. #pwm-cells = <2>;
  1094. clocks = <&cpg CPG_MOD 523>;
  1095. resets = <&cpg 523>;
  1096. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1097. status = "disabled";
  1098. };
  1099. pwm1: pwm@e6e31000 {
  1100. compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
  1101. reg = <0 0xe6e31000 0 0x8>;
  1102. #pwm-cells = <2>;
  1103. clocks = <&cpg CPG_MOD 523>;
  1104. resets = <&cpg 523>;
  1105. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1106. status = "disabled";
  1107. };
  1108. pwm2: pwm@e6e32000 {
  1109. compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
  1110. reg = <0 0xe6e32000 0 0x8>;
  1111. #pwm-cells = <2>;
  1112. clocks = <&cpg CPG_MOD 523>;
  1113. resets = <&cpg 523>;
  1114. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1115. status = "disabled";
  1116. };
  1117. pwm3: pwm@e6e33000 {
  1118. compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
  1119. reg = <0 0xe6e33000 0 0x8>;
  1120. #pwm-cells = <2>;
  1121. clocks = <&cpg CPG_MOD 523>;
  1122. resets = <&cpg 523>;
  1123. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1124. status = "disabled";
  1125. };
  1126. pwm4: pwm@e6e34000 {
  1127. compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
  1128. reg = <0 0xe6e34000 0 0x8>;
  1129. #pwm-cells = <2>;
  1130. clocks = <&cpg CPG_MOD 523>;
  1131. resets = <&cpg 523>;
  1132. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1133. status = "disabled";
  1134. };
  1135. pwm5: pwm@e6e35000 {
  1136. compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
  1137. reg = <0 0xe6e35000 0 0x8>;
  1138. #pwm-cells = <2>;
  1139. clocks = <&cpg CPG_MOD 523>;
  1140. resets = <&cpg 523>;
  1141. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1142. status = "disabled";
  1143. };
  1144. pwm6: pwm@e6e36000 {
  1145. compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
  1146. reg = <0 0xe6e36000 0 0x8>;
  1147. #pwm-cells = <2>;
  1148. clocks = <&cpg CPG_MOD 523>;
  1149. resets = <&cpg 523>;
  1150. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1151. status = "disabled";
  1152. };
  1153. scif0: serial@e6e60000 {
  1154. compatible = "renesas,scif-r8a774a1",
  1155. "renesas,rcar-gen3-scif", "renesas,scif";
  1156. reg = <0 0xe6e60000 0 0x40>;
  1157. interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
  1158. clocks = <&cpg CPG_MOD 207>,
  1159. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  1160. <&scif_clk>;
  1161. clock-names = "fck", "brg_int", "scif_clk";
  1162. dmas = <&dmac1 0x51>, <&dmac1 0x50>,
  1163. <&dmac2 0x51>, <&dmac2 0x50>;
  1164. dma-names = "tx", "rx", "tx", "rx";
  1165. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1166. resets = <&cpg 207>;
  1167. status = "disabled";
  1168. };
  1169. scif1: serial@e6e68000 {
  1170. compatible = "renesas,scif-r8a774a1",
  1171. "renesas,rcar-gen3-scif", "renesas,scif";
  1172. reg = <0 0xe6e68000 0 0x40>;
  1173. interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  1174. clocks = <&cpg CPG_MOD 206>,
  1175. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  1176. <&scif_clk>;
  1177. clock-names = "fck", "brg_int", "scif_clk";
  1178. dmas = <&dmac1 0x53>, <&dmac1 0x52>,
  1179. <&dmac2 0x53>, <&dmac2 0x52>;
  1180. dma-names = "tx", "rx", "tx", "rx";
  1181. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1182. resets = <&cpg 206>;
  1183. status = "disabled";
  1184. };
  1185. scif2: serial@e6e88000 {
  1186. compatible = "renesas,scif-r8a774a1",
  1187. "renesas,rcar-gen3-scif", "renesas,scif";
  1188. reg = <0 0xe6e88000 0 0x40>;
  1189. interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  1190. clocks = <&cpg CPG_MOD 310>,
  1191. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  1192. <&scif_clk>;
  1193. clock-names = "fck", "brg_int", "scif_clk";
  1194. dmas = <&dmac1 0x13>, <&dmac1 0x12>,
  1195. <&dmac2 0x13>, <&dmac2 0x12>;
  1196. dma-names = "tx", "rx", "tx", "rx";
  1197. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1198. resets = <&cpg 310>;
  1199. status = "disabled";
  1200. };
  1201. scif3: serial@e6c50000 {
  1202. compatible = "renesas,scif-r8a774a1",
  1203. "renesas,rcar-gen3-scif", "renesas,scif";
  1204. reg = <0 0xe6c50000 0 0x40>;
  1205. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  1206. clocks = <&cpg CPG_MOD 204>,
  1207. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  1208. <&scif_clk>;
  1209. clock-names = "fck", "brg_int", "scif_clk";
  1210. dmas = <&dmac0 0x57>, <&dmac0 0x56>;
  1211. dma-names = "tx", "rx";
  1212. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1213. resets = <&cpg 204>;
  1214. status = "disabled";
  1215. };
  1216. scif4: serial@e6c40000 {
  1217. compatible = "renesas,scif-r8a774a1",
  1218. "renesas,rcar-gen3-scif", "renesas,scif";
  1219. reg = <0 0xe6c40000 0 0x40>;
  1220. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  1221. clocks = <&cpg CPG_MOD 203>,
  1222. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  1223. <&scif_clk>;
  1224. clock-names = "fck", "brg_int", "scif_clk";
  1225. dmas = <&dmac0 0x59>, <&dmac0 0x58>;
  1226. dma-names = "tx", "rx";
  1227. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1228. resets = <&cpg 203>;
  1229. status = "disabled";
  1230. };
  1231. scif5: serial@e6f30000 {
  1232. compatible = "renesas,scif-r8a774a1",
  1233. "renesas,rcar-gen3-scif", "renesas,scif";
  1234. reg = <0 0xe6f30000 0 0x40>;
  1235. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  1236. clocks = <&cpg CPG_MOD 202>,
  1237. <&cpg CPG_CORE R8A774A1_CLK_S3D1>,
  1238. <&scif_clk>;
  1239. clock-names = "fck", "brg_int", "scif_clk";
  1240. dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
  1241. <&dmac2 0x5b>, <&dmac2 0x5a>;
  1242. dma-names = "tx", "rx", "tx", "rx";
  1243. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1244. resets = <&cpg 202>;
  1245. status = "disabled";
  1246. };
  1247. msiof0: spi@e6e90000 {
  1248. compatible = "renesas,msiof-r8a774a1",
  1249. "renesas,rcar-gen3-msiof";
  1250. reg = <0 0xe6e90000 0 0x0064>;
  1251. interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
  1252. clocks = <&cpg CPG_MOD 211>;
  1253. dmas = <&dmac1 0x41>, <&dmac1 0x40>,
  1254. <&dmac2 0x41>, <&dmac2 0x40>;
  1255. dma-names = "tx", "rx", "tx", "rx";
  1256. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1257. resets = <&cpg 211>;
  1258. #address-cells = <1>;
  1259. #size-cells = <0>;
  1260. status = "disabled";
  1261. };
  1262. msiof1: spi@e6ea0000 {
  1263. compatible = "renesas,msiof-r8a774a1",
  1264. "renesas,rcar-gen3-msiof";
  1265. reg = <0 0xe6ea0000 0 0x0064>;
  1266. interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  1267. clocks = <&cpg CPG_MOD 210>;
  1268. dmas = <&dmac1 0x43>, <&dmac1 0x42>,
  1269. <&dmac2 0x43>, <&dmac2 0x42>;
  1270. dma-names = "tx", "rx", "tx", "rx";
  1271. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1272. resets = <&cpg 210>;
  1273. #address-cells = <1>;
  1274. #size-cells = <0>;
  1275. status = "disabled";
  1276. };
  1277. msiof2: spi@e6c00000 {
  1278. compatible = "renesas,msiof-r8a774a1",
  1279. "renesas,rcar-gen3-msiof";
  1280. reg = <0 0xe6c00000 0 0x0064>;
  1281. interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
  1282. clocks = <&cpg CPG_MOD 209>;
  1283. dmas = <&dmac0 0x45>, <&dmac0 0x44>;
  1284. dma-names = "tx", "rx";
  1285. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1286. resets = <&cpg 209>;
  1287. #address-cells = <1>;
  1288. #size-cells = <0>;
  1289. status = "disabled";
  1290. };
  1291. msiof3: spi@e6c10000 {
  1292. compatible = "renesas,msiof-r8a774a1",
  1293. "renesas,rcar-gen3-msiof";
  1294. reg = <0 0xe6c10000 0 0x0064>;
  1295. interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  1296. clocks = <&cpg CPG_MOD 208>;
  1297. dmas = <&dmac0 0x47>, <&dmac0 0x46>;
  1298. dma-names = "tx", "rx";
  1299. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1300. resets = <&cpg 208>;
  1301. #address-cells = <1>;
  1302. #size-cells = <0>;
  1303. status = "disabled";
  1304. };
  1305. vin0: video@e6ef0000 {
  1306. compatible = "renesas,vin-r8a774a1";
  1307. reg = <0 0xe6ef0000 0 0x1000>;
  1308. interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
  1309. clocks = <&cpg CPG_MOD 811>;
  1310. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1311. resets = <&cpg 811>;
  1312. renesas,id = <0>;
  1313. status = "disabled";
  1314. ports {
  1315. #address-cells = <1>;
  1316. #size-cells = <0>;
  1317. port@1 {
  1318. #address-cells = <1>;
  1319. #size-cells = <0>;
  1320. reg = <1>;
  1321. vin0csi20: endpoint@0 {
  1322. reg = <0>;
  1323. remote-endpoint = <&csi20vin0>;
  1324. };
  1325. vin0csi40: endpoint@2 {
  1326. reg = <2>;
  1327. remote-endpoint = <&csi40vin0>;
  1328. };
  1329. };
  1330. };
  1331. };
  1332. vin1: video@e6ef1000 {
  1333. compatible = "renesas,vin-r8a774a1";
  1334. reg = <0 0xe6ef1000 0 0x1000>;
  1335. interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
  1336. clocks = <&cpg CPG_MOD 810>;
  1337. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1338. resets = <&cpg 810>;
  1339. renesas,id = <1>;
  1340. status = "disabled";
  1341. ports {
  1342. #address-cells = <1>;
  1343. #size-cells = <0>;
  1344. port@1 {
  1345. #address-cells = <1>;
  1346. #size-cells = <0>;
  1347. reg = <1>;
  1348. vin1csi20: endpoint@0 {
  1349. reg = <0>;
  1350. remote-endpoint = <&csi20vin1>;
  1351. };
  1352. vin1csi40: endpoint@2 {
  1353. reg = <2>;
  1354. remote-endpoint = <&csi40vin1>;
  1355. };
  1356. };
  1357. };
  1358. };
  1359. vin2: video@e6ef2000 {
  1360. compatible = "renesas,vin-r8a774a1";
  1361. reg = <0 0xe6ef2000 0 0x1000>;
  1362. interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
  1363. clocks = <&cpg CPG_MOD 809>;
  1364. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1365. resets = <&cpg 809>;
  1366. renesas,id = <2>;
  1367. status = "disabled";
  1368. ports {
  1369. #address-cells = <1>;
  1370. #size-cells = <0>;
  1371. port@1 {
  1372. #address-cells = <1>;
  1373. #size-cells = <0>;
  1374. reg = <1>;
  1375. vin2csi20: endpoint@0 {
  1376. reg = <0>;
  1377. remote-endpoint = <&csi20vin2>;
  1378. };
  1379. vin2csi40: endpoint@2 {
  1380. reg = <2>;
  1381. remote-endpoint = <&csi40vin2>;
  1382. };
  1383. };
  1384. };
  1385. };
  1386. vin3: video@e6ef3000 {
  1387. compatible = "renesas,vin-r8a774a1";
  1388. reg = <0 0xe6ef3000 0 0x1000>;
  1389. interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
  1390. clocks = <&cpg CPG_MOD 808>;
  1391. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1392. resets = <&cpg 808>;
  1393. renesas,id = <3>;
  1394. status = "disabled";
  1395. ports {
  1396. #address-cells = <1>;
  1397. #size-cells = <0>;
  1398. port@1 {
  1399. #address-cells = <1>;
  1400. #size-cells = <0>;
  1401. reg = <1>;
  1402. vin3csi20: endpoint@0 {
  1403. reg = <0>;
  1404. remote-endpoint = <&csi20vin3>;
  1405. };
  1406. vin3csi40: endpoint@2 {
  1407. reg = <2>;
  1408. remote-endpoint = <&csi40vin3>;
  1409. };
  1410. };
  1411. };
  1412. };
  1413. vin4: video@e6ef4000 {
  1414. compatible = "renesas,vin-r8a774a1";
  1415. reg = <0 0xe6ef4000 0 0x1000>;
  1416. interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
  1417. clocks = <&cpg CPG_MOD 807>;
  1418. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1419. resets = <&cpg 807>;
  1420. renesas,id = <4>;
  1421. status = "disabled";
  1422. ports {
  1423. #address-cells = <1>;
  1424. #size-cells = <0>;
  1425. port@1 {
  1426. #address-cells = <1>;
  1427. #size-cells = <0>;
  1428. reg = <1>;
  1429. vin4csi20: endpoint@0 {
  1430. reg = <0>;
  1431. remote-endpoint = <&csi20vin4>;
  1432. };
  1433. vin4csi40: endpoint@2 {
  1434. reg = <2>;
  1435. remote-endpoint = <&csi40vin4>;
  1436. };
  1437. };
  1438. };
  1439. };
  1440. vin5: video@e6ef5000 {
  1441. compatible = "renesas,vin-r8a774a1";
  1442. reg = <0 0xe6ef5000 0 0x1000>;
  1443. interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
  1444. clocks = <&cpg CPG_MOD 806>;
  1445. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1446. resets = <&cpg 806>;
  1447. renesas,id = <5>;
  1448. status = "disabled";
  1449. ports {
  1450. #address-cells = <1>;
  1451. #size-cells = <0>;
  1452. port@1 {
  1453. #address-cells = <1>;
  1454. #size-cells = <0>;
  1455. reg = <1>;
  1456. vin5csi20: endpoint@0 {
  1457. reg = <0>;
  1458. remote-endpoint = <&csi20vin5>;
  1459. };
  1460. vin5csi40: endpoint@2 {
  1461. reg = <2>;
  1462. remote-endpoint = <&csi40vin5>;
  1463. };
  1464. };
  1465. };
  1466. };
  1467. vin6: video@e6ef6000 {
  1468. compatible = "renesas,vin-r8a774a1";
  1469. reg = <0 0xe6ef6000 0 0x1000>;
  1470. interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
  1471. clocks = <&cpg CPG_MOD 805>;
  1472. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1473. resets = <&cpg 805>;
  1474. renesas,id = <6>;
  1475. status = "disabled";
  1476. ports {
  1477. #address-cells = <1>;
  1478. #size-cells = <0>;
  1479. port@1 {
  1480. #address-cells = <1>;
  1481. #size-cells = <0>;
  1482. reg = <1>;
  1483. vin6csi20: endpoint@0 {
  1484. reg = <0>;
  1485. remote-endpoint = <&csi20vin6>;
  1486. };
  1487. vin6csi40: endpoint@2 {
  1488. reg = <2>;
  1489. remote-endpoint = <&csi40vin6>;
  1490. };
  1491. };
  1492. };
  1493. };
  1494. vin7: video@e6ef7000 {
  1495. compatible = "renesas,vin-r8a774a1";
  1496. reg = <0 0xe6ef7000 0 0x1000>;
  1497. interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
  1498. clocks = <&cpg CPG_MOD 804>;
  1499. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1500. resets = <&cpg 804>;
  1501. renesas,id = <7>;
  1502. status = "disabled";
  1503. ports {
  1504. #address-cells = <1>;
  1505. #size-cells = <0>;
  1506. port@1 {
  1507. #address-cells = <1>;
  1508. #size-cells = <0>;
  1509. reg = <1>;
  1510. vin7csi20: endpoint@0 {
  1511. reg = <0>;
  1512. remote-endpoint = <&csi20vin7>;
  1513. };
  1514. vin7csi40: endpoint@2 {
  1515. reg = <2>;
  1516. remote-endpoint = <&csi40vin7>;
  1517. };
  1518. };
  1519. };
  1520. };
  1521. rcar_sound: sound@ec500000 {
  1522. /*
  1523. * #sound-dai-cells is required
  1524. *
  1525. * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
  1526. * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
  1527. */
  1528. /*
  1529. * #clock-cells is required for audio_clkout0/1/2/3
  1530. *
  1531. * clkout : #clock-cells = <0>; <&rcar_sound>;
  1532. * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
  1533. */
  1534. compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3";
  1535. reg = <0 0xec500000 0 0x1000>, /* SCU */
  1536. <0 0xec5a0000 0 0x100>, /* ADG */
  1537. <0 0xec540000 0 0x1000>, /* SSIU */
  1538. <0 0xec541000 0 0x280>, /* SSI */
  1539. <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
  1540. reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
  1541. clocks = <&cpg CPG_MOD 1005>,
  1542. <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
  1543. <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
  1544. <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
  1545. <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
  1546. <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
  1547. <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
  1548. <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
  1549. <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
  1550. <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
  1551. <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
  1552. <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
  1553. <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
  1554. <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
  1555. <&audio_clk_a>, <&audio_clk_b>,
  1556. <&audio_clk_c>,
  1557. <&cpg CPG_CORE R8A774A1_CLK_S0D4>;
  1558. clock-names = "ssi-all",
  1559. "ssi.9", "ssi.8", "ssi.7", "ssi.6",
  1560. "ssi.5", "ssi.4", "ssi.3", "ssi.2",
  1561. "ssi.1", "ssi.0",
  1562. "src.9", "src.8", "src.7", "src.6",
  1563. "src.5", "src.4", "src.3", "src.2",
  1564. "src.1", "src.0",
  1565. "mix.1", "mix.0",
  1566. "ctu.1", "ctu.0",
  1567. "dvc.0", "dvc.1",
  1568. "clk_a", "clk_b", "clk_c", "clk_i";
  1569. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1570. resets = <&cpg 1005>,
  1571. <&cpg 1006>, <&cpg 1007>,
  1572. <&cpg 1008>, <&cpg 1009>,
  1573. <&cpg 1010>, <&cpg 1011>,
  1574. <&cpg 1012>, <&cpg 1013>,
  1575. <&cpg 1014>, <&cpg 1015>;
  1576. reset-names = "ssi-all",
  1577. "ssi.9", "ssi.8", "ssi.7", "ssi.6",
  1578. "ssi.5", "ssi.4", "ssi.3", "ssi.2",
  1579. "ssi.1", "ssi.0";
  1580. status = "disabled";
  1581. rcar_sound,ctu {
  1582. ctu00: ctu-0 { };
  1583. ctu01: ctu-1 { };
  1584. ctu02: ctu-2 { };
  1585. ctu03: ctu-3 { };
  1586. ctu10: ctu-4 { };
  1587. ctu11: ctu-5 { };
  1588. ctu12: ctu-6 { };
  1589. ctu13: ctu-7 { };
  1590. };
  1591. rcar_sound,dvc {
  1592. dvc0: dvc-0 {
  1593. dmas = <&audma1 0xbc>;
  1594. dma-names = "tx";
  1595. };
  1596. dvc1: dvc-1 {
  1597. dmas = <&audma1 0xbe>;
  1598. dma-names = "tx";
  1599. };
  1600. };
  1601. rcar_sound,mix {
  1602. mix0: mix-0 { };
  1603. mix1: mix-1 { };
  1604. };
  1605. rcar_sound,src {
  1606. src0: src-0 {
  1607. interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
  1608. dmas = <&audma0 0x85>, <&audma1 0x9a>;
  1609. dma-names = "rx", "tx";
  1610. };
  1611. src1: src-1 {
  1612. interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
  1613. dmas = <&audma0 0x87>, <&audma1 0x9c>;
  1614. dma-names = "rx", "tx";
  1615. };
  1616. src2: src-2 {
  1617. interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
  1618. dmas = <&audma0 0x89>, <&audma1 0x9e>;
  1619. dma-names = "rx", "tx";
  1620. };
  1621. src3: src-3 {
  1622. interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
  1623. dmas = <&audma0 0x8b>, <&audma1 0xa0>;
  1624. dma-names = "rx", "tx";
  1625. };
  1626. src4: src-4 {
  1627. interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
  1628. dmas = <&audma0 0x8d>, <&audma1 0xb0>;
  1629. dma-names = "rx", "tx";
  1630. };
  1631. src5: src-5 {
  1632. interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
  1633. dmas = <&audma0 0x8f>, <&audma1 0xb2>;
  1634. dma-names = "rx", "tx";
  1635. };
  1636. src6: src-6 {
  1637. interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
  1638. dmas = <&audma0 0x91>, <&audma1 0xb4>;
  1639. dma-names = "rx", "tx";
  1640. };
  1641. src7: src-7 {
  1642. interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
  1643. dmas = <&audma0 0x93>, <&audma1 0xb6>;
  1644. dma-names = "rx", "tx";
  1645. };
  1646. src8: src-8 {
  1647. interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
  1648. dmas = <&audma0 0x95>, <&audma1 0xb8>;
  1649. dma-names = "rx", "tx";
  1650. };
  1651. src9: src-9 {
  1652. interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
  1653. dmas = <&audma0 0x97>, <&audma1 0xba>;
  1654. dma-names = "rx", "tx";
  1655. };
  1656. };
  1657. rcar_sound,ssi {
  1658. ssi0: ssi-0 {
  1659. interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
  1660. dmas = <&audma0 0x01>, <&audma1 0x02>;
  1661. dma-names = "rx", "tx";
  1662. };
  1663. ssi1: ssi-1 {
  1664. interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
  1665. dmas = <&audma0 0x03>, <&audma1 0x04>;
  1666. dma-names = "rx", "tx";
  1667. };
  1668. ssi2: ssi-2 {
  1669. interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
  1670. dmas = <&audma0 0x05>, <&audma1 0x06>;
  1671. dma-names = "rx", "tx";
  1672. };
  1673. ssi3: ssi-3 {
  1674. interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
  1675. dmas = <&audma0 0x07>, <&audma1 0x08>;
  1676. dma-names = "rx", "tx";
  1677. };
  1678. ssi4: ssi-4 {
  1679. interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
  1680. dmas = <&audma0 0x09>, <&audma1 0x0a>;
  1681. dma-names = "rx", "tx";
  1682. };
  1683. ssi5: ssi-5 {
  1684. interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
  1685. dmas = <&audma0 0x0b>, <&audma1 0x0c>;
  1686. dma-names = "rx", "tx";
  1687. };
  1688. ssi6: ssi-6 {
  1689. interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
  1690. dmas = <&audma0 0x0d>, <&audma1 0x0e>;
  1691. dma-names = "rx", "tx";
  1692. };
  1693. ssi7: ssi-7 {
  1694. interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
  1695. dmas = <&audma0 0x0f>, <&audma1 0x10>;
  1696. dma-names = "rx", "tx";
  1697. };
  1698. ssi8: ssi-8 {
  1699. interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
  1700. dmas = <&audma0 0x11>, <&audma1 0x12>;
  1701. dma-names = "rx", "tx";
  1702. };
  1703. ssi9: ssi-9 {
  1704. interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
  1705. dmas = <&audma0 0x13>, <&audma1 0x14>;
  1706. dma-names = "rx", "tx";
  1707. };
  1708. };
  1709. rcar_sound,ssiu {
  1710. ssiu00: ssiu-0 {
  1711. dmas = <&audma0 0x15>, <&audma1 0x16>;
  1712. dma-names = "rx", "tx";
  1713. };
  1714. ssiu01: ssiu-1 {
  1715. dmas = <&audma0 0x35>, <&audma1 0x36>;
  1716. dma-names = "rx", "tx";
  1717. };
  1718. ssiu02: ssiu-2 {
  1719. dmas = <&audma0 0x37>, <&audma1 0x38>;
  1720. dma-names = "rx", "tx";
  1721. };
  1722. ssiu03: ssiu-3 {
  1723. dmas = <&audma0 0x47>, <&audma1 0x48>;
  1724. dma-names = "rx", "tx";
  1725. };
  1726. ssiu04: ssiu-4 {
  1727. dmas = <&audma0 0x3F>, <&audma1 0x40>;
  1728. dma-names = "rx", "tx";
  1729. };
  1730. ssiu05: ssiu-5 {
  1731. dmas = <&audma0 0x43>, <&audma1 0x44>;
  1732. dma-names = "rx", "tx";
  1733. };
  1734. ssiu06: ssiu-6 {
  1735. dmas = <&audma0 0x4F>, <&audma1 0x50>;
  1736. dma-names = "rx", "tx";
  1737. };
  1738. ssiu07: ssiu-7 {
  1739. dmas = <&audma0 0x53>, <&audma1 0x54>;
  1740. dma-names = "rx", "tx";
  1741. };
  1742. ssiu10: ssiu-8 {
  1743. dmas = <&audma0 0x49>, <&audma1 0x4a>;
  1744. dma-names = "rx", "tx";
  1745. };
  1746. ssiu11: ssiu-9 {
  1747. dmas = <&audma0 0x4B>, <&audma1 0x4C>;
  1748. dma-names = "rx", "tx";
  1749. };
  1750. ssiu12: ssiu-10 {
  1751. dmas = <&audma0 0x57>, <&audma1 0x58>;
  1752. dma-names = "rx", "tx";
  1753. };
  1754. ssiu13: ssiu-11 {
  1755. dmas = <&audma0 0x59>, <&audma1 0x5A>;
  1756. dma-names = "rx", "tx";
  1757. };
  1758. ssiu14: ssiu-12 {
  1759. dmas = <&audma0 0x5F>, <&audma1 0x60>;
  1760. dma-names = "rx", "tx";
  1761. };
  1762. ssiu15: ssiu-13 {
  1763. dmas = <&audma0 0xC3>, <&audma1 0xC4>;
  1764. dma-names = "rx", "tx";
  1765. };
  1766. ssiu16: ssiu-14 {
  1767. dmas = <&audma0 0xC7>, <&audma1 0xC8>;
  1768. dma-names = "rx", "tx";
  1769. };
  1770. ssiu17: ssiu-15 {
  1771. dmas = <&audma0 0xCB>, <&audma1 0xCC>;
  1772. dma-names = "rx", "tx";
  1773. };
  1774. ssiu20: ssiu-16 {
  1775. dmas = <&audma0 0x63>, <&audma1 0x64>;
  1776. dma-names = "rx", "tx";
  1777. };
  1778. ssiu21: ssiu-17 {
  1779. dmas = <&audma0 0x67>, <&audma1 0x68>;
  1780. dma-names = "rx", "tx";
  1781. };
  1782. ssiu22: ssiu-18 {
  1783. dmas = <&audma0 0x6B>, <&audma1 0x6C>;
  1784. dma-names = "rx", "tx";
  1785. };
  1786. ssiu23: ssiu-19 {
  1787. dmas = <&audma0 0x6D>, <&audma1 0x6E>;
  1788. dma-names = "rx", "tx";
  1789. };
  1790. ssiu24: ssiu-20 {
  1791. dmas = <&audma0 0xCF>, <&audma1 0xCE>;
  1792. dma-names = "rx", "tx";
  1793. };
  1794. ssiu25: ssiu-21 {
  1795. dmas = <&audma0 0xEB>, <&audma1 0xEC>;
  1796. dma-names = "rx", "tx";
  1797. };
  1798. ssiu26: ssiu-22 {
  1799. dmas = <&audma0 0xED>, <&audma1 0xEE>;
  1800. dma-names = "rx", "tx";
  1801. };
  1802. ssiu27: ssiu-23 {
  1803. dmas = <&audma0 0xEF>, <&audma1 0xF0>;
  1804. dma-names = "rx", "tx";
  1805. };
  1806. ssiu30: ssiu-24 {
  1807. dmas = <&audma0 0x6f>, <&audma1 0x70>;
  1808. dma-names = "rx", "tx";
  1809. };
  1810. ssiu31: ssiu-25 {
  1811. dmas = <&audma0 0x21>, <&audma1 0x22>;
  1812. dma-names = "rx", "tx";
  1813. };
  1814. ssiu32: ssiu-26 {
  1815. dmas = <&audma0 0x23>, <&audma1 0x24>;
  1816. dma-names = "rx", "tx";
  1817. };
  1818. ssiu33: ssiu-27 {
  1819. dmas = <&audma0 0x25>, <&audma1 0x26>;
  1820. dma-names = "rx", "tx";
  1821. };
  1822. ssiu34: ssiu-28 {
  1823. dmas = <&audma0 0x27>, <&audma1 0x28>;
  1824. dma-names = "rx", "tx";
  1825. };
  1826. ssiu35: ssiu-29 {
  1827. dmas = <&audma0 0x29>, <&audma1 0x2A>;
  1828. dma-names = "rx", "tx";
  1829. };
  1830. ssiu36: ssiu-30 {
  1831. dmas = <&audma0 0x2B>, <&audma1 0x2C>;
  1832. dma-names = "rx", "tx";
  1833. };
  1834. ssiu37: ssiu-31 {
  1835. dmas = <&audma0 0x2D>, <&audma1 0x2E>;
  1836. dma-names = "rx", "tx";
  1837. };
  1838. ssiu40: ssiu-32 {
  1839. dmas = <&audma0 0x71>, <&audma1 0x72>;
  1840. dma-names = "rx", "tx";
  1841. };
  1842. ssiu41: ssiu-33 {
  1843. dmas = <&audma0 0x17>, <&audma1 0x18>;
  1844. dma-names = "rx", "tx";
  1845. };
  1846. ssiu42: ssiu-34 {
  1847. dmas = <&audma0 0x19>, <&audma1 0x1A>;
  1848. dma-names = "rx", "tx";
  1849. };
  1850. ssiu43: ssiu-35 {
  1851. dmas = <&audma0 0x1B>, <&audma1 0x1C>;
  1852. dma-names = "rx", "tx";
  1853. };
  1854. ssiu44: ssiu-36 {
  1855. dmas = <&audma0 0x1D>, <&audma1 0x1E>;
  1856. dma-names = "rx", "tx";
  1857. };
  1858. ssiu45: ssiu-37 {
  1859. dmas = <&audma0 0x1F>, <&audma1 0x20>;
  1860. dma-names = "rx", "tx";
  1861. };
  1862. ssiu46: ssiu-38 {
  1863. dmas = <&audma0 0x31>, <&audma1 0x32>;
  1864. dma-names = "rx", "tx";
  1865. };
  1866. ssiu47: ssiu-39 {
  1867. dmas = <&audma0 0x33>, <&audma1 0x34>;
  1868. dma-names = "rx", "tx";
  1869. };
  1870. ssiu50: ssiu-40 {
  1871. dmas = <&audma0 0x73>, <&audma1 0x74>;
  1872. dma-names = "rx", "tx";
  1873. };
  1874. ssiu60: ssiu-41 {
  1875. dmas = <&audma0 0x75>, <&audma1 0x76>;
  1876. dma-names = "rx", "tx";
  1877. };
  1878. ssiu70: ssiu-42 {
  1879. dmas = <&audma0 0x79>, <&audma1 0x7a>;
  1880. dma-names = "rx", "tx";
  1881. };
  1882. ssiu80: ssiu-43 {
  1883. dmas = <&audma0 0x7b>, <&audma1 0x7c>;
  1884. dma-names = "rx", "tx";
  1885. };
  1886. ssiu90: ssiu-44 {
  1887. dmas = <&audma0 0x7d>, <&audma1 0x7e>;
  1888. dma-names = "rx", "tx";
  1889. };
  1890. ssiu91: ssiu-45 {
  1891. dmas = <&audma0 0x7F>, <&audma1 0x80>;
  1892. dma-names = "rx", "tx";
  1893. };
  1894. ssiu92: ssiu-46 {
  1895. dmas = <&audma0 0x81>, <&audma1 0x82>;
  1896. dma-names = "rx", "tx";
  1897. };
  1898. ssiu93: ssiu-47 {
  1899. dmas = <&audma0 0x83>, <&audma1 0x84>;
  1900. dma-names = "rx", "tx";
  1901. };
  1902. ssiu94: ssiu-48 {
  1903. dmas = <&audma0 0xA3>, <&audma1 0xA4>;
  1904. dma-names = "rx", "tx";
  1905. };
  1906. ssiu95: ssiu-49 {
  1907. dmas = <&audma0 0xA5>, <&audma1 0xA6>;
  1908. dma-names = "rx", "tx";
  1909. };
  1910. ssiu96: ssiu-50 {
  1911. dmas = <&audma0 0xA7>, <&audma1 0xA8>;
  1912. dma-names = "rx", "tx";
  1913. };
  1914. ssiu97: ssiu-51 {
  1915. dmas = <&audma0 0xA9>, <&audma1 0xAA>;
  1916. dma-names = "rx", "tx";
  1917. };
  1918. };
  1919. };
  1920. audma0: dma-controller@ec700000 {
  1921. compatible = "renesas,dmac-r8a774a1",
  1922. "renesas,rcar-dmac";
  1923. reg = <0 0xec700000 0 0x10000>;
  1924. interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
  1925. <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  1926. <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
  1927. <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
  1928. <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
  1929. <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
  1930. <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
  1931. <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
  1932. <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
  1933. <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
  1934. <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
  1935. <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
  1936. <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
  1937. <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
  1938. <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
  1939. <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
  1940. <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
  1941. interrupt-names = "error",
  1942. "ch0", "ch1", "ch2", "ch3",
  1943. "ch4", "ch5", "ch6", "ch7",
  1944. "ch8", "ch9", "ch10", "ch11",
  1945. "ch12", "ch13", "ch14", "ch15";
  1946. clocks = <&cpg CPG_MOD 502>;
  1947. clock-names = "fck";
  1948. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1949. resets = <&cpg 502>;
  1950. #dma-cells = <1>;
  1951. dma-channels = <16>;
  1952. iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
  1953. <&ipmmu_mp 2>, <&ipmmu_mp 3>,
  1954. <&ipmmu_mp 4>, <&ipmmu_mp 5>,
  1955. <&ipmmu_mp 6>, <&ipmmu_mp 7>,
  1956. <&ipmmu_mp 8>, <&ipmmu_mp 9>,
  1957. <&ipmmu_mp 10>, <&ipmmu_mp 11>,
  1958. <&ipmmu_mp 12>, <&ipmmu_mp 13>,
  1959. <&ipmmu_mp 14>, <&ipmmu_mp 15>;
  1960. };
  1961. audma1: dma-controller@ec720000 {
  1962. compatible = "renesas,dmac-r8a774a1",
  1963. "renesas,rcar-dmac";
  1964. reg = <0 0xec720000 0 0x10000>;
  1965. interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
  1966. <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
  1967. <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
  1968. <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
  1969. <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
  1970. <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
  1971. <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
  1972. <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
  1973. <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
  1974. <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
  1975. <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
  1976. <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
  1977. <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
  1978. <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
  1979. <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
  1980. <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
  1981. <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
  1982. interrupt-names = "error",
  1983. "ch0", "ch1", "ch2", "ch3",
  1984. "ch4", "ch5", "ch6", "ch7",
  1985. "ch8", "ch9", "ch10", "ch11",
  1986. "ch12", "ch13", "ch14", "ch15";
  1987. clocks = <&cpg CPG_MOD 501>;
  1988. clock-names = "fck";
  1989. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  1990. resets = <&cpg 501>;
  1991. #dma-cells = <1>;
  1992. dma-channels = <16>;
  1993. iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
  1994. <&ipmmu_mp 18>, <&ipmmu_mp 19>,
  1995. <&ipmmu_mp 20>, <&ipmmu_mp 21>,
  1996. <&ipmmu_mp 22>, <&ipmmu_mp 23>,
  1997. <&ipmmu_mp 24>, <&ipmmu_mp 25>,
  1998. <&ipmmu_mp 26>, <&ipmmu_mp 27>,
  1999. <&ipmmu_mp 28>, <&ipmmu_mp 29>,
  2000. <&ipmmu_mp 30>, <&ipmmu_mp 31>;
  2001. };
  2002. xhci0: usb@ee000000 {
  2003. compatible = "renesas,xhci-r8a774a1",
  2004. "renesas,rcar-gen3-xhci";
  2005. reg = <0 0xee000000 0 0xc00>;
  2006. interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  2007. clocks = <&cpg CPG_MOD 328>;
  2008. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2009. resets = <&cpg 328>;
  2010. status = "disabled";
  2011. };
  2012. usb3_peri0: usb@ee020000 {
  2013. compatible = "renesas,r8a774a1-usb3-peri",
  2014. "renesas,rcar-gen3-usb3-peri";
  2015. reg = <0 0xee020000 0 0x400>;
  2016. interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
  2017. clocks = <&cpg CPG_MOD 328>;
  2018. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2019. resets = <&cpg 328>;
  2020. status = "disabled";
  2021. };
  2022. ohci0: usb@ee080000 {
  2023. compatible = "generic-ohci";
  2024. reg = <0 0xee080000 0 0x100>;
  2025. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  2026. clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
  2027. phys = <&usb2_phy0 1>;
  2028. phy-names = "usb";
  2029. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2030. resets = <&cpg 703>, <&cpg 704>;
  2031. status = "disabled";
  2032. };
  2033. ohci1: usb@ee0a0000 {
  2034. compatible = "generic-ohci";
  2035. reg = <0 0xee0a0000 0 0x100>;
  2036. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  2037. clocks = <&cpg CPG_MOD 702>;
  2038. phys = <&usb2_phy1 1>;
  2039. phy-names = "usb";
  2040. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2041. resets = <&cpg 702>;
  2042. status = "disabled";
  2043. };
  2044. ehci0: usb@ee080100 {
  2045. compatible = "generic-ehci";
  2046. reg = <0 0xee080100 0 0x100>;
  2047. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  2048. clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
  2049. phys = <&usb2_phy0 2>;
  2050. phy-names = "usb";
  2051. companion = <&ohci0>;
  2052. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2053. resets = <&cpg 703>, <&cpg 704>;
  2054. status = "disabled";
  2055. };
  2056. ehci1: usb@ee0a0100 {
  2057. compatible = "generic-ehci";
  2058. reg = <0 0xee0a0100 0 0x100>;
  2059. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  2060. clocks = <&cpg CPG_MOD 702>;
  2061. phys = <&usb2_phy1 2>;
  2062. phy-names = "usb";
  2063. companion = <&ohci1>;
  2064. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2065. resets = <&cpg 702>;
  2066. status = "disabled";
  2067. };
  2068. usb2_phy0: usb-phy@ee080200 {
  2069. compatible = "renesas,usb2-phy-r8a774a1",
  2070. "renesas,rcar-gen3-usb2-phy";
  2071. reg = <0 0xee080200 0 0x700>;
  2072. interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  2073. clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
  2074. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2075. resets = <&cpg 703>, <&cpg 704>;
  2076. #phy-cells = <1>;
  2077. status = "disabled";
  2078. };
  2079. usb2_phy1: usb-phy@ee0a0200 {
  2080. compatible = "renesas,usb2-phy-r8a774a1",
  2081. "renesas,rcar-gen3-usb2-phy";
  2082. reg = <0 0xee0a0200 0 0x700>;
  2083. clocks = <&cpg CPG_MOD 702>;
  2084. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2085. resets = <&cpg 702>;
  2086. #phy-cells = <1>;
  2087. status = "disabled";
  2088. };
  2089. sdhi0: mmc@ee100000 {
  2090. compatible = "renesas,sdhi-r8a774a1",
  2091. "renesas,rcar-gen3-sdhi";
  2092. reg = <0 0xee100000 0 0x2000>;
  2093. interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
  2094. clocks = <&cpg CPG_MOD 314>;
  2095. max-frequency = <200000000>;
  2096. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2097. resets = <&cpg 314>;
  2098. status = "disabled";
  2099. };
  2100. sdhi1: mmc@ee120000 {
  2101. compatible = "renesas,sdhi-r8a774a1",
  2102. "renesas,rcar-gen3-sdhi";
  2103. reg = <0 0xee120000 0 0x2000>;
  2104. interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
  2105. clocks = <&cpg CPG_MOD 313>;
  2106. max-frequency = <200000000>;
  2107. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2108. resets = <&cpg 313>;
  2109. status = "disabled";
  2110. };
  2111. sdhi2: mmc@ee140000 {
  2112. compatible = "renesas,sdhi-r8a774a1",
  2113. "renesas,rcar-gen3-sdhi";
  2114. reg = <0 0xee140000 0 0x2000>;
  2115. interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
  2116. clocks = <&cpg CPG_MOD 312>;
  2117. max-frequency = <200000000>;
  2118. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2119. resets = <&cpg 312>;
  2120. status = "disabled";
  2121. };
  2122. sdhi3: mmc@ee160000 {
  2123. compatible = "renesas,sdhi-r8a774a1",
  2124. "renesas,rcar-gen3-sdhi";
  2125. reg = <0 0xee160000 0 0x2000>;
  2126. interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
  2127. clocks = <&cpg CPG_MOD 311>;
  2128. max-frequency = <200000000>;
  2129. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2130. resets = <&cpg 311>;
  2131. status = "disabled";
  2132. };
  2133. gic: interrupt-controller@f1010000 {
  2134. compatible = "arm,gic-400";
  2135. #interrupt-cells = <3>;
  2136. #address-cells = <0>;
  2137. interrupt-controller;
  2138. reg = <0x0 0xf1010000 0 0x1000>,
  2139. <0x0 0xf1020000 0 0x20000>,
  2140. <0x0 0xf1040000 0 0x20000>,
  2141. <0x0 0xf1060000 0 0x20000>;
  2142. interrupts = <GIC_PPI 9
  2143. (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  2144. clocks = <&cpg CPG_MOD 408>;
  2145. clock-names = "clk";
  2146. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2147. resets = <&cpg 408>;
  2148. };
  2149. pciec0: pcie@fe000000 {
  2150. compatible = "renesas,pcie-r8a774a1",
  2151. "renesas,pcie-rcar-gen3";
  2152. reg = <0 0xfe000000 0 0x80000>;
  2153. #address-cells = <3>;
  2154. #size-cells = <2>;
  2155. bus-range = <0x00 0xff>;
  2156. device_type = "pci";
  2157. ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
  2158. <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
  2159. <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
  2160. <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
  2161. /* Map all possible DDR as inbound ranges */
  2162. dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
  2163. interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  2164. <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  2165. <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  2166. #interrupt-cells = <1>;
  2167. interrupt-map-mask = <0 0 0 0>;
  2168. interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
  2169. clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
  2170. clock-names = "pcie", "pcie_bus";
  2171. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2172. resets = <&cpg 319>;
  2173. status = "disabled";
  2174. };
  2175. pciec1: pcie@ee800000 {
  2176. compatible = "renesas,pcie-r8a774a1",
  2177. "renesas,pcie-rcar-gen3";
  2178. reg = <0 0xee800000 0 0x80000>;
  2179. #address-cells = <3>;
  2180. #size-cells = <2>;
  2181. bus-range = <0x00 0xff>;
  2182. device_type = "pci";
  2183. ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
  2184. <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
  2185. <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
  2186. <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
  2187. /* Map all possible DDR as inbound ranges */
  2188. dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
  2189. interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
  2190. <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
  2191. <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
  2192. #interrupt-cells = <1>;
  2193. interrupt-map-mask = <0 0 0 0>;
  2194. interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  2195. clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
  2196. clock-names = "pcie", "pcie_bus";
  2197. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2198. resets = <&cpg 318>;
  2199. status = "disabled";
  2200. };
  2201. fdp1@fe940000 {
  2202. compatible = "renesas,fdp1";
  2203. reg = <0 0xfe940000 0 0x2400>;
  2204. interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
  2205. clocks = <&cpg CPG_MOD 119>;
  2206. power-domains = <&sysc R8A774A1_PD_A3VC>;
  2207. resets = <&cpg 119>;
  2208. renesas,fcp = <&fcpf0>;
  2209. };
  2210. fcpf0: fcp@fe950000 {
  2211. compatible = "renesas,fcpf";
  2212. reg = <0 0xfe950000 0 0x200>;
  2213. clocks = <&cpg CPG_MOD 615>;
  2214. power-domains = <&sysc R8A774A1_PD_A3VC>;
  2215. resets = <&cpg 615>;
  2216. };
  2217. fcpvb0: fcp@fe96f000 {
  2218. compatible = "renesas,fcpv";
  2219. reg = <0 0xfe96f000 0 0x200>;
  2220. clocks = <&cpg CPG_MOD 607>;
  2221. power-domains = <&sysc R8A774A1_PD_A3VC>;
  2222. resets = <&cpg 607>;
  2223. };
  2224. fcpvd0: fcp@fea27000 {
  2225. compatible = "renesas,fcpv";
  2226. reg = <0 0xfea27000 0 0x200>;
  2227. clocks = <&cpg CPG_MOD 603>;
  2228. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2229. resets = <&cpg 603>;
  2230. iommus = <&ipmmu_vi0 8>;
  2231. };
  2232. fcpvd1: fcp@fea2f000 {
  2233. compatible = "renesas,fcpv";
  2234. reg = <0 0xfea2f000 0 0x200>;
  2235. clocks = <&cpg CPG_MOD 602>;
  2236. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2237. resets = <&cpg 602>;
  2238. iommus = <&ipmmu_vi0 9>;
  2239. };
  2240. fcpvd2: fcp@fea37000 {
  2241. compatible = "renesas,fcpv";
  2242. reg = <0 0xfea37000 0 0x200>;
  2243. clocks = <&cpg CPG_MOD 601>;
  2244. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2245. resets = <&cpg 601>;
  2246. iommus = <&ipmmu_vi0 10>;
  2247. };
  2248. fcpvi0: fcp@fe9af000 {
  2249. compatible = "renesas,fcpv";
  2250. reg = <0 0xfe9af000 0 0x200>;
  2251. clocks = <&cpg CPG_MOD 611>;
  2252. power-domains = <&sysc R8A774A1_PD_A3VC>;
  2253. resets = <&cpg 611>;
  2254. iommus = <&ipmmu_vc0 19>;
  2255. };
  2256. vspb: vsp@fe960000 {
  2257. compatible = "renesas,vsp2";
  2258. reg = <0 0xfe960000 0 0x8000>;
  2259. interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
  2260. clocks = <&cpg CPG_MOD 626>;
  2261. power-domains = <&sysc R8A774A1_PD_A3VC>;
  2262. resets = <&cpg 626>;
  2263. renesas,fcp = <&fcpvb0>;
  2264. };
  2265. vspd0: vsp@fea20000 {
  2266. compatible = "renesas,vsp2";
  2267. reg = <0 0xfea20000 0 0x5000>;
  2268. interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
  2269. clocks = <&cpg CPG_MOD 623>;
  2270. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2271. resets = <&cpg 623>;
  2272. renesas,fcp = <&fcpvd0>;
  2273. };
  2274. vspd1: vsp@fea28000 {
  2275. compatible = "renesas,vsp2";
  2276. reg = <0 0xfea28000 0 0x5000>;
  2277. interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
  2278. clocks = <&cpg CPG_MOD 622>;
  2279. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2280. resets = <&cpg 622>;
  2281. renesas,fcp = <&fcpvd1>;
  2282. };
  2283. vspd2: vsp@fea30000 {
  2284. compatible = "renesas,vsp2";
  2285. reg = <0 0xfea30000 0 0x5000>;
  2286. interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
  2287. clocks = <&cpg CPG_MOD 621>;
  2288. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2289. resets = <&cpg 621>;
  2290. renesas,fcp = <&fcpvd2>;
  2291. };
  2292. vspi0: vsp@fe9a0000 {
  2293. compatible = "renesas,vsp2";
  2294. reg = <0 0xfe9a0000 0 0x8000>;
  2295. interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
  2296. clocks = <&cpg CPG_MOD 631>;
  2297. power-domains = <&sysc R8A774A1_PD_A3VC>;
  2298. resets = <&cpg 631>;
  2299. renesas,fcp = <&fcpvi0>;
  2300. };
  2301. csi20: csi2@fea80000 {
  2302. compatible = "renesas,r8a774a1-csi2";
  2303. reg = <0 0xfea80000 0 0x10000>;
  2304. interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  2305. clocks = <&cpg CPG_MOD 714>;
  2306. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2307. resets = <&cpg 714>;
  2308. status = "disabled";
  2309. ports {
  2310. #address-cells = <1>;
  2311. #size-cells = <0>;
  2312. port@1 {
  2313. #address-cells = <1>;
  2314. #size-cells = <0>;
  2315. reg = <1>;
  2316. csi20vin0: endpoint@0 {
  2317. reg = <0>;
  2318. remote-endpoint = <&vin0csi20>;
  2319. };
  2320. csi20vin1: endpoint@1 {
  2321. reg = <1>;
  2322. remote-endpoint = <&vin1csi20>;
  2323. };
  2324. csi20vin2: endpoint@2 {
  2325. reg = <2>;
  2326. remote-endpoint = <&vin2csi20>;
  2327. };
  2328. csi20vin3: endpoint@3 {
  2329. reg = <3>;
  2330. remote-endpoint = <&vin3csi20>;
  2331. };
  2332. csi20vin4: endpoint@4 {
  2333. reg = <4>;
  2334. remote-endpoint = <&vin4csi20>;
  2335. };
  2336. csi20vin5: endpoint@5 {
  2337. reg = <5>;
  2338. remote-endpoint = <&vin5csi20>;
  2339. };
  2340. csi20vin6: endpoint@6 {
  2341. reg = <6>;
  2342. remote-endpoint = <&vin6csi20>;
  2343. };
  2344. csi20vin7: endpoint@7 {
  2345. reg = <7>;
  2346. remote-endpoint = <&vin7csi20>;
  2347. };
  2348. };
  2349. };
  2350. };
  2351. csi40: csi2@feaa0000 {
  2352. compatible = "renesas,r8a774a1-csi2";
  2353. reg = <0 0xfeaa0000 0 0x10000>;
  2354. interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
  2355. clocks = <&cpg CPG_MOD 716>;
  2356. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2357. resets = <&cpg 716>;
  2358. status = "disabled";
  2359. ports {
  2360. #address-cells = <1>;
  2361. #size-cells = <0>;
  2362. port@1 {
  2363. #address-cells = <1>;
  2364. #size-cells = <0>;
  2365. reg = <1>;
  2366. csi40vin0: endpoint@0 {
  2367. reg = <0>;
  2368. remote-endpoint = <&vin0csi40>;
  2369. };
  2370. csi40vin1: endpoint@1 {
  2371. reg = <1>;
  2372. remote-endpoint = <&vin1csi40>;
  2373. };
  2374. csi40vin2: endpoint@2 {
  2375. reg = <2>;
  2376. remote-endpoint = <&vin2csi40>;
  2377. };
  2378. csi40vin3: endpoint@3 {
  2379. reg = <3>;
  2380. remote-endpoint = <&vin3csi40>;
  2381. };
  2382. csi40vin4: endpoint@4 {
  2383. reg = <4>;
  2384. remote-endpoint = <&vin4csi40>;
  2385. };
  2386. csi40vin5: endpoint@5 {
  2387. reg = <5>;
  2388. remote-endpoint = <&vin5csi40>;
  2389. };
  2390. csi40vin6: endpoint@6 {
  2391. reg = <6>;
  2392. remote-endpoint = <&vin6csi40>;
  2393. };
  2394. csi40vin7: endpoint@7 {
  2395. reg = <7>;
  2396. remote-endpoint = <&vin7csi40>;
  2397. };
  2398. };
  2399. };
  2400. };
  2401. hdmi0: hdmi@fead0000 {
  2402. compatible = "renesas,r8a774a1-hdmi",
  2403. "renesas,rcar-gen3-hdmi";
  2404. reg = <0 0xfead0000 0 0x10000>;
  2405. interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
  2406. clocks = <&cpg CPG_MOD 729>,
  2407. <&cpg CPG_CORE R8A774A1_CLK_HDMI>;
  2408. clock-names = "iahb", "isfr";
  2409. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2410. resets = <&cpg 729>;
  2411. status = "disabled";
  2412. ports {
  2413. #address-cells = <1>;
  2414. #size-cells = <0>;
  2415. port@0 {
  2416. reg = <0>;
  2417. dw_hdmi0_in: endpoint {
  2418. remote-endpoint = <&du_out_hdmi0>;
  2419. };
  2420. };
  2421. port@1 {
  2422. reg = <1>;
  2423. };
  2424. port@2 {
  2425. /* HDMI sound */
  2426. reg = <2>;
  2427. };
  2428. };
  2429. };
  2430. du: display@feb00000 {
  2431. compatible = "renesas,du-r8a774a1";
  2432. reg = <0 0xfeb00000 0 0x70000>;
  2433. interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
  2434. <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
  2435. <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
  2436. clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
  2437. <&cpg CPG_MOD 722>;
  2438. clock-names = "du.0", "du.1", "du.2";
  2439. resets = <&cpg 724>, <&cpg 722>;
  2440. reset-names = "du.0", "du.2";
  2441. status = "disabled";
  2442. renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
  2443. ports {
  2444. #address-cells = <1>;
  2445. #size-cells = <0>;
  2446. port@0 {
  2447. reg = <0>;
  2448. du_out_rgb: endpoint {
  2449. };
  2450. };
  2451. port@1 {
  2452. reg = <1>;
  2453. du_out_hdmi0: endpoint {
  2454. remote-endpoint = <&dw_hdmi0_in>;
  2455. };
  2456. };
  2457. port@2 {
  2458. reg = <2>;
  2459. du_out_lvds0: endpoint {
  2460. remote-endpoint = <&lvds0_in>;
  2461. };
  2462. };
  2463. };
  2464. };
  2465. lvds0: lvds@feb90000 {
  2466. compatible = "renesas,r8a774a1-lvds";
  2467. reg = <0 0xfeb90000 0 0x14>;
  2468. clocks = <&cpg CPG_MOD 727>;
  2469. power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
  2470. resets = <&cpg 727>;
  2471. status = "disabled";
  2472. ports {
  2473. #address-cells = <1>;
  2474. #size-cells = <0>;
  2475. port@0 {
  2476. reg = <0>;
  2477. lvds0_in: endpoint {
  2478. remote-endpoint = <&du_out_lvds0>;
  2479. };
  2480. };
  2481. port@1 {
  2482. reg = <1>;
  2483. lvds0_out: endpoint {
  2484. };
  2485. };
  2486. };
  2487. };
  2488. prr: chipid@fff00044 {
  2489. compatible = "renesas,prr";
  2490. reg = <0 0xfff00044 0 4>;
  2491. };
  2492. };
  2493. thermal-zones {
  2494. sensor_thermal1: sensor-thermal1 {
  2495. polling-delay-passive = <250>;
  2496. polling-delay = <1000>;
  2497. thermal-sensors = <&tsc 0>;
  2498. sustainable-power = <3874>;
  2499. trips {
  2500. sensor1_crit: sensor1-crit {
  2501. temperature = <120000>;
  2502. hysteresis = <1000>;
  2503. type = "critical";
  2504. };
  2505. };
  2506. };
  2507. sensor_thermal2: sensor-thermal2 {
  2508. polling-delay-passive = <250>;
  2509. polling-delay = <1000>;
  2510. thermal-sensors = <&tsc 1>;
  2511. sustainable-power = <3874>;
  2512. trips {
  2513. sensor2_crit: sensor2-crit {
  2514. temperature = <120000>;
  2515. hysteresis = <1000>;
  2516. type = "critical";
  2517. };
  2518. };
  2519. };
  2520. sensor_thermal3: sensor-thermal3 {
  2521. polling-delay-passive = <250>;
  2522. polling-delay = <1000>;
  2523. thermal-sensors = <&tsc 2>;
  2524. sustainable-power = <3874>;
  2525. cooling-maps {
  2526. map0 {
  2527. trip = <&target>;
  2528. cooling-device = <&a57_0 0 2>;
  2529. contribution = <1024>;
  2530. };
  2531. map1 {
  2532. trip = <&target>;
  2533. cooling-device = <&a53_0 0 2>;
  2534. contribution = <1024>;
  2535. };
  2536. };
  2537. trips {
  2538. target: trip-point1 {
  2539. temperature = <100000>;
  2540. hysteresis = <1000>;
  2541. type = "passive";
  2542. };
  2543. sensor3_crit: sensor3-crit {
  2544. temperature = <120000>;
  2545. hysteresis = <1000>;
  2546. type = "critical";
  2547. };
  2548. };
  2549. };
  2550. };
  2551. timer {
  2552. compatible = "arm,armv8-timer";
  2553. interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  2554. <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  2555. <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  2556. <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
  2557. };
  2558. /* External USB clocks - can be overridden by the board */
  2559. usb3s0_clk: usb3s0 {
  2560. compatible = "fixed-clock";
  2561. #clock-cells = <0>;
  2562. clock-frequency = <0>;
  2563. };
  2564. usb_extal_clk: usb_extal {
  2565. compatible = "fixed-clock";
  2566. #clock-cells = <0>;
  2567. clock-frequency = <0>;
  2568. };
  2569. };