qcom-ipq4019.dtsi 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019 Sartura Ltd.
  4. *
  5. * Author: Robert Marko <robert.marko@sartura.hr>
  6. */
  7. /dts-v1/;
  8. #include "skeleton.dtsi"
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
  11. #include <dt-bindings/clock/qcom,ipq4019-gcc.h>
  12. #include <dt-bindings/reset/qcom,ipq4019-reset.h>
  13. / {
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. model = "Qualcomm Technologies, Inc. IPQ4019";
  17. compatible = "qcom,ipq4019";
  18. aliases {
  19. serial0 = &blsp1_uart1;
  20. };
  21. reserved-memory {
  22. #address-cells = <0x1>;
  23. #size-cells = <0x1>;
  24. ranges;
  25. smem_mem: smem_region: smem@87e00000 {
  26. reg = <0x87e00000 0x080000>;
  27. no-map;
  28. };
  29. tz@87e80000 {
  30. reg = <0x87e80000 0x180000>;
  31. no-map;
  32. };
  33. };
  34. smem {
  35. compatible = "qcom,smem";
  36. memory-region = <&smem_mem>;
  37. };
  38. soc: soc {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ranges;
  42. compatible = "simple-bus";
  43. gcc: clock-controller@1800000 {
  44. compatible = "qcom,gcc-ipq4019";
  45. reg = <0x1800000 0x60000>;
  46. #clock-cells = <1>;
  47. #reset-cells = <1>;
  48. u-boot,dm-pre-reloc;
  49. };
  50. reset: gcc-reset@1800000 {
  51. compatible = "qcom,gcc-reset-ipq4019";
  52. reg = <0x1800000 0x60000>;
  53. #clock-cells = <1>;
  54. #reset-cells = <1>;
  55. u-boot,dm-pre-reloc;
  56. };
  57. pinctrl: qcom,tlmm@1000000 {
  58. compatible = "qcom,tlmm-ipq4019";
  59. reg = <0x1000000 0x300000>;
  60. u-boot,dm-pre-reloc;
  61. };
  62. blsp1_uart1: serial@78af000 {
  63. compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  64. reg = <0x78af000 0x200>;
  65. clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
  66. bit-rate = <0xFF>;
  67. status = "disabled";
  68. u-boot,dm-pre-reloc;
  69. };
  70. soc_gpios: pinctrl@1000000 {
  71. compatible = "qcom,ipq4019-pinctrl";
  72. reg = <0x1000000 0x300000>;
  73. gpio-controller;
  74. gpio-count = <100>;
  75. gpio-bank-name="soc";
  76. #gpio-cells = <2>;
  77. };
  78. usb3_ss_phy: ssphy@9a000 {
  79. compatible = "qcom,usb-ss-ipq4019-phy";
  80. #phy-cells = <0>;
  81. reg = <0x9a000 0x800>;
  82. reg-names = "phy_base";
  83. resets = <&reset USB3_UNIPHY_PHY_ARES>;
  84. reset-names = "por_rst";
  85. status = "disabled";
  86. };
  87. usb3_hs_phy: hsphy@a6000 {
  88. compatible = "qcom,usb-hs-ipq4019-phy";
  89. #phy-cells = <0>;
  90. reg = <0xa6000 0x40>;
  91. reg-names = "phy_base";
  92. resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
  93. reset-names = "por_rst", "srif_rst";
  94. status = "disabled";
  95. };
  96. usb3: usb3@8af8800 {
  97. compatible = "qcom,dwc3";
  98. reg = <0x8af8800 0x100>;
  99. #address-cells = <1>;
  100. #size-cells = <1>;
  101. clocks = <&gcc GCC_USB3_MASTER_CLK>,
  102. <&gcc GCC_USB3_SLEEP_CLK>,
  103. <&gcc GCC_USB3_MOCK_UTMI_CLK>;
  104. clock-names = "master", "sleep", "mock_utmi";
  105. ranges;
  106. status = "disabled";
  107. dwc3@8a00000 {
  108. compatible = "snps,dwc3";
  109. reg = <0x8a00000 0xf8000>;
  110. phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
  111. phy-names = "usb2-phy", "usb3-phy";
  112. dr_mode = "host";
  113. maximum-speed = "super-speed";
  114. snps,dis_u2_susphy_quirk;
  115. };
  116. };
  117. usb2_hs_phy: hsphy@a8000 {
  118. compatible = "qcom,usb-hs-ipq4019-phy";
  119. #phy-cells = <0>;
  120. reg = <0xa8000 0x40>;
  121. reg-names = "phy_base";
  122. resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
  123. reset-names = "por_rst", "srif_rst";
  124. status = "disabled";
  125. };
  126. usb2: usb2@60f8800 {
  127. compatible = "qcom,dwc3";
  128. reg = <0x60f8800 0x100>;
  129. #address-cells = <1>;
  130. #size-cells = <1>;
  131. clocks = <&gcc GCC_USB2_MASTER_CLK>,
  132. <&gcc GCC_USB2_SLEEP_CLK>,
  133. <&gcc GCC_USB2_MOCK_UTMI_CLK>;
  134. clock-names = "master", "sleep", "mock_utmi";
  135. ranges;
  136. status = "disabled";
  137. dwc3@6000000 {
  138. compatible = "snps,dwc3";
  139. reg = <0x6000000 0xf8000>;
  140. phys = <&usb2_hs_phy>;
  141. phy-names = "usb2-phy";
  142. dr_mode = "host";
  143. maximum-speed = "high-speed";
  144. snps,dis_u2_susphy_quirk;
  145. };
  146. };
  147. };
  148. };