k3-j721e-main.dtsi 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for J721E SoC Family Main Domain peripherals
  4. *
  5. * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. &cbass_main {
  8. msmc_ram: sram@70000000 {
  9. compatible = "mmio-sram";
  10. reg = <0x0 0x70000000 0x0 0x800000>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. ranges = <0x0 0x0 0x70000000 0x800000>;
  14. atf-sram@0 {
  15. reg = <0x0 0x20000>;
  16. };
  17. };
  18. gic500: interrupt-controller@1800000 {
  19. compatible = "arm,gic-v3";
  20. #address-cells = <2>;
  21. #size-cells = <2>;
  22. ranges;
  23. #interrupt-cells = <3>;
  24. interrupt-controller;
  25. reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
  26. <0x00 0x01900000 0x00 0x100000>; /* GICR */
  27. /* vcpumntirq: virtual CPU interface maintenance interrupt */
  28. interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  29. gic_its: gic-its@18200000 {
  30. compatible = "arm,gic-v3-its";
  31. reg = <0x00 0x01820000 0x00 0x10000>;
  32. socionext,synquacer-pre-its = <0x1000000 0x400000>;
  33. msi-controller;
  34. #msi-cells = <1>;
  35. };
  36. };
  37. smmu0: smmu@36600000 {
  38. compatible = "arm,smmu-v3";
  39. reg = <0x0 0x36600000 0x0 0x100000>;
  40. interrupt-parent = <&gic500>;
  41. interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
  42. <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
  43. interrupt-names = "eventq", "gerror";
  44. #iommu-cells = <1>;
  45. };
  46. secure_proxy_main: mailbox@32c00000 {
  47. compatible = "ti,am654-secure-proxy";
  48. #mbox-cells = <1>;
  49. reg-names = "target_data", "rt", "scfg";
  50. reg = <0x00 0x32c00000 0x00 0x100000>,
  51. <0x00 0x32400000 0x00 0x100000>,
  52. <0x00 0x32800000 0x00 0x100000>;
  53. interrupt-names = "rx_011";
  54. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  55. };
  56. main_pmx0: pinmux@11c000 {
  57. compatible = "pinctrl-single";
  58. /* Proxy 0 addressing */
  59. reg = <0x0 0x11c000 0x0 0x2b4>;
  60. #pinctrl-cells = <1>;
  61. pinctrl-single,register-width = <32>;
  62. pinctrl-single,function-mask = <0xffffffff>;
  63. };
  64. main_uart0: serial@2800000 {
  65. compatible = "ti,j721e-uart", "ti,am654-uart";
  66. reg = <0x00 0x02800000 0x00 0x100>;
  67. reg-shift = <2>;
  68. reg-io-width = <4>;
  69. interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  70. clock-frequency = <48000000>;
  71. current-speed = <115200>;
  72. power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
  73. clocks = <&k3_clks 146 0>;
  74. clock-names = "fclk";
  75. };
  76. main_uart1: serial@2810000 {
  77. compatible = "ti,j721e-uart", "ti,am654-uart";
  78. reg = <0x00 0x02810000 0x00 0x100>;
  79. reg-shift = <2>;
  80. reg-io-width = <4>;
  81. interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  82. clock-frequency = <48000000>;
  83. current-speed = <115200>;
  84. power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
  85. clocks = <&k3_clks 278 0>;
  86. clock-names = "fclk";
  87. };
  88. main_uart2: serial@2820000 {
  89. compatible = "ti,j721e-uart", "ti,am654-uart";
  90. reg = <0x00 0x02820000 0x00 0x100>;
  91. reg-shift = <2>;
  92. reg-io-width = <4>;
  93. interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  94. clock-frequency = <48000000>;
  95. current-speed = <115200>;
  96. power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
  97. clocks = <&k3_clks 279 0>;
  98. clock-names = "fclk";
  99. };
  100. main_uart3: serial@2830000 {
  101. compatible = "ti,j721e-uart", "ti,am654-uart";
  102. reg = <0x00 0x02830000 0x00 0x100>;
  103. reg-shift = <2>;
  104. reg-io-width = <4>;
  105. interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
  106. clock-frequency = <48000000>;
  107. current-speed = <115200>;
  108. power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
  109. clocks = <&k3_clks 280 0>;
  110. clock-names = "fclk";
  111. };
  112. main_uart4: serial@2840000 {
  113. compatible = "ti,j721e-uart", "ti,am654-uart";
  114. reg = <0x00 0x02840000 0x00 0x100>;
  115. reg-shift = <2>;
  116. reg-io-width = <4>;
  117. interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  118. clock-frequency = <48000000>;
  119. current-speed = <115200>;
  120. power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
  121. clocks = <&k3_clks 281 0>;
  122. clock-names = "fclk";
  123. };
  124. main_uart5: serial@2850000 {
  125. compatible = "ti,j721e-uart", "ti,am654-uart";
  126. reg = <0x00 0x02850000 0x00 0x100>;
  127. reg-shift = <2>;
  128. reg-io-width = <4>;
  129. interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
  130. clock-frequency = <48000000>;
  131. current-speed = <115200>;
  132. power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
  133. clocks = <&k3_clks 282 0>;
  134. clock-names = "fclk";
  135. };
  136. main_uart6: serial@2860000 {
  137. compatible = "ti,j721e-uart", "ti,am654-uart";
  138. reg = <0x00 0x02860000 0x00 0x100>;
  139. reg-shift = <2>;
  140. reg-io-width = <4>;
  141. interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
  142. clock-frequency = <48000000>;
  143. current-speed = <115200>;
  144. power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
  145. clocks = <&k3_clks 283 0>;
  146. clock-names = "fclk";
  147. };
  148. main_uart7: serial@2870000 {
  149. compatible = "ti,j721e-uart", "ti,am654-uart";
  150. reg = <0x00 0x02870000 0x00 0x100>;
  151. reg-shift = <2>;
  152. reg-io-width = <4>;
  153. interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
  154. clock-frequency = <48000000>;
  155. current-speed = <115200>;
  156. power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
  157. clocks = <&k3_clks 284 0>;
  158. clock-names = "fclk";
  159. };
  160. main_uart8: serial@2880000 {
  161. compatible = "ti,j721e-uart", "ti,am654-uart";
  162. reg = <0x00 0x02880000 0x00 0x100>;
  163. reg-shift = <2>;
  164. reg-io-width = <4>;
  165. interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
  166. clock-frequency = <48000000>;
  167. current-speed = <115200>;
  168. power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
  169. clocks = <&k3_clks 285 0>;
  170. clock-names = "fclk";
  171. };
  172. main_uart9: serial@2890000 {
  173. compatible = "ti,j721e-uart", "ti,am654-uart";
  174. reg = <0x00 0x02890000 0x00 0x100>;
  175. reg-shift = <2>;
  176. reg-io-width = <4>;
  177. interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
  178. clock-frequency = <48000000>;
  179. current-speed = <115200>;
  180. power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
  181. clocks = <&k3_clks 286 0>;
  182. clock-names = "fclk";
  183. };
  184. main_gpio0: gpio@600000 {
  185. compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  186. reg = <0x0 0x00600000 0x0 0x100>;
  187. gpio-controller;
  188. #gpio-cells = <2>;
  189. interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
  190. <105 1 IRQ_TYPE_EDGE_RISING>,
  191. <105 2 IRQ_TYPE_EDGE_RISING>,
  192. <105 3 IRQ_TYPE_EDGE_RISING>,
  193. <105 4 IRQ_TYPE_EDGE_RISING>,
  194. <105 5 IRQ_TYPE_EDGE_RISING>,
  195. <105 6 IRQ_TYPE_EDGE_RISING>,
  196. <105 7 IRQ_TYPE_EDGE_RISING>;
  197. interrupt-controller;
  198. #interrupt-cells = <2>;
  199. ti,ngpio = <128>;
  200. ti,davinci-gpio-unbanked = <0>;
  201. power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
  202. clocks = <&k3_clks 105 0>;
  203. clock-names = "gpio";
  204. };
  205. main_sdhci0: sdhci@4f80000 {
  206. compatible = "ti,j721e-sdhci-8bit";
  207. reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
  208. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  209. power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
  210. clock-names = "clk_xin", "clk_ahb";
  211. clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
  212. assigned-clocks = <&k3_clks 91 1>;
  213. assigned-clock-parents = <&k3_clks 91 2>;
  214. bus-width = <8>;
  215. ti,trm-icp = <0x8>;
  216. dma-coherent;
  217. mmc-ddr-1_8v;
  218. ti,otap-del-sel-legacy = <0x0>;
  219. ti,otap-del-sel-mmc-hs = <0x0>;
  220. ti,otap-del-sel-ddr52 = <0x5>;
  221. ti,otap-del-sel-hs200 = <0x6>;
  222. ti,otap-del-sel-hs400 = <0x0>;
  223. };
  224. main_sdhci1: sdhci@4fb0000 {
  225. compatible = "ti,j721e-sdhci-4bit";
  226. reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
  227. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  228. power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
  229. clock-names = "clk_xin", "clk_ahb";
  230. clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
  231. assigned-clocks = <&k3_clks 92 0>;
  232. assigned-clock-parents = <&k3_clks 92 1>;
  233. ti,otap-del-sel-legacy = <0x0>;
  234. ti,otap-del-sel-sd-hs = <0xf>;
  235. ti,otap-del-sel-sdr12 = <0xf>;
  236. ti,otap-del-sel-sdr25 = <0xf>;
  237. ti,otap-del-sel-sdr50 = <0xc>;
  238. ti,otap-del-sel-sdr104 = <0x5>;
  239. ti,otap-del-sel-ddr50 = <0xc>;
  240. ti,trm-icp = <0x8>;
  241. dma-coherent;
  242. };
  243. main_r5fss0: r5fss@5c00000 {
  244. compatible = "ti,j721e-r5fss";
  245. lockstep-mode = <0>;
  246. #address-cells = <1>;
  247. #size-cells = <1>;
  248. ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
  249. <0x5d00000 0x00 0x5d00000 0x20000>;
  250. power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
  251. main_r5fss0_core0: r5f@5c00000 {
  252. compatible = "ti,j721e-r5f";
  253. reg = <0x5c00000 0x00008000>,
  254. <0x5c10000 0x00008000>;
  255. reg-names = "atcm", "btcm";
  256. ti,sci = <&dmsc>;
  257. ti,sci-dev-id = <245>;
  258. ti,sci-proc-ids = <0x06 0xFF>;
  259. resets = <&k3_reset 245 1>;
  260. atcm-enable = <1>;
  261. btcm-enable = <1>;
  262. loczrama = <1>;
  263. };
  264. main_r5fss0_core1: r5f@5d00000 {
  265. compatible = "ti,j721e-r5f";
  266. reg = <0x5d00000 0x00008000>,
  267. <0x5d10000 0x00008000>;
  268. reg-names = "atcm", "btcm";
  269. ti,sci = <&dmsc>;
  270. ti,sci-dev-id = <246>;
  271. ti,sci-proc-ids = <0x07 0xFF>;
  272. resets = <&k3_reset 246 1>;
  273. atcm-enable = <1>;
  274. btcm-enable = <1>;
  275. loczrama = <1>;
  276. };
  277. };
  278. main_r5fss1: r5fss@5e00000 {
  279. compatible = "ti,j721e-r5fss";
  280. lockstep-mode = <0>;
  281. #address-cells = <1>;
  282. #size-cells = <1>;
  283. ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
  284. <0x5f00000 0x00 0x5f00000 0x20000>;
  285. power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
  286. main_r5fss1_core0: r5f@5e00000 {
  287. compatible = "ti,j721e-r5f";
  288. reg = <0x5e00000 0x00008000>,
  289. <0x5e10000 0x00008000>;
  290. reg-names = "atcm", "btcm";
  291. ti,sci = <&dmsc>;
  292. ti,sci-dev-id = <247>;
  293. ti,sci-proc-ids = <0x08 0xFF>;
  294. resets = <&k3_reset 247 1>;
  295. atcm-enable = <1>;
  296. btcm-enable = <1>;
  297. loczrama = <1>;
  298. };
  299. main_r5fss1_core1: r5f@5f00000 {
  300. compatible = "ti,j721e-r5f";
  301. reg = <0x5f00000 0x00008000>,
  302. <0x5f10000 0x00008000>;
  303. reg-names = "atcm", "btcm";
  304. ti,sci = <&dmsc>;
  305. ti,sci-dev-id = <248>;
  306. ti,sci-proc-ids = <0x09 0xFF>;
  307. resets = <&k3_reset 248 1>;
  308. atcm-enable = <1>;
  309. btcm-enable = <1>;
  310. loczrama = <1>;
  311. };
  312. };
  313. c66_0: dsp@4d80800000 {
  314. compatible = "ti,j721e-c66-dsp";
  315. reg = <0x4d 0x80800000 0x00 0x00048000>,
  316. <0x4d 0x80e00000 0x00 0x00008000>,
  317. <0x4d 0x80f00000 0x00 0x00008000>;
  318. reg-names = "l2sram", "l1pram", "l1dram";
  319. ti,sci = <&dmsc>;
  320. ti,sci-dev-id = <142>;
  321. ti,sci-proc-ids = <0x03 0xFF>;
  322. resets = <&k3_reset 142 1>;
  323. };
  324. c66_1: dsp@4d81800000 {
  325. compatible = "ti,j721e-c66-dsp";
  326. reg = <0x4d 0x81800000 0x00 0x00048000>,
  327. <0x4d 0x81e00000 0x00 0x00008000>,
  328. <0x4d 0x81f00000 0x00 0x00008000>;
  329. reg-names = "l2sram", "l1pram", "l1dram";
  330. ti,sci = <&dmsc>;
  331. ti,sci-dev-id = <143>;
  332. ti,sci-proc-ids = <0x04 0xFF>;
  333. resets = <&k3_reset 143 1>;
  334. };
  335. c71_0: dsp@64800000 {
  336. compatible = "ti,j721e-c71-dsp";
  337. reg = <0x00 0x64800000 0x00 0x00080000>,
  338. <0x00 0x64e00000 0x00 0x0000c000>;
  339. reg-names = "l2sram", "l1dram";
  340. ti,sci = <&dmsc>;
  341. ti,sci-dev-id = <15>;
  342. ti,sci-proc-ids = <0x30 0xFF>;
  343. resets = <&k3_reset 15 1>;
  344. };
  345. usbss0: cdns_usb@4104000 {
  346. compatible = "ti,j721e-usb";
  347. reg = <0x00 0x4104000 0x00 0x100>;
  348. dma-coherent;
  349. power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
  350. clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
  351. clock-names = "usb2_refclk", "lpm_clk";
  352. assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
  353. assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
  354. #address-cells = <2>;
  355. #size-cells = <2>;
  356. ranges;
  357. phy@4108000 {
  358. compatible = "ti,j721e-usb2-phy";
  359. reg = <0x00 0x4108000 0x00 0x400>;
  360. };
  361. usb0: usb@6000000 {
  362. compatible = "cdns,usb3";
  363. reg = <0x00 0x6000000 0x00 0x10000>,
  364. <0x00 0x6010000 0x00 0x10000>,
  365. <0x00 0x6020000 0x00 0x10000>;
  366. reg-names = "otg", "xhci", "dev";
  367. interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
  368. <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
  369. <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
  370. interrupt-names = "host",
  371. "peripheral",
  372. "otg";
  373. maximum-speed = "super-speed";
  374. dr_mode = "otg";
  375. };
  376. };
  377. usbss1: cdns_usb@4114000 {
  378. compatible = "ti,j721e-usb";
  379. reg = <0x00 0x4114000 0x00 0x100>;
  380. dma-coherent;
  381. power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
  382. clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
  383. clock-names = "usb2_refclk", "lpm_clk";
  384. assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
  385. assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
  386. #address-cells = <2>;
  387. #size-cells = <2>;
  388. ranges;
  389. phy@4118000 {
  390. compatible = "ti,j721e-usb2-phy";
  391. reg = <0x00 0x4118000 0x00 0x400>;
  392. };
  393. usb1: usb@6400000 {
  394. compatible = "cdns,usb3";
  395. reg = <0x00 0x6400000 0x00 0x10000>,
  396. <0x00 0x6410000 0x00 0x10000>,
  397. <0x00 0x6420000 0x00 0x10000>;
  398. reg-names = "otg", "xhci", "dev";
  399. interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
  400. <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
  401. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
  402. interrupt-names = "host",
  403. "peripheral",
  404. "otg";
  405. maximum-speed = "super-speed";
  406. dr_mode = "otg";
  407. };
  408. };
  409. ufs_wrapper: ufs-wrapper@4e80000 {
  410. compatible = "ti,j721e-ufs";
  411. reg = <0x0 0x4e80000 0x0 0x100>;
  412. power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
  413. clocks = <&k3_clks 277 1>;
  414. assigned-clocks = <&k3_clks 277 1>;
  415. assigned-clock-parents = <&k3_clks 277 4>;
  416. ranges;
  417. #address-cells = <2>;
  418. #size-cells = <2>;
  419. ufs@4e84000 {
  420. compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
  421. reg = <0x0 0x4e84000 0x0 0x10000>;
  422. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  423. freq-table-hz = <0 0>, <0 0>;
  424. clocks = <&k3_clks 277 0>, <&k3_clks 277 1>;
  425. clock-names = "core_clk", "phy_clk";
  426. assigned-clocks = <&k3_clks 277 1>;
  427. assigned-clock-parents = <&k3_clks 277 4>;
  428. dma-coherent;
  429. };
  430. };
  431. main_i2c0: i2c@2000000 {
  432. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  433. reg = <0x0 0x2000000 0x0 0x100>;
  434. interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  435. #address-cells = <1>;
  436. #size-cells = <0>;
  437. clock-names = "fck";
  438. clocks = <&k3_clks 187 0>;
  439. power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
  440. };
  441. main_i2c1: i2c@2010000 {
  442. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  443. reg = <0x0 0x2010000 0x0 0x100>;
  444. interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
  445. #address-cells = <1>;
  446. #size-cells = <0>;
  447. clock-names = "fck";
  448. clocks = <&k3_clks 188 0>;
  449. power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
  450. };
  451. main_i2c2: i2c@2020000 {
  452. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  453. reg = <0x0 0x2020000 0x0 0x100>;
  454. interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
  455. #address-cells = <1>;
  456. #size-cells = <0>;
  457. clock-names = "fck";
  458. clocks = <&k3_clks 189 0>;
  459. power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
  460. };
  461. main_i2c3: i2c@2030000 {
  462. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  463. reg = <0x0 0x2030000 0x0 0x100>;
  464. interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
  465. #address-cells = <1>;
  466. #size-cells = <0>;
  467. clock-names = "fck";
  468. clocks = <&k3_clks 190 0>;
  469. power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
  470. };
  471. main_i2c4: i2c@2040000 {
  472. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  473. reg = <0x0 0x2040000 0x0 0x100>;
  474. interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
  475. #address-cells = <1>;
  476. #size-cells = <0>;
  477. clock-names = "fck";
  478. clocks = <&k3_clks 191 0>;
  479. power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
  480. };
  481. main_i2c5: i2c@2050000 {
  482. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  483. reg = <0x0 0x2050000 0x0 0x100>;
  484. interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
  485. #address-cells = <1>;
  486. #size-cells = <0>;
  487. clock-names = "fck";
  488. clocks = <&k3_clks 192 0>;
  489. power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
  490. };
  491. main_i2c6: i2c@2060000 {
  492. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  493. reg = <0x0 0x2060000 0x0 0x100>;
  494. interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  495. #address-cells = <1>;
  496. #size-cells = <0>;
  497. clock-names = "fck";
  498. clocks = <&k3_clks 193 0>;
  499. power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
  500. };
  501. watchdog0: watchdog@2200000 {
  502. compatible = "ti,j7-rti-wdt";
  503. reg = <0x0 0x2200000 0x0 0x100>;
  504. clocks = <&k3_clks 252 1>;
  505. power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
  506. assigned-clocks = <&k3_clks 252 1>;
  507. assigned-clock-parents = <&k3_clks 252 5>;
  508. };
  509. watchdog1: watchdog@2210000 {
  510. compatible = "ti,j7-rti-wdt";
  511. reg = <0x0 0x2210000 0x0 0x100>;
  512. clocks = <&k3_clks 253 1>;
  513. power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
  514. assigned-clocks = <&k3_clks 253 1>;
  515. assigned-clock-parents = <&k3_clks 253 5>;
  516. };
  517. };