k3-j7200-r5-common-proc-board.dts 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  4. */
  5. /dts-v1/;
  6. #include "k3-j7200-som-p0.dtsi"
  7. #include "k3-j7200-ddr-evm-lp4-1600.dtsi"
  8. #include "k3-j721e-ddr.dtsi"
  9. / {
  10. aliases {
  11. remoteproc0 = &sysctrler;
  12. remoteproc1 = &a72_0;
  13. };
  14. chosen {
  15. stdout-path = &main_uart0;
  16. tick-timer = &timer1;
  17. firmware-loader = &fs_loader0;
  18. };
  19. fs_loader0: fs_loader@0 {
  20. u-boot,dm-pre-reloc;
  21. compatible = "u-boot,fs-loader";
  22. };
  23. a72_0: a72@0 {
  24. compatible = "ti,am654-rproc";
  25. reg = <0x0 0x00a90000 0x0 0x10>;
  26. power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
  27. <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
  28. resets = <&k3_reset 202 0>;
  29. assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
  30. assigned-clock-rates = <2000000000>, <200000000>;
  31. ti,sci = <&dmsc>;
  32. ti,sci-proc-id = <32>;
  33. ti,sci-host-id = <10>;
  34. u-boot,dm-spl;
  35. };
  36. clk_200mhz: dummy_clock_200mhz {
  37. compatible = "fixed-clock";
  38. #clock-cells = <0>;
  39. clock-frequency = <200000000>;
  40. u-boot,dm-spl;
  41. };
  42. clk_19_2mhz: dummy_clock_19_2mhz {
  43. compatible = "fixed-clock";
  44. #clock-cells = <0>;
  45. clock-frequency = <19200000>;
  46. u-boot,dm-spl;
  47. };
  48. };
  49. &memorycontroller {
  50. power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
  51. <&k3_pds 90 TI_SCI_PD_SHARED>;
  52. clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
  53. };
  54. &cbass_mcu_wakeup {
  55. mcu_secproxy: secproxy@2a380000 {
  56. u-boot,dm-spl;
  57. compatible = "ti,am654-secure-proxy";
  58. reg = <0x0 0x2a380000 0x0 0x80000>,
  59. <0x0 0x2a400000 0x0 0x80000>,
  60. <0x0 0x2a480000 0x0 0x80000>;
  61. reg-names = "rt", "scfg", "target_data";
  62. #mbox-cells = <1>;
  63. };
  64. sysctrler: sysctrler {
  65. u-boot,dm-spl;
  66. compatible = "ti,am654-system-controller";
  67. mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
  68. mbox-names = "tx", "rx";
  69. };
  70. };
  71. &dmsc {
  72. mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
  73. mbox-names = "tx", "rx", "notify";
  74. ti,host-id = <4>;
  75. ti,secure-host;
  76. };
  77. &wkup_pmx0 {
  78. u-boot,dm-spl;
  79. wkup_uart0_pins_default: wkup_uart0_pins_default {
  80. u-boot,dm-spl;
  81. pinctrl-single,pins = <
  82. J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
  83. J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
  84. >;
  85. };
  86. mcu_uart0_pins_default: mcu_uart0_pins_default {
  87. u-boot,dm-spl;
  88. pinctrl-single,pins = <
  89. J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
  90. J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
  91. J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */
  92. J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */
  93. >;
  94. };
  95. wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  96. pinctrl-single,pins = <
  97. J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
  98. J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
  99. >;
  100. };
  101. mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
  102. pinctrl-single,pins = <
  103. J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
  104. J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
  105. J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
  106. J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
  107. J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
  108. J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
  109. J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
  110. J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
  111. J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
  112. J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
  113. J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
  114. J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
  115. J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
  116. J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
  117. >;
  118. };
  119. wkup_gpio_pins_default: wkup-gpio-pins-default {
  120. pinctrl-single,pins = <
  121. J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
  122. >;
  123. };
  124. };
  125. &main_pmx0 {
  126. u-boot,dm-spl;
  127. main_uart0_pins_default: main_uart0_pins_default {
  128. u-boot,dm-spl;
  129. pinctrl-single,pins = <
  130. J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
  131. J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
  132. J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
  133. J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
  134. >;
  135. };
  136. main_i2c0_pins_default: main-i2c0-pins-default {
  137. u-boot,dm-spl;
  138. pinctrl-single,pins = <
  139. J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
  140. J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
  141. >;
  142. };
  143. main_usbss0_pins_default: main_usbss0_pins_default {
  144. pinctrl-single,pins = <
  145. J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
  146. >;
  147. };
  148. };
  149. &wkup_uart0 {
  150. u-boot,dm-spl;
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&wkup_uart0_pins_default>;
  153. status = "okay";
  154. };
  155. &mcu_uart0 {
  156. /delete-property/ power-domains;
  157. /delete-property/ clocks;
  158. /delete-property/ clock-names;
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&mcu_uart0_pins_default>;
  161. status = "okay";
  162. clock-frequency = <96000000>;
  163. };
  164. &main_uart0 {
  165. status = "okay";
  166. power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&main_uart0_pins_default>;
  169. status = "okay";
  170. };
  171. &main_sdhci0 {
  172. /delete-property/ power-domains;
  173. /delete-property/ assigned-clocks;
  174. /delete-property/ assigned-clock-parents;
  175. clock-names = "clk_xin";
  176. clocks = <&clk_200mhz>;
  177. ti,driver-strength-ohm = <50>;
  178. non-removable;
  179. bus-width = <8>;
  180. };
  181. &main_sdhci1 {
  182. /delete-property/ power-domains;
  183. /delete-property/ assigned-clocks;
  184. /delete-property/ assigned-clock-parents;
  185. clock-names = "clk_xin";
  186. clocks = <&clk_200mhz>;
  187. ti,driver-strength-ohm = <50>;
  188. };
  189. &main_i2c0 {
  190. pinctrl-names = "default";
  191. pinctrl-0 = <&main_i2c0_pins_default>;
  192. clock-frequency = <400000>;
  193. exp1: gpio@20 {
  194. compatible = "ti,tca6416";
  195. reg = <0x20>;
  196. gpio-controller;
  197. #gpio-cells = <2>;
  198. };
  199. exp2: gpio@22 {
  200. compatible = "ti,tca6424";
  201. reg = <0x22>;
  202. gpio-controller;
  203. #gpio-cells = <2>;
  204. };
  205. };
  206. &usbss0 {
  207. pinctrl-names = "default";
  208. pinctrl-0 = <&main_usbss0_pins_default>;
  209. ti,vbus-divider;
  210. ti,usb2-only;
  211. };
  212. &usb0 {
  213. dr_mode = "otg";
  214. maximum-speed = "high-speed";
  215. };
  216. &hbmc {
  217. status = "okay";
  218. pinctrl-names = "default";
  219. pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
  220. reg = <0x0 0x47040000 0x0 0x100>,
  221. <0x0 0x50000000 0x0 0x8000000>;
  222. ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
  223. <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
  224. flash@0,0 {
  225. compatible = "cypress,hyperflash", "cfi-flash";
  226. reg = <0x0 0x0 0x4000000>;
  227. };
  228. };
  229. #include "k3-j7200-common-proc-board-u-boot.dtsi"