k3-j7200-mcu-wakeup.dtsi 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
  4. *
  5. * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  6. */
  7. &cbass_mcu_wakeup {
  8. dmsc: dmsc@44083000 {
  9. compatible = "ti,k2g-sci";
  10. ti,host-id = <12>;
  11. mbox-names = "rx", "tx";
  12. mboxes= <&secure_proxy_main 11>,
  13. <&secure_proxy_main 13>;
  14. reg-names = "debug_messages";
  15. reg = <0x00 0x44083000 0x0 0x1000>;
  16. k3_pds: power-controller {
  17. compatible = "ti,sci-pm-domain";
  18. #power-domain-cells = <2>;
  19. };
  20. k3_clks: clocks {
  21. compatible = "ti,k2g-sci-clk";
  22. #clock-cells = <2>;
  23. };
  24. k3_reset: reset-controller {
  25. compatible = "ti,sci-reset";
  26. #reset-cells = <2>;
  27. };
  28. };
  29. chipid: chipid@43000014 {
  30. compatible = "ti,am654-chipid";
  31. reg = <0x0 0x43000014 0x0 0x4>;
  32. };
  33. wkup_pmx0: pinmux@4301c000 {
  34. compatible = "pinctrl-single";
  35. /* Proxy 0 addressing */
  36. reg = <0x00 0x4301c000 0x00 0x178>;
  37. #pinctrl-cells = <1>;
  38. pinctrl-single,register-width = <32>;
  39. pinctrl-single,function-mask = <0xffffffff>;
  40. };
  41. mcu_ram: sram@41c00000 {
  42. compatible = "mmio-sram";
  43. reg = <0x00 0x41c00000 0x00 0x100000>;
  44. ranges = <0x0 0x00 0x41c00000 0x100000>;
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. };
  48. wkup_uart0: serial@42300000 {
  49. compatible = "ti,j721e-uart", "ti,am654-uart";
  50. reg = <0x00 0x42300000 0x00 0x100>;
  51. reg-shift = <2>;
  52. reg-io-width = <4>;
  53. interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
  54. clock-frequency = <48000000>;
  55. current-speed = <115200>;
  56. power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
  57. clocks = <&k3_clks 287 2>;
  58. clock-names = "fclk";
  59. };
  60. wkup_i2c0: i2c@42120000 {
  61. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  62. reg = <0x0 0x42120000 0x0 0x100>;
  63. interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
  64. #address-cells = <1>;
  65. #size-cells = <0>;
  66. clock-names = "fck";
  67. clocks = <&k3_clks 197 1>;
  68. power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
  69. };
  70. mcu_uart0: serial@40a00000 {
  71. compatible = "ti,j721e-uart", "ti,am654-uart";
  72. reg = <0x00 0x40a00000 0x00 0x100>;
  73. reg-shift = <2>;
  74. reg-io-width = <4>;
  75. interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
  76. clock-frequency = <96000000>;
  77. current-speed = <115200>;
  78. power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  79. clocks = <&k3_clks 149 2>;
  80. clock-names = "fclk";
  81. };
  82. fss: system-controller@47000000 {
  83. compatible = "syscon", "simple-mfd";
  84. reg = <0x0 0x47000000 0x0 0x100>;
  85. #address-cells = <2>;
  86. #size-cells = <2>;
  87. ranges;
  88. hbmc_mux: hbmc-mux {
  89. compatible = "mmio-mux";
  90. #mux-control-cells = <1>;
  91. mux-reg-masks = <0x4 0x2>; /* HBMC select */
  92. };
  93. hbmc: hyperbus@47034000 {
  94. compatible = "ti,am654-hbmc";
  95. reg = <0x0 0x47034000 0x0 0x100>,
  96. <0x5 0x00000000 0x1 0x0000000>;
  97. power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
  98. #address-cells = <2>;
  99. #size-cells = <1>;
  100. mux-controls = <&hbmc_mux 0>;
  101. clocks = <&k3_clks 102 5>;
  102. assigned-clocks = <&k3_clks 102 5>;
  103. assigned-clock-rates = <333333333>;
  104. };
  105. };
  106. mcu_i2c0: i2c@40b00000 {
  107. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  108. reg = <0x0 0x40b00000 0x0 0x100>;
  109. interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. clock-names = "fck";
  113. clocks = <&k3_clks 194 1>;
  114. power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
  115. };
  116. mcu_i2c1: i2c@40b10000 {
  117. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  118. reg = <0x0 0x40b10000 0x0 0x100>;
  119. interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. clock-names = "fck";
  123. clocks = <&k3_clks 195 1>;
  124. power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
  125. };
  126. cbass_mcu_navss: mcu-navss {
  127. compatible = "simple-mfd";
  128. #address-cells = <2>;
  129. #size-cells = <2>;
  130. ranges;
  131. dma-coherent;
  132. dma-ranges;
  133. ti,sci-dev-id = <232>;
  134. mcu_ringacc: ringacc@2b800000 {
  135. compatible = "ti,am654-navss-ringacc";
  136. reg = <0x0 0x2b800000 0x0 0x400000>,
  137. <0x0 0x2b000000 0x0 0x400000>,
  138. <0x0 0x28590000 0x0 0x100>,
  139. <0x0 0x2a500000 0x0 0x40000>;
  140. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
  141. ti,num-rings = <286>;
  142. ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
  143. ti,sci = <&dmsc>;
  144. ti,sci-dev-id = <235>;
  145. };
  146. mcu_udmap: dma-controller@285c0000 {
  147. compatible = "ti,j721e-navss-mcu-udmap";
  148. reg = <0x0 0x285c0000 0x0 0x100>,
  149. <0x0 0x2a800000 0x0 0x40000>,
  150. <0x0 0x2aa00000 0x0 0x40000>;
  151. reg-names = "gcfg", "rchanrt", "tchanrt";
  152. #dma-cells = <1>;
  153. ti,sci = <&dmsc>;
  154. ti,sci-dev-id = <236>;
  155. ti,ringacc = <&mcu_ringacc>;
  156. ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
  157. <0x0f>; /* TX_HCHAN */
  158. ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
  159. <0x0b>; /* RX_HCHAN */
  160. ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
  161. };
  162. };
  163. wkup_gpio0: gpio@42110000 {
  164. compatible = "ti,j721e-gpio", "ti,keystone-gpio";
  165. reg = <0x0 0x42110000 0x0 0x100>;
  166. gpio-controller;
  167. #gpio-cells = <2>;
  168. ti,ngpio = <84>;
  169. ti,davinci-gpio-unbanked = <0>;
  170. power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
  171. clocks = <&k3_clks 113 0>;
  172. clock-names = "gpio";
  173. };
  174. mcu_conf: scm_conf@40f00000 {
  175. compatible = "syscon", "simple-mfd";
  176. reg = <0x0 0x40f00000 0x0 0x20000>;
  177. #address-cells = <1>;
  178. #size-cells = <1>;
  179. ranges = <0x0 0x0 0x40f00000 0x20000>;
  180. phy_gmii_sel: phy@4040 {
  181. compatible = "ti,am654-cpsw-phy-sel";
  182. reg = <0x4040 0x4>;
  183. reg-names = "gmii-sel";
  184. #phy-cells = <1>;
  185. };
  186. };
  187. mcu_cpsw: ethernet@46000000 {
  188. compatible = "ti,j721e-cpsw-nuss";
  189. #address-cells = <2>;
  190. #size-cells = <2>;
  191. reg = <0x0 0x46000000 0x0 0x200000>;
  192. reg-names = "cpsw_nuss";
  193. ranges;
  194. dma-coherent;
  195. clocks = <&k3_clks 18 21>;
  196. clock-names = "fck";
  197. power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
  198. dmas = <&mcu_udmap 0xf000>,
  199. <&mcu_udmap 0xf001>,
  200. <&mcu_udmap 0xf002>,
  201. <&mcu_udmap 0xf003>,
  202. <&mcu_udmap 0xf004>,
  203. <&mcu_udmap 0xf005>,
  204. <&mcu_udmap 0xf006>,
  205. <&mcu_udmap 0xf007>,
  206. <&mcu_udmap 0x7000>;
  207. dma-names = "tx0", "tx1", "tx2", "tx3",
  208. "tx4", "tx5", "tx6", "tx7",
  209. "rx";
  210. ethernet-ports {
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. cpsw_port1: port@1 {
  214. reg = <1>;
  215. ti,mac-only;
  216. ti,label = "port1";
  217. ti,syscon-efuse = <&mcu_conf 0x200>;
  218. phys = <&phy_gmii_sel 1>;
  219. };
  220. };
  221. davinci_mdio: mdio@f00 {
  222. compatible = "ti,cpsw-mdio","ti,davinci_mdio";
  223. reg = <0x0 0xf00 0x0 0x100>;
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. clocks = <&k3_clks 18 21>;
  227. clock-names = "fck";
  228. bus_freq = <1000000>;
  229. };
  230. cpts {
  231. clocks = <&k3_clks 18 2>;
  232. clock-names = "cpts";
  233. interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
  234. interrupt-names = "cpts";
  235. ti,cpts-ext-ts-inputs = <4>;
  236. ti,cpts-periodic-outputs = <2>;
  237. };
  238. };
  239. mcu_r5fss0: r5fss@41000000 {
  240. compatible = "ti,j7200-r5fss";
  241. lockstep-mode = <1>;
  242. #address-cells = <1>;
  243. #size-cells = <1>;
  244. ranges = <0x41000000 0x00 0x41000000 0x20000>,
  245. <0x41400000 0x00 0x41400000 0x20000>;
  246. power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
  247. mcu_r5fss0_core0: r5f@41000000 {
  248. compatible = "ti,j7200-r5f";
  249. reg = <0x41000000 0x00010000>,
  250. <0x41010000 0x00010000>;
  251. reg-names = "atcm", "btcm";
  252. ti,sci = <&dmsc>;
  253. ti,sci-dev-id = <250>;
  254. ti,sci-proc-ids = <0x01 0xff>;
  255. resets = <&k3_reset 250 1>;
  256. firmware-name = "j7200-mcu-r5f0_0-fw";
  257. atcm-enable = <1>;
  258. btcm-enable = <1>;
  259. loczrama = <1>;
  260. };
  261. mcu_r5fss0_core1: r5f@41400000 {
  262. compatible = "ti,j7200-r5f";
  263. reg = <0x41400000 0x00008000>,
  264. <0x41410000 0x00008000>;
  265. reg-names = "atcm", "btcm";
  266. ti,sci = <&dmsc>;
  267. ti,sci-dev-id = <251>;
  268. ti,sci-proc-ids = <0x02 0xff>;
  269. resets = <&k3_reset 251 1>;
  270. firmware-name = "j7200-mcu-r5f0_1-fw";
  271. atcm-enable = <1>;
  272. btcm-enable = <1>;
  273. loczrama = <1>;
  274. };
  275. };
  276. };