ast2500-u-boot.dtsi 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <dt-bindings/clock/aspeed-clock.h>
  3. #include <dt-bindings/reset/ast2500-reset.h>
  4. #include "ast2500.dtsi"
  5. / {
  6. scu: clock-controller@1e6e2000 {
  7. compatible = "aspeed,ast2500-scu";
  8. reg = <0x1e6e2000 0x1000>;
  9. u-boot,dm-pre-reloc;
  10. #clock-cells = <1>;
  11. #reset-cells = <1>;
  12. };
  13. rst: reset-controller {
  14. u-boot,dm-pre-reloc;
  15. compatible = "aspeed,ast2500-reset";
  16. aspeed,wdt = <&wdt1>;
  17. #reset-cells = <1>;
  18. };
  19. sdrammc: sdrammc@1e6e0000 {
  20. u-boot,dm-pre-reloc;
  21. compatible = "aspeed,ast2500-sdrammc";
  22. reg = <0x1e6e0000 0x174
  23. 0x1e6e0200 0x1d4 >;
  24. #reset-cells = <1>;
  25. clocks = <&scu ASPEED_CLK_MPLL>;
  26. resets = <&rst AST_RESET_SDRAM>;
  27. };
  28. ahb {
  29. u-boot,dm-pre-reloc;
  30. apb {
  31. u-boot,dm-pre-reloc;
  32. sdhci0: sdhci@1e740100 {
  33. compatible = "aspeed,ast2500-sdhci";
  34. reg = <0x1e740100>;
  35. #reset-cells = <1>;
  36. clocks = <&scu ASPEED_CLK_SDIO>;
  37. resets = <&rst AST_RESET_SDIO>;
  38. };
  39. sdhci1: sdhci@1e740200 {
  40. compatible = "aspeed,ast2500-sdhci";
  41. reg = <0x1e740200>;
  42. #reset-cells = <1>;
  43. clocks = <&scu ASPEED_CLK_SDIO>;
  44. resets = <&rst AST_RESET_SDIO>;
  45. };
  46. };
  47. };
  48. };
  49. &uart1 {
  50. clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
  51. };
  52. &uart2 {
  53. clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
  54. };
  55. &uart3 {
  56. clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
  57. };
  58. &uart4 {
  59. clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
  60. };
  61. &uart5 {
  62. clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
  63. };
  64. &timer {
  65. u-boot,dm-pre-reloc;
  66. };
  67. &mac0 {
  68. clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
  69. };
  70. &mac1 {
  71. clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
  72. };