zynqmppl.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 - 2016, Xilinx, Inc,
  4. * Michal Simek <michal.simek@xilinx.com>
  5. * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
  6. */
  7. #include <console.h>
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <log.h>
  11. #include <zynqmppl.h>
  12. #include <zynqmp_firmware.h>
  13. #include <asm/cache.h>
  14. #include <linux/bitops.h>
  15. #include <linux/sizes.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <memalign.h>
  18. #define DUMMY_WORD 0xffffffff
  19. /* Xilinx binary format header */
  20. static const u32 bin_format[] = {
  21. DUMMY_WORD, /* Dummy words */
  22. DUMMY_WORD,
  23. DUMMY_WORD,
  24. DUMMY_WORD,
  25. DUMMY_WORD,
  26. DUMMY_WORD,
  27. DUMMY_WORD,
  28. DUMMY_WORD,
  29. DUMMY_WORD,
  30. DUMMY_WORD,
  31. DUMMY_WORD,
  32. DUMMY_WORD,
  33. DUMMY_WORD,
  34. DUMMY_WORD,
  35. DUMMY_WORD,
  36. DUMMY_WORD,
  37. 0x000000bb, /* Sync word */
  38. 0x11220044, /* Sync word */
  39. DUMMY_WORD,
  40. DUMMY_WORD,
  41. 0xaa995566, /* Sync word */
  42. };
  43. #define SWAP_NO 1
  44. #define SWAP_DONE 2
  45. /*
  46. * Load the whole word from unaligned buffer
  47. * Keep in your mind that it is byte loading on little-endian system
  48. */
  49. static u32 load_word(const void *buf, u32 swap)
  50. {
  51. u32 word = 0;
  52. u8 *bitc = (u8 *)buf;
  53. int p;
  54. if (swap == SWAP_NO) {
  55. for (p = 0; p < 4; p++) {
  56. word <<= 8;
  57. word |= bitc[p];
  58. }
  59. } else {
  60. for (p = 3; p >= 0; p--) {
  61. word <<= 8;
  62. word |= bitc[p];
  63. }
  64. }
  65. return word;
  66. }
  67. static u32 check_header(const void *buf)
  68. {
  69. u32 i, pattern;
  70. int swap = SWAP_NO;
  71. u32 *test = (u32 *)buf;
  72. debug("%s: Let's check bitstream header\n", __func__);
  73. /* Checking that passing bin is not a bitstream */
  74. for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  75. pattern = load_word(&test[i], swap);
  76. /*
  77. * Bitstreams in binary format are swapped
  78. * compare to regular bistream.
  79. * Do not swap dummy word but if swap is done assume
  80. * that parsing buffer is binary format
  81. */
  82. if ((__swab32(pattern) != DUMMY_WORD) &&
  83. (__swab32(pattern) == bin_format[i])) {
  84. swap = SWAP_DONE;
  85. debug("%s: data swapped - let's swap\n", __func__);
  86. }
  87. debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
  88. &test[i], pattern, bin_format[i]);
  89. }
  90. debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
  91. buf, swap == SWAP_NO ? "without" : "with");
  92. return swap;
  93. }
  94. static void *check_data(u8 *buf, size_t bsize, u32 *swap)
  95. {
  96. u32 word, p = 0; /* possition */
  97. /* Because buf doesn't need to be aligned let's read it by chars */
  98. for (p = 0; p < bsize; p++) {
  99. word = load_word(&buf[p], SWAP_NO);
  100. debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
  101. /* Find the first bitstream dummy word */
  102. if (word == DUMMY_WORD) {
  103. debug("%s: Found dummy word at position %x/%px\n",
  104. __func__, p, &buf[p]);
  105. *swap = check_header(&buf[p]);
  106. if (*swap) {
  107. /* FIXME add full bitstream checking here */
  108. return &buf[p];
  109. }
  110. }
  111. /* Loop can be huge - support CTRL + C */
  112. if (ctrlc())
  113. return NULL;
  114. }
  115. return NULL;
  116. }
  117. static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
  118. {
  119. u32 *new_buf;
  120. u32 i;
  121. if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
  122. new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
  123. /*
  124. * This might be dangerous but permits to flash if
  125. * ARCH_DMA_MINALIGN is greater than header size
  126. */
  127. if (new_buf > (u32 *)buf) {
  128. debug("%s: Aligned buffer is after buffer start\n",
  129. __func__);
  130. new_buf -= ARCH_DMA_MINALIGN;
  131. }
  132. printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
  133. buf, new_buf, swap);
  134. for (i = 0; i < (len/4); i++)
  135. new_buf[i] = load_word(&buf[i], swap);
  136. buf = new_buf;
  137. } else if ((swap != SWAP_DONE) &&
  138. (zynqmp_firmware_version() <= PMUFW_V1_0)) {
  139. /* For bitstream which are aligned */
  140. new_buf = buf;
  141. printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
  142. swap);
  143. for (i = 0; i < (len/4); i++)
  144. new_buf[i] = load_word(&buf[i], swap);
  145. }
  146. return (ulong)buf;
  147. }
  148. static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
  149. size_t bsize, u32 blocksize, u32 *swap)
  150. {
  151. ulong *buf_start;
  152. ulong diff;
  153. buf_start = check_data((u8 *)buf, blocksize, swap);
  154. if (!buf_start)
  155. return FPGA_FAIL;
  156. /* Check if data is postpone from start */
  157. diff = (ulong)buf_start - (ulong)buf;
  158. if (diff) {
  159. printf("%s: Bitstream is not validated yet (diff %lx)\n",
  160. __func__, diff);
  161. return FPGA_FAIL;
  162. }
  163. if ((ulong)buf < SZ_1M) {
  164. printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
  165. __func__, buf);
  166. return FPGA_FAIL;
  167. }
  168. return 0;
  169. }
  170. static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
  171. bitstream_type bstype)
  172. {
  173. ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
  174. u32 swap = 0;
  175. ulong bin_buf;
  176. int ret;
  177. u32 buf_lo, buf_hi;
  178. u32 ret_payload[PAYLOAD_ARG_CNT];
  179. bool xilfpga_old = false;
  180. if (zynqmp_firmware_version() <= PMUFW_V1_0) {
  181. puts("WARN: PMUFW v1.0 or less is detected\n");
  182. puts("WARN: Not all bitstream formats are supported\n");
  183. puts("WARN: Please upgrade PMUFW\n");
  184. xilfpga_old = true;
  185. if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
  186. return FPGA_FAIL;
  187. bsizeptr = (u32 *)&bsize;
  188. flush_dcache_range((ulong)bsizeptr,
  189. (ulong)bsizeptr + sizeof(size_t));
  190. bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
  191. }
  192. bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
  193. debug("%s called!\n", __func__);
  194. flush_dcache_range(bin_buf, bin_buf + bsize);
  195. buf_lo = (u32)bin_buf;
  196. buf_hi = upper_32_bits(bin_buf);
  197. if (xilfpga_old)
  198. ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
  199. buf_hi, (u32)(uintptr_t)bsizeptr,
  200. bstype, ret_payload);
  201. else
  202. ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
  203. buf_hi, (u32)bsize, 0, ret_payload);
  204. if (ret)
  205. printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
  206. return ret;
  207. }
  208. #if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
  209. static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
  210. struct fpga_secure_info *fpga_sec_info)
  211. {
  212. int ret;
  213. u32 buf_lo, buf_hi;
  214. u32 ret_payload[PAYLOAD_ARG_CNT];
  215. u8 flag = 0;
  216. flush_dcache_range((ulong)buf, (ulong)buf +
  217. ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
  218. if (!fpga_sec_info->encflag)
  219. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
  220. if (fpga_sec_info->userkey_addr &&
  221. fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
  222. flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
  223. (ulong)fpga_sec_info->userkey_addr +
  224. ALIGN(KEY_PTR_LEN,
  225. CONFIG_SYS_CACHELINE_SIZE));
  226. flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
  227. }
  228. if (!fpga_sec_info->authflag)
  229. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
  230. if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
  231. flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
  232. buf_lo = lower_32_bits((ulong)buf);
  233. buf_hi = upper_32_bits((ulong)buf);
  234. ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
  235. buf_hi,
  236. (u32)(uintptr_t)fpga_sec_info->userkey_addr,
  237. flag, ret_payload);
  238. if (ret)
  239. puts("PL FPGA LOAD fail\n");
  240. else
  241. puts("Bitstream successfully loaded\n");
  242. return ret;
  243. }
  244. #endif
  245. static int zynqmp_pcap_info(xilinx_desc *desc)
  246. {
  247. int ret;
  248. u32 ret_payload[PAYLOAD_ARG_CNT];
  249. ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0,
  250. 0, ret_payload);
  251. if (!ret)
  252. printf("PCAP status\t0x%x\n", ret_payload[1]);
  253. return ret;
  254. }
  255. struct xilinx_fpga_op zynqmp_op = {
  256. .load = zynqmp_load,
  257. #if defined CONFIG_CMD_FPGA_LOAD_SECURE
  258. .loads = zynqmp_loads,
  259. #endif
  260. .info = zynqmp_pcap_info,
  261. };