sh7757lcr.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <flash.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <asm/processor.h>
  11. #include <asm/io.h>
  12. #include <asm/mmc.h>
  13. #include <spi.h>
  14. #include <spi_flash.h>
  15. int checkboard(void)
  16. {
  17. puts("BOARD: R0P7757LC0030RL board\n");
  18. return 0;
  19. }
  20. static void init_gctrl(void)
  21. {
  22. struct gctrl_regs *gctrl = GCTRL_BASE;
  23. unsigned long graofst;
  24. graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
  25. writel(graofst | 0x20000f00, &gctrl->gracr3);
  26. }
  27. static int init_pcie_bridge_from_spi(void *buf, size_t size)
  28. {
  29. #ifdef CONFIG_DEPRECATED
  30. struct spi_flash *spi;
  31. int ret;
  32. unsigned long pcie_addr;
  33. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  34. if (!spi) {
  35. printf("%s: spi_flash probe error.\n", __func__);
  36. return 1;
  37. }
  38. if (is_sh7757_b0())
  39. pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
  40. else
  41. pcie_addr = SH7757LCR_PCIEBRG_ADDR;
  42. ret = spi_flash_read(spi, pcie_addr, size, buf);
  43. if (ret) {
  44. printf("%s: spi_flash read error.\n", __func__);
  45. spi_flash_free(spi);
  46. return 1;
  47. }
  48. spi_flash_free(spi);
  49. return 0;
  50. #else
  51. printf("No SPI support so no PCIe support\n");
  52. return 1;
  53. #endif
  54. }
  55. static void init_pcie_bridge(void)
  56. {
  57. struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
  58. struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
  59. int i;
  60. unsigned char *data;
  61. unsigned short tmp;
  62. unsigned long pcie_size;
  63. if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
  64. return;
  65. if (is_sh7757_b0())
  66. pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
  67. else
  68. pcie_size = SH7757LCR_PCIEBRG_SIZE;
  69. data = malloc(pcie_size);
  70. if (!data) {
  71. printf("%s: malloc error.\n", __func__);
  72. return;
  73. }
  74. if (init_pcie_bridge_from_spi(data, pcie_size)) {
  75. free(data);
  76. return;
  77. }
  78. if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
  79. data[3] == 0xff) {
  80. free(data);
  81. printf("%s: skipped initialization\n", __func__);
  82. return;
  83. }
  84. writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
  85. writew(0x0000, &pciebrg->cp_ctrl);
  86. writew(0x0000, &pciebrg->cp_addr);
  87. for (i = 0; i < pcie_size; i += 2) {
  88. tmp = (data[i] << 8) | data[i + 1];
  89. writew(tmp, &pciebrg->cp_data);
  90. }
  91. writew(0xa500, &pciebrg->ctrl_h8s); /* start */
  92. if (!is_sh7757_b0())
  93. writel(0x00000001, &pcie_setup->pbictl3);
  94. free(data);
  95. }
  96. static void init_usb_phy(void)
  97. {
  98. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  99. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  100. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  101. struct usb1_port_regs *port = USB1_PORT_BASE;
  102. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  103. writew(0x0100, &phy->reset); /* set reset */
  104. /* port0 = USB0, port1 = USB1 */
  105. writew(0x0002, &phy->portsel);
  106. writel(0x0001, &port->port1sel); /* port1 = Host */
  107. writew(0x0111, &phy->reset); /* clear reset */
  108. writew(0x4000, &common0->suspmode);
  109. writew(0x4000, &common1->suspmode);
  110. #if defined(__LITTLE_ENDIAN)
  111. writel(0x00000000, &align->ehcidatac);
  112. writel(0x00000000, &align->ohcidatac);
  113. #endif
  114. }
  115. static void set_mac_to_sh_eth_register(int channel, char *mac_string)
  116. {
  117. struct ether_mac_regs *ether;
  118. unsigned char mac[6];
  119. unsigned long val;
  120. string_to_enetaddr(mac_string, mac);
  121. if (!channel)
  122. ether = ETHER0_MAC_BASE;
  123. else
  124. ether = ETHER1_MAC_BASE;
  125. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  126. writel(val, &ether->mahr);
  127. val = (mac[4] << 8) | mac[5];
  128. writel(val, &ether->malr);
  129. }
  130. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  131. {
  132. struct ether_mac_regs *ether;
  133. unsigned char mac[6];
  134. unsigned long val;
  135. string_to_enetaddr(mac_string, mac);
  136. if (!channel)
  137. ether = GETHER0_MAC_BASE;
  138. else
  139. ether = GETHER1_MAC_BASE;
  140. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  141. writel(val, &ether->mahr);
  142. val = (mac[4] << 8) | mac[5];
  143. writel(val, &ether->malr);
  144. }
  145. /*****************************************************************
  146. * This PMB must be set on this timing. The lowlevel_init is run on
  147. * Area 0(phys 0x00000000), so we have to map it.
  148. *
  149. * The new PMB table is following:
  150. * ent virt phys v sz c wt
  151. * 0 0xa0000000 0x40000000 1 128M 0 1
  152. * 1 0xa8000000 0x48000000 1 128M 0 1
  153. * 2 0xb0000000 0x50000000 1 128M 0 1
  154. * 3 0xb8000000 0x58000000 1 128M 0 1
  155. * 4 0x80000000 0x40000000 1 128M 1 1
  156. * 5 0x88000000 0x48000000 1 128M 1 1
  157. * 6 0x90000000 0x50000000 1 128M 1 1
  158. * 7 0x98000000 0x58000000 1 128M 1 1
  159. */
  160. static void set_pmb_on_board_init(void)
  161. {
  162. struct mmu_regs *mmu = MMU_BASE;
  163. /* clear ITLB */
  164. writel(0x00000004, &mmu->mmucr);
  165. /* delete PMB for SPIBOOT */
  166. writel(0, PMB_ADDR_BASE(0));
  167. writel(0, PMB_DATA_BASE(0));
  168. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  169. /* ppn ub v s1 s0 c wt */
  170. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  171. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  172. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  173. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  174. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  175. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  176. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  177. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  178. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  179. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  180. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  181. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  182. }
  183. int board_init(void)
  184. {
  185. struct gether_control_regs *gether = GETHER_CONTROL_BASE;
  186. set_pmb_on_board_init();
  187. /* enable RMII's MDIO (disable GRMII's MDIO) */
  188. writel(0x00030000, &gether->gbecont);
  189. init_gctrl();
  190. init_usb_phy();
  191. return 0;
  192. }
  193. int board_mmc_init(bd_t *bis)
  194. {
  195. return mmcif_mmc_init();
  196. }
  197. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  198. {
  199. #ifdef CONFIG_DEPRECATED
  200. struct spi_flash *spi;
  201. int ret;
  202. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  203. if (spi == NULL) {
  204. printf("%s: spi_flash probe error.\n", __func__);
  205. return 1;
  206. }
  207. ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
  208. if (ret) {
  209. printf("%s: spi_flash read error.\n", __func__);
  210. spi_flash_free(spi);
  211. return 1;
  212. }
  213. spi_flash_free(spi);
  214. #endif
  215. return 0;
  216. }
  217. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  218. {
  219. memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
  220. SH7757LCR_ETHERNET_MAC_SIZE);
  221. mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  222. return 0;
  223. }
  224. static void init_ethernet_mac(void)
  225. {
  226. char mac_string[64];
  227. char env_string[64];
  228. int i;
  229. unsigned char *buf;
  230. buf = malloc(256);
  231. if (!buf) {
  232. printf("%s: malloc error.\n", __func__);
  233. return;
  234. }
  235. get_sh_eth_mac_raw(buf, 256);
  236. /* Fast Ethernet */
  237. for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
  238. get_sh_eth_mac(i, mac_string, buf);
  239. if (i == 0)
  240. env_set("ethaddr", mac_string);
  241. else {
  242. sprintf(env_string, "eth%daddr", i);
  243. env_set(env_string, mac_string);
  244. }
  245. set_mac_to_sh_eth_register(i, mac_string);
  246. }
  247. /* Gigabit Ethernet */
  248. for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
  249. get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
  250. sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
  251. env_set(env_string, mac_string);
  252. set_mac_to_sh_giga_eth_register(i, mac_string);
  253. }
  254. free(buf);
  255. }
  256. static void init_pcie(void)
  257. {
  258. struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
  259. struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
  260. writel(0x00000ff2, &pcie_setup->ladmsk0);
  261. writel(0x00000001, &pcie_setup->barmap);
  262. writel(0xffcaa000, &pcie_setup->lad0);
  263. writel(0x00030000, &pcie_sysbus->endictl0);
  264. writel(0x00000003, &pcie_sysbus->endictl1);
  265. writel(0x00000004, &pcie_setup->pbictl2);
  266. }
  267. static void finish_spiboot(void)
  268. {
  269. struct gctrl_regs *gctrl = GCTRL_BASE;
  270. /*
  271. * SH7757 B0 does not use LBSC.
  272. * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
  273. * This setting is not cleared by manual reset, So we have to set it
  274. * to 0.
  275. */
  276. writel(0x00000000, &gctrl->spibootcan);
  277. }
  278. int board_late_init(void)
  279. {
  280. init_ethernet_mac();
  281. init_pcie_bridge();
  282. init_pcie();
  283. finish_spiboot();
  284. return 0;
  285. }
  286. int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  287. {
  288. struct gctrl_regs *gctrl = GCTRL_BASE;
  289. unsigned long graofst;
  290. writel(0xfedcba98, &gctrl->wprotect);
  291. graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
  292. writel(graofst | 0xa0000f00, &gctrl->gracr3);
  293. return 0;
  294. }
  295. U_BOOT_CMD(
  296. sh_g200, 1, 1, do_sh_g200,
  297. "enable sh-g200",
  298. "enable SH-G200 bus (disable PCIe-G200)"
  299. );
  300. #ifdef CONFIG_DEPRECATED
  301. int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  302. {
  303. int i, ret;
  304. char mac_string[256];
  305. struct spi_flash *spi;
  306. unsigned char *buf;
  307. if (argc != 5) {
  308. buf = malloc(256);
  309. if (!buf) {
  310. printf("%s: malloc error.\n", __func__);
  311. return 1;
  312. }
  313. get_sh_eth_mac_raw(buf, 256);
  314. /* print current MAC address */
  315. for (i = 0; i < 4; i++) {
  316. get_sh_eth_mac(i, mac_string, buf);
  317. if (i < 2)
  318. printf(" ETHERC ch%d = %s\n", i, mac_string);
  319. else
  320. printf("GETHERC ch%d = %s\n", i-2, mac_string);
  321. }
  322. free(buf);
  323. return 0;
  324. }
  325. /* new setting */
  326. memset(mac_string, 0xff, sizeof(mac_string));
  327. sprintf(mac_string, "%s\t%s\t%s\t%s",
  328. argv[1], argv[2], argv[3], argv[4]);
  329. /* write MAC data to SPI rom */
  330. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  331. if (!spi) {
  332. printf("%s: spi_flash probe error.\n", __func__);
  333. return 1;
  334. }
  335. ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
  336. SH7757LCR_SPI_SECTOR_SIZE);
  337. if (ret) {
  338. printf("%s: spi_flash erase error.\n", __func__);
  339. return 1;
  340. }
  341. ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
  342. sizeof(mac_string), mac_string);
  343. if (ret) {
  344. printf("%s: spi_flash write error.\n", __func__);
  345. spi_flash_free(spi);
  346. return 1;
  347. }
  348. spi_flash_free(spi);
  349. puts("The writing of the MAC address to SPI ROM was completed.\n");
  350. return 0;
  351. }
  352. U_BOOT_CMD(
  353. write_mac, 5, 1, do_write_mac,
  354. "write MAC address for ETHERC/GETHERC",
  355. "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
  356. );
  357. #endif