bcsr.c 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <flash.h>
  7. #include <asm/io.h>
  8. #include "bcsr.h"
  9. void enable_8569mds_flash_write(void)
  10. {
  11. setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
  12. }
  13. void disable_8569mds_flash_write(void)
  14. {
  15. clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
  16. }
  17. void enable_8569mds_qe_uec(void)
  18. {
  19. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  20. setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
  21. BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
  22. setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
  23. BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
  24. setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
  25. BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
  26. setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
  27. BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
  28. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  29. /* Set UCC1-4 working at RMII mode */
  30. clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
  31. BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
  32. clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
  33. BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
  34. clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
  35. BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
  36. clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
  37. BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
  38. setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
  39. #endif
  40. }
  41. void disable_8569mds_brd_eeprom_write_protect(void)
  42. {
  43. clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
  44. }