usb_a9263.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2013
  4. * Stelian Pop <stelian.pop@leadtechdesign.com>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
  7. * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <asm/arch/at91sam9_smc.h>
  12. #include <asm/arch/at91_common.h>
  13. #include <asm/arch/at91_matrix.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm-generic/gpio.h>
  17. #include <asm/io.h>
  18. #include <net.h>
  19. #include <netdev.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #ifdef CONFIG_CMD_NAND
  22. static void usb_a9263_nand_hw_init(void)
  23. {
  24. unsigned long csa;
  25. at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
  26. at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
  27. /* Enable CS3 */
  28. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  29. writel(csa, &matrix->csa[0]);
  30. /* Configure SMC CS3 for NAND/SmartMedia */
  31. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  32. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  33. &smc->cs[3].setup);
  34. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  35. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  36. &smc->cs[3].pulse);
  37. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  38. &smc->cs[3].cycle);
  39. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  40. AT91_SMC_MODE_EXNW_DISABLE |
  41. AT91_SMC_MODE_DBW_8 |
  42. AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
  43. at91_periph_clk_enable(ATMEL_ID_PIOA);
  44. at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  45. /* Configure RDY/BSY */
  46. gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
  47. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  48. /* Enable NandFlash */
  49. gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
  50. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  51. }
  52. #endif
  53. #ifdef CONFIG_MACB
  54. static void usb_a9263_macb_hw_init(void)
  55. {
  56. at91_periph_clk_enable(ATMEL_ID_EMAC);
  57. /*
  58. * Disable pull-up on:
  59. * RXDV (PC25) => PHY normal mode (not Test mode)
  60. * ERX0 (PE25) => PHY ADDR0
  61. * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  62. *
  63. * PHY has internal weak pull-up/pull-down
  64. */
  65. gpio_request(GPIO_PIN_PC(25), "PHY mode");
  66. gpio_direction_input(GPIO_PIN_PC(25));
  67. gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
  68. gpio_direction_input(GPIO_PIN_PE(25));
  69. gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
  70. gpio_direction_input(GPIO_PIN_PE(26));
  71. at91_phy_reset();
  72. /* It will set proper pinmux for ports PC25, PE25-26 */
  73. at91_macb_hw_init();
  74. }
  75. #endif
  76. int board_init(void)
  77. {
  78. /* adress of boot parameters */
  79. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  80. #ifdef CONFIG_CMD_NAND
  81. usb_a9263_nand_hw_init();
  82. #endif
  83. #ifdef CONFIG_MACB
  84. usb_a9263_macb_hw_init();
  85. #endif
  86. #ifdef CONFIG_USB_OHCI_NEW
  87. at91_uhp_hw_init();
  88. #endif
  89. return 0;
  90. }
  91. int dram_init(void)
  92. {
  93. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  94. CONFIG_SYS_SDRAM_SIZE);
  95. return 0;
  96. }
  97. int board_eth_init(struct bd_info *bis)
  98. {
  99. int rc = 0;
  100. #ifdef CONFIG_MACB
  101. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
  102. #endif
  103. return rc;
  104. }