nitrogen6x.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <malloc.h>
  17. #include <asm/arch/mx6-pins.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <asm/gpio.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/mxc_i2c.h>
  23. #include <asm/mach-imx/sata.h>
  24. #include <asm/mach-imx/spi.h>
  25. #include <asm/mach-imx/boot_mode.h>
  26. #include <asm/mach-imx/video.h>
  27. #include <fsl_esdhc_imx.h>
  28. #include <micrel.h>
  29. #include <miiphy.h>
  30. #include <netdev.h>
  31. #include <asm/arch/crm_regs.h>
  32. #include <asm/arch/mxc_hdmi.h>
  33. #include <i2c.h>
  34. #include <input.h>
  35. #include <netdev.h>
  36. #include <usb/ehci-ci.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  39. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  40. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  41. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  43. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  44. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  45. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  46. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  48. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  49. #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  50. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  52. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  53. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54. #define RGB_PAD_CTRL PAD_CTL_DSE_120ohm
  55. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  56. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  57. PAD_CTL_SRE_SLOW)
  58. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  59. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  60. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  61. #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  62. /* Prevent compiler error if gpio number 08 or 09 is used */
  63. #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  64. #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
  65. sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) { \
  66. .scl = { \
  67. .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  68. pad_ctrl), \
  69. .gpio_mode = NEW_PAD_CTRL( \
  70. cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  71. pad_ctrl), \
  72. .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp)) \
  73. }, \
  74. .sda = { \
  75. .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  76. pad_ctrl), \
  77. .gpio_mode = NEW_PAD_CTRL( \
  78. cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  79. pad_ctrl), \
  80. .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp)) \
  81. } \
  82. }
  83. #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
  84. sda_pad, sda_bank, sda_gp, pad_ctrl) \
  85. _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp, \
  86. sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
  87. #if defined(CONFIG_MX6QDL)
  88. #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
  89. sda_pad, sda_bank, sda_gp, pad_ctrl) \
  90. I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp, \
  91. sda_pad, sda_bank, sda_gp, pad_ctrl), \
  92. I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp, \
  93. sda_pad, sda_bank, sda_gp, pad_ctrl)
  94. #define I2C_PADS_INFO_ENTRY_SPACING 2
  95. #define IOMUX_PAD_CTRL(name, pad_ctrl) \
  96. NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl), \
  97. NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
  98. #else
  99. #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp, \
  100. sda_pad, sda_bank, sda_gp, pad_ctrl) \
  101. I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp, \
  102. sda_pad, sda_bank, sda_gp, pad_ctrl)
  103. #define I2C_PADS_INFO_ENTRY_SPACING 1
  104. #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
  105. #endif
  106. int dram_init(void)
  107. {
  108. gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  109. return 0;
  110. }
  111. static iomux_v3_cfg_t const uart1_pads[] = {
  112. IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
  113. IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
  114. };
  115. static iomux_v3_cfg_t const uart2_pads[] = {
  116. IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
  117. IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
  118. };
  119. static struct i2c_pads_info i2c_pads[] = {
  120. /* I2C1, SGTL5000 */
  121. I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
  122. /* I2C2 Camera, MIPI */
  123. I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
  124. I2C_PAD_CTRL),
  125. /* I2C3, J15 - RGB connector */
  126. I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
  127. };
  128. #define I2C_BUS_CNT 3
  129. static iomux_v3_cfg_t const usdhc2_pads[] = {
  130. IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
  131. IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
  132. IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
  133. IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
  134. IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
  135. IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
  136. };
  137. static iomux_v3_cfg_t const enet_pads1[] = {
  138. IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
  139. IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
  140. IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
  141. IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
  142. IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
  143. IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
  144. IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
  145. IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
  146. IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
  147. /* pin 35 - 1 (PHY_AD2) on reset */
  148. IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
  149. /* pin 32 - 1 - (MODE0) all */
  150. IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
  151. /* pin 31 - 1 - (MODE1) all */
  152. IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
  153. /* pin 28 - 1 - (MODE2) all */
  154. IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
  155. /* pin 27 - 1 - (MODE3) all */
  156. IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
  157. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  158. IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
  159. /* pin 42 PHY nRST */
  160. IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
  161. IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
  162. };
  163. static iomux_v3_cfg_t const enet_pads2[] = {
  164. IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
  165. IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
  166. IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
  167. IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
  168. IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
  169. IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
  170. };
  171. static iomux_v3_cfg_t const misc_pads[] = {
  172. IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
  173. IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
  174. IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
  175. /* OTG Power enable */
  176. IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
  177. };
  178. /* wl1271 pads on nitrogen6x */
  179. static iomux_v3_cfg_t const wl12xx_pads[] = {
  180. IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
  181. IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
  182. IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
  183. };
  184. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  185. #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
  186. #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
  187. /* Button assignments for J14 */
  188. static iomux_v3_cfg_t const button_pads[] = {
  189. /* Menu */
  190. IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
  191. /* Back */
  192. IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
  193. /* Labelled Search (mapped to Power under Android) */
  194. IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
  195. /* Home */
  196. IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
  197. /* Volume Down */
  198. IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
  199. /* Volume Up */
  200. IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
  201. };
  202. static void setup_iomux_enet(void)
  203. {
  204. gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
  205. gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
  206. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  207. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  208. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  209. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  210. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  211. SETUP_IOMUX_PADS(enet_pads1);
  212. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  213. /* Need delay 10ms according to KSZ9021 spec */
  214. udelay(1000 * 10);
  215. gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
  216. gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
  217. SETUP_IOMUX_PADS(enet_pads2);
  218. udelay(100); /* Wait 100 us before using mii interface */
  219. }
  220. static iomux_v3_cfg_t const usb_pads[] = {
  221. IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
  222. };
  223. static void setup_iomux_uart(void)
  224. {
  225. SETUP_IOMUX_PADS(uart1_pads);
  226. SETUP_IOMUX_PADS(uart2_pads);
  227. }
  228. #ifdef CONFIG_USB_EHCI_MX6
  229. int board_ehci_hcd_init(int port)
  230. {
  231. SETUP_IOMUX_PADS(usb_pads);
  232. /* Reset USB hub */
  233. gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
  234. mdelay(2);
  235. gpio_set_value(IMX_GPIO_NR(7, 12), 1);
  236. return 0;
  237. }
  238. int board_ehci_power(int port, int on)
  239. {
  240. if (port)
  241. return 0;
  242. gpio_set_value(GP_USB_OTG_PWR, on);
  243. return 0;
  244. }
  245. #endif
  246. #ifdef CONFIG_MXC_SPI
  247. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  248. {
  249. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  250. }
  251. static iomux_v3_cfg_t const ecspi1_pads[] = {
  252. /* SS1 */
  253. IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
  254. IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
  255. IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
  256. IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
  257. };
  258. static void setup_spi(void)
  259. {
  260. SETUP_IOMUX_PADS(ecspi1_pads);
  261. }
  262. #endif
  263. int board_phy_config(struct phy_device *phydev)
  264. {
  265. /* min rx data delay */
  266. ksz9021_phy_extended_write(phydev,
  267. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  268. /* min tx data delay */
  269. ksz9021_phy_extended_write(phydev,
  270. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  271. /* max rx/tx clock delay, min rx/tx control */
  272. ksz9021_phy_extended_write(phydev,
  273. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  274. if (phydev->drv->config)
  275. phydev->drv->config(phydev);
  276. return 0;
  277. }
  278. int board_eth_init(struct bd_info *bis)
  279. {
  280. uint32_t base = IMX_FEC_BASE;
  281. struct mii_dev *bus = NULL;
  282. struct phy_device *phydev = NULL;
  283. int ret;
  284. gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
  285. gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
  286. gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
  287. gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
  288. gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
  289. gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
  290. gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
  291. gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
  292. gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
  293. setup_iomux_enet();
  294. #ifdef CONFIG_FEC_MXC
  295. bus = fec_get_miibus(base, -1);
  296. if (!bus)
  297. return -EINVAL;
  298. /* scan phy 4,5,6,7 */
  299. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  300. if (!phydev) {
  301. ret = -EINVAL;
  302. goto free_bus;
  303. }
  304. printf("using phy at %d\n", phydev->addr);
  305. ret = fec_probe(bis, -1, base, bus, phydev);
  306. if (ret)
  307. goto free_phydev;
  308. #endif
  309. #ifdef CONFIG_CI_UDC
  310. /* For otg ethernet*/
  311. usb_eth_initialize(bis);
  312. #endif
  313. return 0;
  314. free_phydev:
  315. free(phydev);
  316. free_bus:
  317. free(bus);
  318. return ret;
  319. }
  320. static void setup_buttons(void)
  321. {
  322. SETUP_IOMUX_PADS(button_pads);
  323. }
  324. #if defined(CONFIG_VIDEO_IPUV3)
  325. static iomux_v3_cfg_t const backlight_pads[] = {
  326. /* Backlight on RGB connector: J15 */
  327. IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
  328. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
  329. /* Backlight on LVDS connector: J6 */
  330. IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
  331. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
  332. };
  333. static iomux_v3_cfg_t const rgb_pads[] = {
  334. IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
  335. IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
  336. IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
  337. IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
  338. IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
  339. IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
  340. IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
  341. IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
  342. IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
  343. IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
  344. IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
  345. IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
  346. IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
  347. IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
  348. IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
  349. IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
  350. IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
  351. IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
  352. IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
  353. IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
  354. IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
  355. IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
  356. IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
  357. IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
  358. IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
  359. IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
  360. IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
  361. IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
  362. IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
  363. };
  364. static void do_enable_hdmi(struct display_info_t const *dev)
  365. {
  366. imx_enable_hdmi_phy();
  367. }
  368. static int detect_i2c(struct display_info_t const *dev)
  369. {
  370. return ((0 == i2c_set_bus_num(dev->bus))
  371. &&
  372. (0 == i2c_probe(dev->addr)));
  373. }
  374. static void enable_lvds(struct display_info_t const *dev)
  375. {
  376. struct iomuxc *iomux = (struct iomuxc *)
  377. IOMUXC_BASE_ADDR;
  378. u32 reg = readl(&iomux->gpr[2]);
  379. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  380. writel(reg, &iomux->gpr[2]);
  381. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  382. }
  383. static void enable_lvds_jeida(struct display_info_t const *dev)
  384. {
  385. struct iomuxc *iomux = (struct iomuxc *)
  386. IOMUXC_BASE_ADDR;
  387. u32 reg = readl(&iomux->gpr[2]);
  388. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  389. |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
  390. writel(reg, &iomux->gpr[2]);
  391. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  392. }
  393. static void enable_rgb(struct display_info_t const *dev)
  394. {
  395. SETUP_IOMUX_PADS(rgb_pads);
  396. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  397. }
  398. struct display_info_t const displays[] = {{
  399. .bus = 1,
  400. .addr = 0x50,
  401. .pixfmt = IPU_PIX_FMT_RGB24,
  402. .detect = detect_i2c,
  403. .enable = do_enable_hdmi,
  404. .mode = {
  405. .name = "HDMI",
  406. .refresh = 60,
  407. .xres = 1024,
  408. .yres = 768,
  409. .pixclock = 15385,
  410. .left_margin = 220,
  411. .right_margin = 40,
  412. .upper_margin = 21,
  413. .lower_margin = 7,
  414. .hsync_len = 60,
  415. .vsync_len = 10,
  416. .sync = FB_SYNC_EXT,
  417. .vmode = FB_VMODE_NONINTERLACED
  418. } }, {
  419. .bus = 0,
  420. .addr = 0,
  421. .pixfmt = IPU_PIX_FMT_RGB24,
  422. .detect = NULL,
  423. .enable = enable_lvds_jeida,
  424. .mode = {
  425. .name = "LDB-WXGA",
  426. .refresh = 60,
  427. .xres = 1280,
  428. .yres = 800,
  429. .pixclock = 14065,
  430. .left_margin = 40,
  431. .right_margin = 40,
  432. .upper_margin = 3,
  433. .lower_margin = 80,
  434. .hsync_len = 10,
  435. .vsync_len = 10,
  436. .sync = FB_SYNC_EXT,
  437. .vmode = FB_VMODE_NONINTERLACED
  438. } }, {
  439. .bus = 0,
  440. .addr = 0,
  441. .pixfmt = IPU_PIX_FMT_RGB24,
  442. .detect = NULL,
  443. .enable = enable_lvds,
  444. .mode = {
  445. .name = "LDB-WXGA-S",
  446. .refresh = 60,
  447. .xres = 1280,
  448. .yres = 800,
  449. .pixclock = 14065,
  450. .left_margin = 40,
  451. .right_margin = 40,
  452. .upper_margin = 3,
  453. .lower_margin = 80,
  454. .hsync_len = 10,
  455. .vsync_len = 10,
  456. .sync = FB_SYNC_EXT,
  457. .vmode = FB_VMODE_NONINTERLACED
  458. } }, {
  459. .bus = 2,
  460. .addr = 0x4,
  461. .pixfmt = IPU_PIX_FMT_LVDS666,
  462. .detect = detect_i2c,
  463. .enable = enable_lvds,
  464. .mode = {
  465. .name = "Hannstar-XGA",
  466. .refresh = 60,
  467. .xres = 1024,
  468. .yres = 768,
  469. .pixclock = 15385,
  470. .left_margin = 220,
  471. .right_margin = 40,
  472. .upper_margin = 21,
  473. .lower_margin = 7,
  474. .hsync_len = 60,
  475. .vsync_len = 10,
  476. .sync = FB_SYNC_EXT,
  477. .vmode = FB_VMODE_NONINTERLACED
  478. } }, {
  479. .bus = 0,
  480. .addr = 0,
  481. .pixfmt = IPU_PIX_FMT_LVDS666,
  482. .detect = NULL,
  483. .enable = enable_lvds,
  484. .mode = {
  485. .name = "LG-9.7",
  486. .refresh = 60,
  487. .xres = 1024,
  488. .yres = 768,
  489. .pixclock = 15385, /* ~65MHz */
  490. .left_margin = 480,
  491. .right_margin = 260,
  492. .upper_margin = 16,
  493. .lower_margin = 6,
  494. .hsync_len = 250,
  495. .vsync_len = 10,
  496. .sync = FB_SYNC_EXT,
  497. .vmode = FB_VMODE_NONINTERLACED
  498. } }, {
  499. .bus = 2,
  500. .addr = 0x38,
  501. .pixfmt = IPU_PIX_FMT_LVDS666,
  502. .detect = detect_i2c,
  503. .enable = enable_lvds,
  504. .mode = {
  505. .name = "wsvga-lvds",
  506. .refresh = 60,
  507. .xres = 1024,
  508. .yres = 600,
  509. .pixclock = 15385,
  510. .left_margin = 220,
  511. .right_margin = 40,
  512. .upper_margin = 21,
  513. .lower_margin = 7,
  514. .hsync_len = 60,
  515. .vsync_len = 10,
  516. .sync = FB_SYNC_EXT,
  517. .vmode = FB_VMODE_NONINTERLACED
  518. } }, {
  519. .bus = 2,
  520. .addr = 0x10,
  521. .pixfmt = IPU_PIX_FMT_RGB666,
  522. .detect = detect_i2c,
  523. .enable = enable_rgb,
  524. .mode = {
  525. .name = "fusion7",
  526. .refresh = 60,
  527. .xres = 800,
  528. .yres = 480,
  529. .pixclock = 33898,
  530. .left_margin = 96,
  531. .right_margin = 24,
  532. .upper_margin = 3,
  533. .lower_margin = 10,
  534. .hsync_len = 72,
  535. .vsync_len = 7,
  536. .sync = 0x40000002,
  537. .vmode = FB_VMODE_NONINTERLACED
  538. } }, {
  539. .bus = 0,
  540. .addr = 0,
  541. .pixfmt = IPU_PIX_FMT_RGB666,
  542. .detect = NULL,
  543. .enable = enable_rgb,
  544. .mode = {
  545. .name = "svga",
  546. .refresh = 60,
  547. .xres = 800,
  548. .yres = 600,
  549. .pixclock = 15385,
  550. .left_margin = 220,
  551. .right_margin = 40,
  552. .upper_margin = 21,
  553. .lower_margin = 7,
  554. .hsync_len = 60,
  555. .vsync_len = 10,
  556. .sync = 0,
  557. .vmode = FB_VMODE_NONINTERLACED
  558. } }, {
  559. .bus = 2,
  560. .addr = 0x41,
  561. .pixfmt = IPU_PIX_FMT_LVDS666,
  562. .detect = detect_i2c,
  563. .enable = enable_lvds,
  564. .mode = {
  565. .name = "amp1024x600",
  566. .refresh = 60,
  567. .xres = 1024,
  568. .yres = 600,
  569. .pixclock = 15385,
  570. .left_margin = 220,
  571. .right_margin = 40,
  572. .upper_margin = 21,
  573. .lower_margin = 7,
  574. .hsync_len = 60,
  575. .vsync_len = 10,
  576. .sync = FB_SYNC_EXT,
  577. .vmode = FB_VMODE_NONINTERLACED
  578. } }, {
  579. .bus = 0,
  580. .addr = 0,
  581. .pixfmt = IPU_PIX_FMT_LVDS666,
  582. .detect = 0,
  583. .enable = enable_lvds,
  584. .mode = {
  585. .name = "wvga-lvds",
  586. .refresh = 57,
  587. .xres = 800,
  588. .yres = 480,
  589. .pixclock = 15385,
  590. .left_margin = 220,
  591. .right_margin = 40,
  592. .upper_margin = 21,
  593. .lower_margin = 7,
  594. .hsync_len = 60,
  595. .vsync_len = 10,
  596. .sync = FB_SYNC_EXT,
  597. .vmode = FB_VMODE_NONINTERLACED
  598. } }, {
  599. .bus = 2,
  600. .addr = 0x48,
  601. .pixfmt = IPU_PIX_FMT_RGB666,
  602. .detect = detect_i2c,
  603. .enable = enable_rgb,
  604. .mode = {
  605. .name = "wvga-rgb",
  606. .refresh = 57,
  607. .xres = 800,
  608. .yres = 480,
  609. .pixclock = 37037,
  610. .left_margin = 40,
  611. .right_margin = 60,
  612. .upper_margin = 10,
  613. .lower_margin = 10,
  614. .hsync_len = 20,
  615. .vsync_len = 10,
  616. .sync = 0,
  617. .vmode = FB_VMODE_NONINTERLACED
  618. } }, {
  619. .bus = 0,
  620. .addr = 0,
  621. .pixfmt = IPU_PIX_FMT_RGB24,
  622. .detect = NULL,
  623. .enable = enable_rgb,
  624. .mode = {
  625. .name = "qvga",
  626. .refresh = 60,
  627. .xres = 320,
  628. .yres = 240,
  629. .pixclock = 37037,
  630. .left_margin = 38,
  631. .right_margin = 37,
  632. .upper_margin = 16,
  633. .lower_margin = 15,
  634. .hsync_len = 30,
  635. .vsync_len = 3,
  636. .sync = 0,
  637. .vmode = FB_VMODE_NONINTERLACED
  638. } } };
  639. size_t display_count = ARRAY_SIZE(displays);
  640. int board_cfb_skip(void)
  641. {
  642. return NULL != env_get("novideo");
  643. }
  644. static void setup_display(void)
  645. {
  646. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  647. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  648. int reg;
  649. enable_ipu_clock();
  650. imx_setup_hdmi();
  651. /* Turn on LDB0,IPU,IPU DI0 clocks */
  652. reg = __raw_readl(&mxc_ccm->CCGR3);
  653. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  654. writel(reg, &mxc_ccm->CCGR3);
  655. /* set LDB0, LDB1 clk select to 011/011 */
  656. reg = readl(&mxc_ccm->cs2cdr);
  657. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  658. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  659. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  660. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  661. writel(reg, &mxc_ccm->cs2cdr);
  662. reg = readl(&mxc_ccm->cscmr2);
  663. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  664. writel(reg, &mxc_ccm->cscmr2);
  665. reg = readl(&mxc_ccm->chsccdr);
  666. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  667. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  668. writel(reg, &mxc_ccm->chsccdr);
  669. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  670. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  671. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  672. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  673. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  674. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  675. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  676. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  677. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  678. writel(reg, &iomux->gpr[2]);
  679. reg = readl(&iomux->gpr[3]);
  680. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  681. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  682. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  683. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  684. writel(reg, &iomux->gpr[3]);
  685. /* backlights off until needed */
  686. SETUP_IOMUX_PADS(backlight_pads);
  687. gpio_direction_input(LVDS_BACKLIGHT_GP);
  688. gpio_direction_input(RGB_BACKLIGHT_GP);
  689. }
  690. #endif
  691. static iomux_v3_cfg_t const init_pads[] = {
  692. /* SGTL5000 sys_mclk */
  693. IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
  694. /* J5 - Camera MCLK */
  695. IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
  696. /* wl1271 pads on nitrogen6x */
  697. /* WL12XX_WL_IRQ_GP */
  698. IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
  699. /* WL12XX_WL_ENABLE_GP */
  700. IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
  701. /* WL12XX_BT_ENABLE_GP */
  702. IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
  703. /* USB otg power */
  704. IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
  705. IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
  706. IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
  707. IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
  708. IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
  709. };
  710. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  711. static unsigned gpios_out_low[] = {
  712. /* Disable wl1271 */
  713. IMX_GPIO_NR(6, 15), /* disable wireless */
  714. IMX_GPIO_NR(6, 16), /* disable bluetooth */
  715. IMX_GPIO_NR(3, 22), /* disable USB otg power */
  716. IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
  717. IMX_GPIO_NR(1, 8), /* ov5642 reset */
  718. };
  719. static unsigned gpios_out_high[] = {
  720. IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
  721. IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
  722. };
  723. static void set_gpios(unsigned *p, int cnt, int val)
  724. {
  725. int i;
  726. for (i = 0; i < cnt; i++)
  727. gpio_direction_output(*p++, val);
  728. }
  729. int board_early_init_f(void)
  730. {
  731. setup_iomux_uart();
  732. set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
  733. set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
  734. gpio_direction_input(WL12XX_WL_IRQ_GP);
  735. SETUP_IOMUX_PADS(wl12xx_pads);
  736. SETUP_IOMUX_PADS(init_pads);
  737. setup_buttons();
  738. #if defined(CONFIG_VIDEO_IPUV3)
  739. setup_display();
  740. #endif
  741. return 0;
  742. }
  743. /*
  744. * Do not overwrite the console
  745. * Use always serial for U-Boot console
  746. */
  747. int overwrite_console(void)
  748. {
  749. return 1;
  750. }
  751. int board_init(void)
  752. {
  753. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  754. struct i2c_pads_info *p = i2c_pads;
  755. int i;
  756. int stride = 1;
  757. #if defined(CONFIG_MX6QDL)
  758. stride = 2;
  759. if (!is_mx6dq() && !is_mx6dqp())
  760. p += 1;
  761. #endif
  762. clrsetbits_le32(&iomuxc_regs->gpr[1],
  763. IOMUXC_GPR1_OTG_ID_MASK,
  764. IOMUXC_GPR1_OTG_ID_GPIO1);
  765. SETUP_IOMUX_PADS(misc_pads);
  766. /* address of boot parameters */
  767. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  768. #ifdef CONFIG_MXC_SPI
  769. setup_spi();
  770. #endif
  771. SETUP_IOMUX_PADS(usdhc2_pads);
  772. for (i = 0; i < I2C_BUS_CNT; i++) {
  773. setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
  774. p += stride;
  775. }
  776. #ifdef CONFIG_SATA
  777. setup_sata();
  778. #endif
  779. return 0;
  780. }
  781. int checkboard(void)
  782. {
  783. int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
  784. if (ret < 0) {
  785. /* The gpios have not been probed yet. Read it myself */
  786. struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
  787. int gpio = WL12XX_WL_IRQ_GP & 0x1f;
  788. ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  789. }
  790. if (ret)
  791. puts("Board: Nitrogen6X\n");
  792. else
  793. puts("Board: SABRE Lite\n");
  794. return 0;
  795. }
  796. struct button_key {
  797. char const *name;
  798. unsigned gpnum;
  799. char ident;
  800. };
  801. static struct button_key const buttons[] = {
  802. {"back", IMX_GPIO_NR(2, 2), 'B'},
  803. {"home", IMX_GPIO_NR(2, 4), 'H'},
  804. {"menu", IMX_GPIO_NR(2, 1), 'M'},
  805. {"search", IMX_GPIO_NR(2, 3), 'S'},
  806. {"volup", IMX_GPIO_NR(7, 13), 'V'},
  807. {"voldown", IMX_GPIO_NR(4, 5), 'v'},
  808. };
  809. /*
  810. * generate a null-terminated string containing the buttons pressed
  811. * returns number of keys pressed
  812. */
  813. static int read_keys(char *buf)
  814. {
  815. int i, numpressed = 0;
  816. for (i = 0; i < ARRAY_SIZE(buttons); i++) {
  817. if (!gpio_get_value(buttons[i].gpnum))
  818. buf[numpressed++] = buttons[i].ident;
  819. }
  820. buf[numpressed] = '\0';
  821. return numpressed;
  822. }
  823. static int do_kbd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  824. {
  825. char envvalue[ARRAY_SIZE(buttons)+1];
  826. int numpressed = read_keys(envvalue);
  827. env_set("keybd", envvalue);
  828. return numpressed == 0;
  829. }
  830. U_BOOT_CMD(
  831. kbd, 1, 1, do_kbd,
  832. "Tests for keypresses, sets 'keybd' environment variable",
  833. "Returns 0 (true) to shell if key is pressed."
  834. );
  835. #ifdef CONFIG_PREBOOT
  836. static char const kbd_magic_prefix[] = "key_magic";
  837. static char const kbd_command_prefix[] = "key_cmd";
  838. static void preboot_keys(void)
  839. {
  840. int numpressed;
  841. char keypress[ARRAY_SIZE(buttons)+1];
  842. numpressed = read_keys(keypress);
  843. if (numpressed) {
  844. char *kbd_magic_keys = env_get("magic_keys");
  845. char *suffix;
  846. /*
  847. * loop over all magic keys
  848. */
  849. for (suffix = kbd_magic_keys; *suffix; ++suffix) {
  850. char *keys;
  851. char magic[sizeof(kbd_magic_prefix) + 1];
  852. sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
  853. keys = env_get(magic);
  854. if (keys) {
  855. if (!strcmp(keys, keypress))
  856. break;
  857. }
  858. }
  859. if (*suffix) {
  860. char cmd_name[sizeof(kbd_command_prefix) + 1];
  861. char *cmd;
  862. sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
  863. cmd = env_get(cmd_name);
  864. if (cmd) {
  865. env_set("preboot", cmd);
  866. return;
  867. }
  868. }
  869. }
  870. }
  871. #endif
  872. #ifdef CONFIG_CMD_BMODE
  873. static const struct boot_mode board_boot_modes[] = {
  874. /* 4 bit bus width */
  875. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  876. {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  877. {NULL, 0},
  878. };
  879. #endif
  880. int misc_init_r(void)
  881. {
  882. gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
  883. gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
  884. gpio_request(GP_USB_OTG_PWR, "usbotg power");
  885. gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
  886. gpio_request(IMX_GPIO_NR(2, 2), "back");
  887. gpio_request(IMX_GPIO_NR(2, 4), "home");
  888. gpio_request(IMX_GPIO_NR(2, 1), "menu");
  889. gpio_request(IMX_GPIO_NR(2, 3), "search");
  890. gpio_request(IMX_GPIO_NR(7, 13), "volup");
  891. gpio_request(IMX_GPIO_NR(4, 5), "voldown");
  892. #ifdef CONFIG_PREBOOT
  893. preboot_keys();
  894. #endif
  895. #ifdef CONFIG_CMD_BMODE
  896. add_board_boot_modes(board_boot_modes);
  897. #endif
  898. env_set_hex("reset_cause", get_imx_reset_cause());
  899. return 0;
  900. }