board.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * (C) Copyright 2016
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. *
  8. * Based on:
  9. * Board functions for TI AM335X based boards
  10. *
  11. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12. */
  13. #include <common.h>
  14. #include <bootstage.h>
  15. #include <cpu_func.h>
  16. #include <env.h>
  17. #include <errno.h>
  18. #include <init.h>
  19. #include <irq_func.h>
  20. #include <net.h>
  21. #include <spl.h>
  22. #include <asm/arch/cpu.h>
  23. #include <asm/arch/hardware.h>
  24. #include <asm/arch/omap.h>
  25. #include <asm/arch/ddr_defs.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/mmc_host_def.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/arch/mem.h>
  31. #include <asm/io.h>
  32. #include <asm/emif.h>
  33. #include <asm/gpio.h>
  34. #include <i2c.h>
  35. #include <miiphy.h>
  36. #include <cpsw.h>
  37. #include <linux/delay.h>
  38. #include <power/tps65217.h>
  39. #include <env_internal.h>
  40. #include <watchdog.h>
  41. #include "mmc.h"
  42. #include "board.h"
  43. DECLARE_GLOBAL_DATA_PTR;
  44. static struct shc_eeprom __attribute__((section(".data"))) header;
  45. static int shc_eeprom_valid;
  46. /*
  47. * Read header information from EEPROM into global structure.
  48. */
  49. static int read_eeprom(void)
  50. {
  51. /* Check if baseboard eeprom is available */
  52. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  53. puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
  54. return -ENODEV;
  55. }
  56. /* read the eeprom using i2c */
  57. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
  58. sizeof(header))) {
  59. puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
  60. return -EIO;
  61. }
  62. if (header.magic != HDR_MAGIC) {
  63. printf("Incorrect magic number (0x%x) in EEPROM\n",
  64. header.magic);
  65. return -EIO;
  66. }
  67. shc_eeprom_valid = 1;
  68. return 0;
  69. }
  70. static void shc_request_gpio(void)
  71. {
  72. gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
  73. gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
  74. gpio_request(RESET_GPIO, "reset");
  75. gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
  76. gpio_request(WIFI_RST_GPIO, "WIFI rst");
  77. gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
  78. gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
  79. gpio_request(ENOC_RST_GPIO, "ENOC rst");
  80. #if defined CONFIG_B_SAMPLE
  81. gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
  82. gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
  83. gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
  84. gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
  85. #else
  86. gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
  87. gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
  88. gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
  89. gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
  90. gpio_request(LED_PWM_GPIO, "LED PWM");
  91. gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
  92. #endif
  93. gpio_request(BACK_BUTTON_GPIO, "Back button");
  94. gpio_request(FRONT_BUTTON_GPIO, "Front button");
  95. }
  96. /*
  97. * Function which forces all installed modules into running state for ICT
  98. * testing. Called by SPL.
  99. */
  100. static void __maybe_unused force_modules_running(void)
  101. {
  102. /* Wi-Fi power regulator enable - high = enabled */
  103. gpio_direction_output(WIFI_REGEN_GPIO, 1);
  104. /*
  105. * Wait for Wi-Fi power regulator to reach a stable voltage
  106. * (soft-start time, max. 350 µs)
  107. */
  108. __udelay(350);
  109. /* Wi-Fi module reset - high = running */
  110. gpio_direction_output(WIFI_RST_GPIO, 1);
  111. /* ZigBee reset - high = running */
  112. gpio_direction_output(ZIGBEE_RST_GPIO, 1);
  113. /* BidCos reset - high = running */
  114. gpio_direction_output(BIDCOS_RST_GPIO, 1);
  115. #if !defined(CONFIG_B_SAMPLE)
  116. /* Z-Wave reset - high = running */
  117. gpio_direction_output(Z_WAVE_RST_GPIO, 1);
  118. #endif
  119. /* EnOcean reset - low = running */
  120. gpio_direction_output(ENOC_RST_GPIO, 0);
  121. }
  122. /*
  123. * Function which forces all installed modules into reset - to be released by
  124. * the OS, called by SPL
  125. */
  126. static void __maybe_unused force_modules_reset(void)
  127. {
  128. /* Wi-Fi module reset - low = reset */
  129. gpio_direction_output(WIFI_RST_GPIO, 0);
  130. /* Wi-Fi power regulator enable - low = disabled */
  131. gpio_direction_output(WIFI_REGEN_GPIO, 0);
  132. /* ZigBee reset - low = reset */
  133. gpio_direction_output(ZIGBEE_RST_GPIO, 0);
  134. /* BidCos reset - low = reset */
  135. /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
  136. #if !defined(CONFIG_B_SAMPLE)
  137. /* Z-Wave reset - low = reset */
  138. gpio_direction_output(Z_WAVE_RST_GPIO, 0);
  139. #endif
  140. /* EnOcean reset - high = reset*/
  141. gpio_direction_output(ENOC_RST_GPIO, 1);
  142. }
  143. /*
  144. * Function to set the LEDs in the state "Bootloader booting"
  145. */
  146. static void __maybe_unused leds_set_booting(void)
  147. {
  148. #if defined(CONFIG_B_SAMPLE)
  149. /* Turn all red LEDs on */
  150. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  151. gpio_direction_output(LED_CONN_RD_GPIO, 1);
  152. #else /* All other SHCs starting with B2-Sample */
  153. /* Set the PWM GPIO */
  154. gpio_direction_output(LED_PWM_GPIO, 1);
  155. /* Turn all red LEDs on */
  156. gpio_direction_output(LED_PWR_RD_GPIO, 1);
  157. gpio_direction_output(LED_LAN_RD_GPIO, 1);
  158. gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
  159. #endif
  160. }
  161. /*
  162. * Function to set the LEDs in the state "Bootloader error"
  163. */
  164. static void leds_set_failure(int state)
  165. {
  166. #if defined(CONFIG_B_SAMPLE)
  167. /* Turn all blue and green LEDs off */
  168. gpio_set_value(LED_PWR_BL_GPIO, 0);
  169. gpio_set_value(LED_PWR_GN_GPIO, 0);
  170. gpio_set_value(LED_CONN_BL_GPIO, 0);
  171. gpio_set_value(LED_CONN_GN_GPIO, 0);
  172. /* Turn all red LEDs to 'state' */
  173. gpio_set_value(LED_PWR_RD_GPIO, state);
  174. gpio_set_value(LED_CONN_RD_GPIO, state);
  175. #else /* All other SHCs starting with B2-Sample */
  176. /* Set the PWM GPIO */
  177. gpio_direction_output(LED_PWM_GPIO, 1);
  178. /* Turn all blue LEDs off */
  179. gpio_set_value(LED_PWR_BL_GPIO, 0);
  180. gpio_set_value(LED_LAN_BL_GPIO, 0);
  181. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  182. /* Turn all red LEDs to 'state' */
  183. gpio_set_value(LED_PWR_RD_GPIO, state);
  184. gpio_set_value(LED_LAN_RD_GPIO, state);
  185. gpio_set_value(LED_CLOUD_RD_GPIO, state);
  186. #endif
  187. }
  188. /*
  189. * Function to set the LEDs in the state "Bootloader finished"
  190. */
  191. static void leds_set_finish(void)
  192. {
  193. #if defined(CONFIG_B_SAMPLE)
  194. /* Turn all LEDs off */
  195. gpio_set_value(LED_PWR_BL_GPIO, 0);
  196. gpio_set_value(LED_PWR_RD_GPIO, 0);
  197. gpio_set_value(LED_PWR_GN_GPIO, 0);
  198. gpio_set_value(LED_CONN_BL_GPIO, 0);
  199. gpio_set_value(LED_CONN_RD_GPIO, 0);
  200. gpio_set_value(LED_CONN_GN_GPIO, 0);
  201. #else /* All other SHCs starting with B2-Sample */
  202. /* Turn all LEDs off */
  203. gpio_set_value(LED_PWR_BL_GPIO, 0);
  204. gpio_set_value(LED_PWR_RD_GPIO, 0);
  205. gpio_set_value(LED_LAN_BL_GPIO, 0);
  206. gpio_set_value(LED_LAN_RD_GPIO, 0);
  207. gpio_set_value(LED_CLOUD_BL_GPIO, 0);
  208. gpio_set_value(LED_CLOUD_RD_GPIO, 0);
  209. /* Turn off the PWM GPIO and mux it to EHRPWM */
  210. gpio_set_value(LED_PWM_GPIO, 0);
  211. enable_shc_board_pwm_pin_mux();
  212. #endif
  213. }
  214. static void check_button_status(void)
  215. {
  216. ulong value;
  217. gpio_direction_input(FRONT_BUTTON_GPIO);
  218. value = gpio_get_value(FRONT_BUTTON_GPIO);
  219. if (value == 0) {
  220. printf("front button activated !\n");
  221. env_set("harakiri", "1");
  222. }
  223. }
  224. #if defined(CONFIG_SPL_BUILD)
  225. #ifdef CONFIG_SPL_OS_BOOT
  226. int spl_start_uboot(void)
  227. {
  228. return 1;
  229. }
  230. #endif
  231. static void shc_board_early_init(void)
  232. {
  233. shc_request_gpio();
  234. # ifdef CONFIG_SHC_ICT
  235. /* Force all modules into enabled state for ICT testing */
  236. force_modules_running();
  237. # else
  238. /* Force all modules to enter Reset state until released by the OS */
  239. force_modules_reset();
  240. # endif
  241. leds_set_booting();
  242. }
  243. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  244. #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
  245. #define OSC (V_OSCK/1000000)
  246. /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
  247. #define MPUPLL_N (4-1)
  248. /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
  249. #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
  250. const struct dpll_params dpll_ddr_shc = {
  251. 400, OSC-1, 1, -1, -1, -1, -1};
  252. const struct dpll_params *get_dpll_ddr_params(void)
  253. {
  254. return &dpll_ddr_shc;
  255. }
  256. /*
  257. * As we enabled downspread SSC with 1.8%, the values needed to be corrected
  258. * such that the 20% overshoot will not lead to too high frequencies.
  259. * In all cases, this is achieved by subtracting one from M (6 MHz less).
  260. * Example: 600 MHz CPU
  261. * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
  262. * 600 MHz - 6 MHz (1x Fref) = 594 MHz
  263. * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
  264. * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
  265. * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
  266. */
  267. const struct dpll_params dpll_mpu_shc_opp100 = {
  268. 99, MPUPLL_N, 1, -1, -1, -1, -1};
  269. void am33xx_spl_board_init(void)
  270. {
  271. int sil_rev;
  272. int mpu_vdd;
  273. puts(BOARD_ID_STR);
  274. /*
  275. * Set CORE Frequency to OPP100
  276. * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
  277. */
  278. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  279. sil_rev = readl(&cdev->deviceid) >> 28;
  280. if (sil_rev < 2) {
  281. puts("We do not support Silicon Revisions below 2.0!\n");
  282. return;
  283. }
  284. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  285. if (i2c_probe(TPS65217_CHIP_PM))
  286. return;
  287. /*
  288. * Retrieve the CPU max frequency by reading the efuse
  289. * SHC-Default: 600 MHz
  290. */
  291. switch (dpll_mpu_opp100.m) {
  292. case MPUPLL_M_1000:
  293. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  294. break;
  295. case MPUPLL_M_800:
  296. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  297. break;
  298. case MPUPLL_M_720:
  299. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  300. break;
  301. case MPUPLL_M_600:
  302. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  303. break;
  304. case MPUPLL_M_300:
  305. mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
  306. break;
  307. default:
  308. puts("Cannot determine the frequency, failing!\n");
  309. return;
  310. }
  311. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  312. puts("tps65217_voltage_update failure\n");
  313. return;
  314. }
  315. /* Set MPU Frequency to what we detected */
  316. printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
  317. printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
  318. dpll_mpu_shc_opp100.m);
  319. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
  320. /* Enable Spread Spectrum for this freq to be clean on EMI side */
  321. set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
  322. /*
  323. * Using the default voltages for the PMIC (TPS65217D)
  324. * LS1 = 1.8V (VDD_1V8)
  325. * LS2 = 3.3V (VDD_3V3A)
  326. * LDO1 = 1.8V (VIO and VRTC)
  327. * LDO2 = 3.3V (VDD_3V3AUX)
  328. */
  329. shc_board_early_init();
  330. }
  331. void set_uart_mux_conf(void)
  332. {
  333. enable_uart0_pin_mux();
  334. }
  335. void set_mux_conf_regs(void)
  336. {
  337. enable_shc_board_pin_mux();
  338. }
  339. const struct ctrl_ioregs ioregs_evmsk = {
  340. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  341. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  342. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  343. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  344. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  345. };
  346. static const struct ddr_data ddr3_shc_data = {
  347. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  348. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  349. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  350. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  351. };
  352. static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
  353. .cmd0csratio = MT41K256M16HA125E_RATIO,
  354. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  355. .cmd1csratio = MT41K256M16HA125E_RATIO,
  356. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  357. .cmd2csratio = MT41K256M16HA125E_RATIO,
  358. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  359. };
  360. static struct emif_regs ddr3_shc_emif_reg_data = {
  361. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  362. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  363. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  364. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  365. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  366. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  367. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
  368. PHY_EN_DYN_PWRDN,
  369. };
  370. void sdram_init(void)
  371. {
  372. /* Configure the DDR3 RAM */
  373. config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
  374. &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
  375. }
  376. #endif
  377. /*
  378. * Basic board specific setup. Pinmux has been handled already.
  379. */
  380. int board_init(void)
  381. {
  382. #if defined(CONFIG_HW_WATCHDOG)
  383. hw_watchdog_init();
  384. #endif
  385. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  386. if (read_eeprom() < 0)
  387. puts("EEPROM Content Invalid.\n");
  388. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  389. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  390. gpmc_init();
  391. #endif
  392. shc_request_gpio();
  393. return 0;
  394. }
  395. #ifdef CONFIG_BOARD_LATE_INIT
  396. int board_late_init(void)
  397. {
  398. check_button_status();
  399. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  400. if (shc_eeprom_valid)
  401. if (is_valid_ethaddr(header.mac_addr))
  402. eth_env_set_enetaddr("ethaddr", header.mac_addr);
  403. #endif
  404. return 0;
  405. }
  406. #endif
  407. #if defined(CONFIG_USB_ETHER) && \
  408. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
  409. int board_eth_init(struct bd_info *bis)
  410. {
  411. return usb_eth_initialize(bis);
  412. }
  413. #endif
  414. #ifdef CONFIG_SHOW_BOOT_PROGRESS
  415. static void bosch_check_reset_pin(void)
  416. {
  417. if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
  418. printf("Resetting ...\n");
  419. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  420. disable_interrupts();
  421. reset_cpu(0);
  422. /*NOTREACHED*/
  423. }
  424. }
  425. static void hang_bosch(const char *cause, int code)
  426. {
  427. int lv;
  428. gpio_direction_input(RESET_GPIO);
  429. /* Enable reset pin interrupt on falling edge */
  430. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
  431. writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
  432. enable_interrupts();
  433. puts(cause);
  434. for (;;) {
  435. for (lv = 0; lv < code; lv++) {
  436. bosch_check_reset_pin();
  437. leds_set_failure(1);
  438. __udelay(150 * 1000);
  439. leds_set_failure(0);
  440. __udelay(150 * 1000);
  441. }
  442. #if defined(BLINK_CODE)
  443. __udelay(300 * 1000);
  444. #endif
  445. }
  446. }
  447. void show_boot_progress(int val)
  448. {
  449. switch (val) {
  450. case BOOTSTAGE_ID_NEED_RESET:
  451. hang_bosch("need reset", 4);
  452. break;
  453. }
  454. }
  455. void arch_preboot_os(void)
  456. {
  457. leds_set_finish();
  458. }
  459. #endif