apx4devkit.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Bluegiga APX4 Development Kit
  4. *
  5. * Copyright (C) 2012 Bluegiga Technologies Oy
  6. *
  7. * Authors:
  8. * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
  9. * Lauri Hintsala <lauri.hintsala@bluegiga.com>
  10. *
  11. * Based on m28evk.c:
  12. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  13. * on behalf of DENX Software Engineering GmbH
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <net.h>
  18. #include <asm/gpio.h>
  19. #include <asm/io.h>
  20. #include <asm/setup.h>
  21. #include <asm/arch/imx-regs.h>
  22. #include <asm/arch/iomux-mx28.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <env.h>
  26. #include <linux/mii.h>
  27. #include <miiphy.h>
  28. #include <netdev.h>
  29. #include <errno.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /* Functions */
  32. int board_early_init_f(void)
  33. {
  34. /* IO0 clock at 480MHz */
  35. mxs_set_ioclk(MXC_IOCLK0, 480000);
  36. /* IO1 clock at 480MHz */
  37. mxs_set_ioclk(MXC_IOCLK1, 480000);
  38. /* SSP0 clock at 96MHz */
  39. mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
  40. return 0;
  41. }
  42. int dram_init(void)
  43. {
  44. return mxs_dram_init();
  45. }
  46. int board_init(void)
  47. {
  48. /* Adress of boot parameters */
  49. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  50. return 0;
  51. }
  52. #ifdef CONFIG_CMD_MMC
  53. int board_mmc_init(struct bd_info *bis)
  54. {
  55. return mxsmmc_initialize(bis, 0, NULL, NULL);
  56. }
  57. #endif
  58. #ifdef CONFIG_CMD_NET
  59. #define MII_PHY_CTRL2 0x1f
  60. int fecmxc_mii_postcall(int phy)
  61. {
  62. /* change PHY RMII clock to 50MHz */
  63. miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
  64. return 0;
  65. }
  66. int board_eth_init(struct bd_info *bis)
  67. {
  68. int ret;
  69. struct eth_device *dev;
  70. ret = cpu_eth_init(bis);
  71. if (ret) {
  72. printf("FEC MXS: Unable to init FEC clocks\n");
  73. return ret;
  74. }
  75. ret = fecmxc_initialize(bis);
  76. if (ret) {
  77. printf("FEC MXS: Unable to init FEC\n");
  78. return ret;
  79. }
  80. dev = eth_get_dev_by_name("FEC");
  81. if (!dev) {
  82. printf("FEC MXS: Unable to get FEC device entry\n");
  83. return -EINVAL;
  84. }
  85. ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
  86. if (ret) {
  87. printf("FEC MXS: Unable to register FEC MII postcall\n");
  88. return ret;
  89. }
  90. return ret;
  91. }
  92. #endif
  93. #ifdef CONFIG_SERIAL_TAG
  94. #define MXS_OCOTP_MAX_TIMEOUT 1000000
  95. void get_board_serial(struct tag_serialnr *serialnr)
  96. {
  97. struct mxs_ocotp_regs *ocotp_regs =
  98. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  99. serialnr->high = 0;
  100. serialnr->low = 0;
  101. writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
  102. if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
  103. MXS_OCOTP_MAX_TIMEOUT)) {
  104. printf("MXS: Can't get serial number from OCOTP\n");
  105. return;
  106. }
  107. serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
  108. }
  109. #endif
  110. #ifdef CONFIG_REVISION_TAG
  111. u32 get_board_rev(void)
  112. {
  113. if (env_get("revision#") != NULL)
  114. return simple_strtoul(env_get("revision#"), NULL, 10);
  115. return 0;
  116. }
  117. #endif