titanium.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <init.h>
  7. #include <net.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <mmc.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <micrel.h>
  22. #include <miiphy.h>
  23. #include <netdev.h>
  24. #include <linux/delay.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  27. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  28. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  29. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  30. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  31. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  32. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  33. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  34. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  35. int dram_init(void)
  36. {
  37. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  38. return 0;
  39. }
  40. iomux_v3_cfg_t const uart1_pads[] = {
  41. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  42. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  43. };
  44. iomux_v3_cfg_t const uart2_pads[] = {
  45. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  46. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  47. };
  48. iomux_v3_cfg_t const uart4_pads[] = {
  49. MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  50. MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  51. };
  52. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  53. struct i2c_pads_info i2c_pad_info0 = {
  54. .scl = {
  55. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
  56. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  57. .gp = IMX_GPIO_NR(5, 27)
  58. },
  59. .sda = {
  60. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  61. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  62. .gp = IMX_GPIO_NR(5, 26)
  63. }
  64. };
  65. struct i2c_pads_info i2c_pad_info2 = {
  66. .scl = {
  67. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
  68. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
  69. .gp = IMX_GPIO_NR(1, 3)
  70. },
  71. .sda = {
  72. .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
  73. .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
  74. .gp = IMX_GPIO_NR(7, 11)
  75. }
  76. };
  77. iomux_v3_cfg_t const usdhc3_pads[] = {
  78. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  85. };
  86. iomux_v3_cfg_t const enet_pads1[] = {
  87. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96. /* pin 35 - 1 (PHY_AD2) on reset */
  97. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  98. /* pin 32 - 1 - (MODE0) all */
  99. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  100. /* pin 31 - 1 - (MODE1) all */
  101. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. /* pin 28 - 1 - (MODE2) all */
  103. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  104. /* pin 27 - 1 - (MODE3) all */
  105. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  106. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  107. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  108. /* pin 42 PHY nRST */
  109. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  110. };
  111. iomux_v3_cfg_t const enet_pads2[] = {
  112. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  113. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  114. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  115. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  116. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  117. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  118. };
  119. iomux_v3_cfg_t nfc_pads[] = {
  120. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
  121. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
  122. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  123. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  124. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  125. MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  126. MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  127. MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  129. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  130. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  131. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  132. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  133. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  134. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  135. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  136. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  137. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  138. MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
  139. };
  140. static void setup_gpmi_nand(void)
  141. {
  142. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  143. /* config gpmi nand iomux */
  144. imx_iomux_v3_setup_multiple_pads(nfc_pads,
  145. ARRAY_SIZE(nfc_pads));
  146. /* config gpmi and bch clock to 100 MHz */
  147. clrsetbits_le32(&mxc_ccm->cs2cdr,
  148. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  149. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  150. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  151. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  152. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  153. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  154. /* enable gpmi and bch clock gating */
  155. setbits_le32(&mxc_ccm->CCGR4,
  156. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  157. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  158. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  159. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  160. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  161. /* enable apbh clock gating */
  162. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  163. }
  164. static void setup_iomux_enet(void)
  165. {
  166. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  167. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  168. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  169. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  170. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  171. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  172. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  173. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  174. /* Need delay 10ms according to KSZ9021 spec */
  175. udelay(1000 * 10);
  176. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  177. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  178. }
  179. static void setup_iomux_uart(void)
  180. {
  181. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  182. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  183. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  184. }
  185. #ifdef CONFIG_USB_EHCI_MX6
  186. int board_ehci_hcd_init(int port)
  187. {
  188. return 0;
  189. }
  190. #endif
  191. #ifdef CONFIG_FSL_ESDHC_IMX
  192. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  193. { USDHC3_BASE_ADDR },
  194. };
  195. int board_mmc_getcd(struct mmc *mmc)
  196. {
  197. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  198. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  199. gpio_direction_input(IMX_GPIO_NR(7, 0));
  200. return !gpio_get_value(IMX_GPIO_NR(7, 0));
  201. }
  202. return 0;
  203. }
  204. int board_mmc_init(struct bd_info *bis)
  205. {
  206. /*
  207. * Only one USDHC controller on titianium
  208. */
  209. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  210. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  211. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  212. }
  213. #endif
  214. int board_phy_config(struct phy_device *phydev)
  215. {
  216. /* min rx data delay */
  217. ksz9021_phy_extended_write(phydev,
  218. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  219. /* min tx data delay */
  220. ksz9021_phy_extended_write(phydev,
  221. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  222. /* max rx/tx clock delay, min rx/tx control */
  223. ksz9021_phy_extended_write(phydev,
  224. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  225. if (phydev->drv->config)
  226. phydev->drv->config(phydev);
  227. return 0;
  228. }
  229. int board_eth_init(struct bd_info *bis)
  230. {
  231. setup_iomux_enet();
  232. return cpu_eth_init(bis);
  233. }
  234. int board_early_init_f(void)
  235. {
  236. setup_iomux_uart();
  237. return 0;
  238. }
  239. int board_init(void)
  240. {
  241. /* address of boot parameters */
  242. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  243. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  244. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  245. setup_gpmi_nand();
  246. return 0;
  247. }
  248. int checkboard(void)
  249. {
  250. puts("Board: Titanium\n");
  251. return 0;
  252. }
  253. #ifdef CONFIG_CMD_BMODE
  254. static const struct boot_mode board_boot_modes[] = {
  255. /* NAND */
  256. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  257. /* 4 bit bus width */
  258. { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
  259. { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
  260. { NULL, 0 },
  261. };
  262. #endif
  263. int misc_init_r(void)
  264. {
  265. #ifdef CONFIG_CMD_BMODE
  266. add_board_boot_modes(board_boot_modes);
  267. #endif
  268. return 0;
  269. }