spl_picon.c 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  4. *
  5. * Based on: gw_ventana_spl.c which is:
  6. * Copyright (C) 2014 Gateworks Corporation
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <spl.h>
  20. #include "platinum.h"
  21. #undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  22. /* Configure MX6Q/DUAL mmdc DDR io registers */
  23. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  24. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  25. .dram_sdclk_0 = 0x00020030,
  26. .dram_sdclk_1 = 0x00020030,
  27. .dram_cas = 0x00020030,
  28. .dram_ras = 0x00020030,
  29. .dram_reset = 0x00020030,
  30. /* SDCKE[0:1]: 100k pull-up */
  31. .dram_sdcke0 = 0x00003000,
  32. .dram_sdcke1 = 0x00003000,
  33. /* SDBA2: pull-up disabled */
  34. .dram_sdba2 = 0x00000000,
  35. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  36. .dram_sdodt0 = 0x00003030,
  37. .dram_sdodt1 = 0x00003030,
  38. /* SDQS[0:7]: Differential input, 40 ohm */
  39. .dram_sdqs0 = 0x00000030,
  40. .dram_sdqs1 = 0x00000030,
  41. .dram_sdqs2 = 0x00000030,
  42. .dram_sdqs3 = 0x00000030,
  43. .dram_sdqs4 = 0x00000030,
  44. .dram_sdqs5 = 0x00000030,
  45. .dram_sdqs6 = 0x00000030,
  46. .dram_sdqs7 = 0x00000030,
  47. /* DQM[0:7]: Differential input, 40 ohm */
  48. .dram_dqm0 = 0x00020030,
  49. .dram_dqm1 = 0x00020030,
  50. .dram_dqm2 = 0x00020030,
  51. .dram_dqm3 = 0x00020030,
  52. .dram_dqm4 = 0x00020030,
  53. .dram_dqm5 = 0x00020030,
  54. .dram_dqm6 = 0x00020030,
  55. .dram_dqm7 = 0x00020030,
  56. };
  57. /* Configure MX6Q/DUAL mmdc GRP io registers */
  58. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  59. /* DDR3 */
  60. .grp_ddr_type = 0x000c0000,
  61. .grp_ddrmode_ctl = 0x00020000,
  62. /* disable DDR pullups */
  63. .grp_ddrpke = 0x00000000,
  64. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  65. .grp_addds = 0x00000030,
  66. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  67. .grp_ctlds = 0x00000030,
  68. /* DATA[00:63]: Differential input, 40 ohm */
  69. .grp_ddrmode = 0x00020000,
  70. .grp_b0ds = 0x00000030,
  71. .grp_b1ds = 0x00000030,
  72. .grp_b2ds = 0x00000030,
  73. .grp_b3ds = 0x00000030,
  74. .grp_b4ds = 0x00000030,
  75. .grp_b5ds = 0x00000030,
  76. .grp_b6ds = 0x00000030,
  77. .grp_b7ds = 0x00000030,
  78. };
  79. /* MT41K256M16HA-125 */
  80. static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
  81. .mem_speed = 1600,
  82. .density = 4, /* 4Gbit */
  83. .width = 16,
  84. .banks = 8,
  85. .rowaddr = 15,
  86. .coladdr = 10,
  87. .pagesz = 2,
  88. .trcd = 1375,
  89. .trcmin = 4875,
  90. .trasmin = 3500,
  91. };
  92. /*
  93. * Values from running the Freescale DDR stress tool via USB
  94. */
  95. static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
  96. /* write leveling calibration determine */
  97. .p0_mpwldectrl0 = 0x0044004E,
  98. .p0_mpwldectrl1 = 0x001F0023,
  99. /* Read DQS Gating calibration */
  100. .p0_mpdgctrl0 = 0x02480248,
  101. .p0_mpdgctrl1 = 0x0210021C,
  102. /* Read Calibration: DQS delay relative to DQ read access */
  103. .p0_mprddlctl = 0x42444444,
  104. /* Write Calibration: DQ/DM delay relative to DQS write access */
  105. .p0_mpwrdlctl = 0x36322C32,
  106. };
  107. static void spl_dram_init(int width)
  108. {
  109. struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125;
  110. struct mx6_ddr_sysinfo sysinfo = {
  111. /* width of data bus:0=16,1=32,2=64 */
  112. .dsize = width / 32,
  113. /* config for full 4GB range so that get_mem_size() works */
  114. .cs_density = 32, /* 32Gb per CS */
  115. /* single chip select */
  116. .ncs = 1,
  117. .cs1_mirror = 1,
  118. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  119. #ifdef RTT_NOM_120OHM
  120. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  121. #else
  122. .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
  123. #endif
  124. .walat = 0, /* Write additional latency */
  125. .ralat = 5, /* Read additional latency */
  126. .mif3_mode = 3, /* Command prediction working mode */
  127. .bi_on = 1, /* Bank interleaving enabled */
  128. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  129. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  130. .ddr_type = DDR_TYPE_DDR3,
  131. .refsel = 1, /* Refresh cycles at 32KHz */
  132. .refr = 7, /* 8 refresh commands per refresh cycle */
  133. };
  134. mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  135. mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
  136. }
  137. /*
  138. * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  139. * - we have a stack and a place to store GD, both in SRAM
  140. * - no variable global data is available
  141. */
  142. void board_init_f(ulong dummy)
  143. {
  144. /* Setup AIPS and disable watchdog */
  145. arch_cpu_init();
  146. ccgr_init();
  147. gpr_init();
  148. /* UART iomux */
  149. board_early_init_f();
  150. /* Setup GP timer */
  151. timer_init();
  152. /* UART clocks enabled and gd valid - init serial console */
  153. preloader_console_init();
  154. /* Init DDR with 32bit width */
  155. spl_dram_init(32);
  156. /* Clear the BSS */
  157. memset(__bss_start, 0, __bss_end - __bss_start);
  158. /*
  159. * Setup enet related MUXing early to give the PHY
  160. * some time to wake-up from reset
  161. */
  162. platinum_setup_enet();
  163. /* load/boot image from boot device */
  164. board_init_r(NULL, 0);
  165. }