platinum_titanium.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Barco (www.barco.com)
  4. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  5. */
  6. #include <common.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/mx6-pins.h>
  9. #include <asm/gpio.h>
  10. #include <asm/mach-imx/iomux-v3.h>
  11. #include <asm/mach-imx/mxc_i2c.h>
  12. #include <miiphy.h>
  13. #include <micrel.h>
  14. #include <linux/delay.h>
  15. #include "platinum.h"
  16. iomux_v3_cfg_t const ecspi1_pads[] = {
  17. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
  18. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
  19. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
  20. MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  21. /* non mounted spi nor flash for booting */
  22. MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  23. MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  24. MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  25. };
  26. iomux_v3_cfg_t const ecspi2_pads[] = {
  27. MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
  28. MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
  29. MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
  30. MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
  31. };
  32. iomux_v3_cfg_t const enet_pads1[] = {
  33. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  34. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  35. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  36. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  37. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  38. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  39. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  40. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  41. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  42. /* pin 35 - 1 (PHY_AD2) on reset */
  43. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  44. /* pin 32 - 1 - (MODE0) all */
  45. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  46. /* pin 31 - 1 - (MODE1) all */
  47. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  48. /* pin 28 - 1 - (MODE2) all */
  49. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  50. /* pin 27 - 1 - (MODE3) all */
  51. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  52. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  53. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  54. /* pin 42 PHY nRST */
  55. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  56. };
  57. iomux_v3_cfg_t const enet_pads2[] = {
  58. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64. };
  65. iomux_v3_cfg_t const uart1_pads[] = {
  66. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  67. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68. };
  69. iomux_v3_cfg_t const uart2_pads[] = {
  70. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  71. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72. MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  73. MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  74. };
  75. iomux_v3_cfg_t const uart4_pads[] = {
  76. MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77. MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78. MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  79. MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  80. };
  81. struct i2c_pads_info i2c_pad_info0 = {
  82. .scl = {
  83. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
  84. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
  85. .gp = IMX_GPIO_NR(5, 27)
  86. },
  87. .sda = {
  88. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  89. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  90. .gp = IMX_GPIO_NR(5, 26)
  91. }
  92. };
  93. struct i2c_pads_info i2c_pad_info2 = {
  94. .scl = {
  95. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
  96. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
  97. .gp = IMX_GPIO_NR(1, 3)
  98. },
  99. .sda = {
  100. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  101. .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
  102. .gp = IMX_GPIO_NR(7, 11)
  103. }
  104. };
  105. /*
  106. * This enet related pin-muxing and GPIO handling is done
  107. * in SPL U-Boot. For early initialization. And to give the
  108. * PHY some time to come out of reset before the U-Boot
  109. * ethernet driver tries to access its registers via MDIO.
  110. */
  111. int platinum_setup_enet(void)
  112. {
  113. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  114. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  115. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  116. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  117. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  118. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  119. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  120. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  121. /* Need delay 10ms according to KSZ9021 spec */
  122. mdelay(10);
  123. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  124. udelay(100);
  125. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  126. return 0;
  127. }
  128. int platinum_setup_i2c(void)
  129. {
  130. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  131. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  132. return 0;
  133. }
  134. int platinum_setup_spi(void)
  135. {
  136. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  137. imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
  138. return 0;
  139. }
  140. int platinum_setup_uart(void)
  141. {
  142. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  143. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  144. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  145. return 0;
  146. }
  147. int platinum_phy_config(struct phy_device *phydev)
  148. {
  149. /* min rx data delay */
  150. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  151. 0x0);
  152. /* min tx data delay */
  153. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
  154. 0x0);
  155. /* max rx/tx clock delay, min rx/tx control */
  156. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  157. 0xf0f0);
  158. if (phydev->drv->config)
  159. phydev->drv->config(phydev);
  160. return 0;
  161. }
  162. int platinum_init_gpio(void)
  163. {
  164. /* Default GPIO's */
  165. /* Toggle CONFIG_n to reset fpga on every boot */
  166. gpio_direction_output(IMX_GPIO_NR(5, 18), 0);
  167. /* Need delay >=2uS */
  168. udelay(3);
  169. gpio_set_value(IMX_GPIO_NR(5, 18), 1);
  170. /* Default pin 1,15 high - DLP_FLASH_WPZ */
  171. gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
  172. return 0;
  173. }
  174. int platinum_init_usb(void)
  175. {
  176. return 0;
  177. }
  178. int platinum_init_finished(void)
  179. {
  180. return 0;
  181. }