platinum.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Barco (www.barco.com)
  4. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <mmc.h>
  9. #include <fsl_esdhc_imx.h>
  10. #include <miiphy.h>
  11. #include <net.h>
  12. #include <netdev.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/iomux.h>
  17. #include <asm/arch/mx6-pins.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/gpio.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/boot_mode.h>
  23. #include "platinum.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. iomux_v3_cfg_t const usdhc3_pads[] = {
  26. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  27. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  28. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  29. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  30. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  31. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  32. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  33. };
  34. iomux_v3_cfg_t nfc_pads[] = {
  35. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
  36. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
  37. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  38. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  39. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  40. MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  41. MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  42. MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  43. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  44. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  45. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  46. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  47. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  48. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  49. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  50. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  51. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  52. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  53. MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
  54. };
  55. struct fsl_esdhc_cfg usdhc_cfg[] = {
  56. { USDHC3_BASE_ADDR },
  57. };
  58. void setup_gpmi_nand(void)
  59. {
  60. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  61. /* config gpmi nand iomux */
  62. imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
  63. /* config gpmi and bch clock to 100 MHz */
  64. clrsetbits_le32(&mxc_ccm->cs2cdr,
  65. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  66. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  67. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  68. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  69. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  70. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  71. /* enable gpmi and bch clock gating */
  72. setbits_le32(&mxc_ccm->CCGR4,
  73. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  74. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  75. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  76. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  77. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  78. /* enable apbh clock gating */
  79. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  80. }
  81. int dram_init(void)
  82. {
  83. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  84. return 0;
  85. }
  86. int board_ehci_hcd_init(int port)
  87. {
  88. return 0;
  89. }
  90. int board_mmc_getcd(struct mmc *mmc)
  91. {
  92. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  93. if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
  94. unsigned sd3_cd = IMX_GPIO_NR(7, 0);
  95. gpio_direction_input(sd3_cd);
  96. return !gpio_get_value(sd3_cd);
  97. }
  98. return 0;
  99. }
  100. int board_mmc_init(struct bd_info *bis)
  101. {
  102. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  103. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  104. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  105. }
  106. void board_init_gpio(void)
  107. {
  108. platinum_init_gpio();
  109. }
  110. void board_init_gpmi_nand(void)
  111. {
  112. setup_gpmi_nand();
  113. }
  114. void board_init_i2c(void)
  115. {
  116. platinum_setup_i2c();
  117. }
  118. void board_init_spi(void)
  119. {
  120. platinum_setup_spi();
  121. }
  122. void board_init_uart(void)
  123. {
  124. platinum_setup_uart();
  125. }
  126. void board_init_usb(void)
  127. {
  128. platinum_init_usb();
  129. }
  130. void board_init_finished(void)
  131. {
  132. platinum_init_finished();
  133. }
  134. int board_phy_config(struct phy_device *phydev)
  135. {
  136. return platinum_phy_config(phydev);
  137. }
  138. int board_eth_init(struct bd_info *bis)
  139. {
  140. return cpu_eth_init(bis);
  141. }
  142. int board_early_init_f(void)
  143. {
  144. board_init_uart();
  145. return 0;
  146. }
  147. int board_init(void)
  148. {
  149. /* address of boot parameters */
  150. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  151. board_init_spi();
  152. board_init_i2c();
  153. board_init_gpmi_nand();
  154. board_init_gpio();
  155. board_init_usb();
  156. board_init_finished();
  157. return 0;
  158. }
  159. int checkboard(void)
  160. {
  161. puts("Board: " CONFIG_PLATINUM_BOARD "\n");
  162. return 0;
  163. }
  164. static const struct boot_mode board_boot_modes[] = {
  165. /* NAND */
  166. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  167. /* 4 bit bus width */
  168. { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
  169. { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
  170. { NULL, 0 },
  171. };
  172. int misc_init_r(void)
  173. {
  174. add_board_boot_modes(board_boot_modes);
  175. return 0;
  176. }