ot1200.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2014, Bachmann electronic GmbH
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux.h>
  13. #include <env.h>
  14. #include <malloc.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/sata.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <mmc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <netdev.h>
  25. #include <i2c.h>
  26. #include <pca953x.h>
  27. #include <asm/gpio.h>
  28. #include <phy.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  31. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  32. OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  34. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  35. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
  37. PAD_CTL_HYS)
  38. #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
  39. PAD_CTL_SRE_FAST)
  40. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
  41. PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  42. int dram_init(void)
  43. {
  44. gd->ram_size = imx_ddr_size();
  45. return 0;
  46. }
  47. static iomux_v3_cfg_t const uart1_pads[] = {
  48. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  49. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  50. };
  51. static void setup_iomux_uart(void)
  52. {
  53. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  54. }
  55. static iomux_v3_cfg_t const enet_pads[] = {
  56. MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57. MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61. MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62. MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63. MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64. MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65. MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66. MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68. MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69. MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. };
  74. static void setup_iomux_enet(void)
  75. {
  76. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  77. }
  78. static iomux_v3_cfg_t const ecspi1_pads[] = {
  79. MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  80. MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  81. MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  82. MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  83. MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  84. };
  85. static void setup_iomux_spi(void)
  86. {
  87. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  88. }
  89. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  90. {
  91. return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
  92. }
  93. static iomux_v3_cfg_t const feature_pads[] = {
  94. /* SD card detect */
  95. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
  96. /* eMMC soldered? */
  97. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
  98. };
  99. static void setup_iomux_features(void)
  100. {
  101. imx_iomux_v3_setup_multiple_pads(feature_pads,
  102. ARRAY_SIZE(feature_pads));
  103. }
  104. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  105. /* I2C2 - EEPROM */
  106. static struct i2c_pads_info i2c_pad_info1 = {
  107. .scl = {
  108. .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  109. .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  110. .gp = IMX_GPIO_NR(2, 30)
  111. },
  112. .sda = {
  113. .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
  114. .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
  115. .gp = IMX_GPIO_NR(3, 16)
  116. }
  117. };
  118. /* I2C3 - IO expander */
  119. static struct i2c_pads_info i2c_pad_info2 = {
  120. .scl = {
  121. .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  122. .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  123. .gp = IMX_GPIO_NR(3, 17)
  124. },
  125. .sda = {
  126. .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  127. .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  128. .gp = IMX_GPIO_NR(3, 18)
  129. }
  130. };
  131. static void setup_iomux_i2c(void)
  132. {
  133. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  134. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  135. }
  136. static void ccgr_init(void)
  137. {
  138. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  139. writel(0x00C03F3F, &ccm->CCGR0);
  140. writel(0x0030FC33, &ccm->CCGR1);
  141. writel(0x0FFFC000, &ccm->CCGR2);
  142. writel(0x3FF00000, &ccm->CCGR3);
  143. writel(0x00FFF300, &ccm->CCGR4);
  144. writel(0x0F0000C3, &ccm->CCGR5);
  145. writel(0x000003FF, &ccm->CCGR6);
  146. }
  147. int board_early_init_f(void)
  148. {
  149. ccgr_init();
  150. gpr_init();
  151. setup_iomux_uart();
  152. setup_iomux_spi();
  153. setup_iomux_i2c();
  154. setup_iomux_features();
  155. return 0;
  156. }
  157. static iomux_v3_cfg_t const usdhc3_pads[] = {
  158. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  159. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  160. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  161. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  162. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  163. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  164. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  165. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  166. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  167. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  168. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  169. };
  170. iomux_v3_cfg_t const usdhc4_pads[] = {
  171. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  172. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  173. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  174. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  175. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  176. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  177. };
  178. int board_mmc_getcd(struct mmc *mmc)
  179. {
  180. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  181. int ret;
  182. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  183. gpio_direction_input(IMX_GPIO_NR(4, 5));
  184. ret = gpio_get_value(IMX_GPIO_NR(4, 5));
  185. } else {
  186. gpio_direction_input(IMX_GPIO_NR(1, 5));
  187. ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
  188. }
  189. return ret;
  190. }
  191. struct fsl_esdhc_cfg usdhc_cfg[2] = {
  192. {USDHC3_BASE_ADDR},
  193. {USDHC4_BASE_ADDR},
  194. };
  195. int board_mmc_init(struct bd_info *bis)
  196. {
  197. int ret;
  198. u32 index = 0;
  199. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  200. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  201. usdhc_cfg[0].max_bus_width = 8;
  202. usdhc_cfg[1].max_bus_width = 4;
  203. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  204. switch (index) {
  205. case 0:
  206. imx_iomux_v3_setup_multiple_pads(
  207. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  208. break;
  209. case 1:
  210. imx_iomux_v3_setup_multiple_pads(
  211. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  212. break;
  213. default:
  214. printf("Warning: you configured more USDHC controllers"
  215. "(%d) then supported by the board (%d)\n",
  216. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  217. return -EINVAL;
  218. }
  219. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  220. if (ret)
  221. return ret;
  222. }
  223. return 0;
  224. }
  225. static void leds_on(void)
  226. {
  227. /* turn on all possible leds connected via GPIO expander */
  228. i2c_set_bus_num(2);
  229. pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
  230. pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
  231. }
  232. static void backlight_lcd_off(void)
  233. {
  234. unsigned gpio = IMX_GPIO_NR(2, 0);
  235. gpio_direction_output(gpio, 0);
  236. gpio = IMX_GPIO_NR(2, 3);
  237. gpio_direction_output(gpio, 0);
  238. }
  239. int board_eth_init(struct bd_info *bis)
  240. {
  241. uint32_t base = IMX_FEC_BASE;
  242. struct mii_dev *bus = NULL;
  243. struct phy_device *phydev = NULL;
  244. int ret;
  245. setup_iomux_enet();
  246. bus = fec_get_miibus(base, -1);
  247. if (!bus)
  248. return -EINVAL;
  249. /* scan phy 0 and 5 */
  250. phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
  251. if (!phydev) {
  252. ret = -EINVAL;
  253. goto free_bus;
  254. }
  255. /* depending on the phy address we can detect our board version */
  256. if (phydev->addr == 0)
  257. env_set("boardver", "");
  258. else
  259. env_set("boardver", "mr");
  260. printf("using phy at %d\n", phydev->addr);
  261. ret = fec_probe(bis, -1, base, bus, phydev);
  262. if (ret)
  263. goto free_phydev;
  264. return 0;
  265. free_phydev:
  266. free(phydev);
  267. free_bus:
  268. free(bus);
  269. return ret;
  270. }
  271. int board_init(void)
  272. {
  273. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  274. backlight_lcd_off();
  275. leds_on();
  276. #ifdef CONFIG_SATA
  277. setup_sata();
  278. #endif
  279. return 0;
  280. }
  281. int checkboard(void)
  282. {
  283. puts("Board: "CONFIG_SYS_BOARD"\n");
  284. return 0;
  285. }
  286. #ifdef CONFIG_CMD_BMODE
  287. static const struct boot_mode board_boot_modes[] = {
  288. /* 4 bit bus width */
  289. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  290. {NULL, 0},
  291. };
  292. #endif
  293. int misc_init_r(void)
  294. {
  295. #ifdef CONFIG_CMD_BMODE
  296. add_board_boot_modes(board_boot_modes);
  297. #endif
  298. return 0;
  299. }