at91sam9n12ek.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Atmel Corporation
  4. * Josh Wu <josh.wu@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <vsprintf.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/at91sam9x5_matrix.h>
  12. #include <asm/arch/at91sam9_smc.h>
  13. #include <asm/arch/at91_common.h>
  14. #include <asm/arch/at91_rstc.h>
  15. #include <asm/arch/at91_pio.h>
  16. #include <asm/arch/clk.h>
  17. #include <debug_uart.h>
  18. #include <lcd.h>
  19. #include <atmel_hlcdc.h>
  20. #include <netdev.h>
  21. #ifdef CONFIG_LCD_INFO
  22. #include <nand.h>
  23. #include <version.h>
  24. #endif
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /* ------------------------------------------------------------------------- */
  27. /*
  28. * Miscelaneous platform dependent initialisations
  29. */
  30. #ifdef CONFIG_NAND_ATMEL
  31. static void at91sam9n12ek_nand_hw_init(void)
  32. {
  33. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  34. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  35. unsigned long csa;
  36. /* Assign CS3 to NAND/SmartMedia Interface */
  37. csa = readl(&matrix->ebicsa);
  38. csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  39. /* Configure databus */
  40. csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
  41. /* Configure IO drive */
  42. csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  43. writel(csa, &matrix->ebicsa);
  44. /* Configure SMC CS3 for NAND/SmartMedia */
  45. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  46. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  47. &smc->cs[3].setup);
  48. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  49. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  50. &smc->cs[3].pulse);
  51. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
  52. &smc->cs[3].cycle);
  53. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  54. AT91_SMC_MODE_EXNW_DISABLE |
  55. #ifdef CONFIG_SYS_NAND_DBW_16
  56. AT91_SMC_MODE_DBW_16 |
  57. #else /* CONFIG_SYS_NAND_DBW_8 */
  58. AT91_SMC_MODE_DBW_8 |
  59. #endif
  60. AT91_SMC_MODE_TDF_CYCLE(1),
  61. &smc->cs[3].mode);
  62. /* Configure RDY/BSY pin */
  63. at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
  64. /* Configure ENABLE pin for NandFlash */
  65. at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
  66. at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
  67. at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
  68. at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
  69. at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
  70. }
  71. #endif
  72. #ifdef CONFIG_LCD
  73. vidinfo_t panel_info = {
  74. .vl_col = 480,
  75. .vl_row = 272,
  76. .vl_clk = 9000000,
  77. .vl_bpix = LCD_BPP,
  78. .vl_sync = 0,
  79. .vl_tft = 1,
  80. .vl_hsync_len = 5,
  81. .vl_left_margin = 8,
  82. .vl_right_margin = 43,
  83. .vl_vsync_len = 10,
  84. .vl_upper_margin = 4,
  85. .vl_lower_margin = 12,
  86. .mmio = ATMEL_BASE_LCDC,
  87. };
  88. void lcd_enable(void)
  89. {
  90. at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
  91. }
  92. void lcd_disable(void)
  93. {
  94. at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
  95. }
  96. #ifdef CONFIG_LCD_INFO
  97. void lcd_show_board_info(void)
  98. {
  99. ulong dram_size, nand_size;
  100. int i;
  101. char temp[32];
  102. lcd_printf("%s\n", U_BOOT_VERSION);
  103. lcd_printf("ATMEL Corp\n");
  104. lcd_printf("at91@atmel.com\n");
  105. lcd_printf("%s CPU at %s MHz\n",
  106. ATMEL_CPU_NAME,
  107. strmhz(temp, get_cpu_clk_rate()));
  108. dram_size = 0;
  109. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  110. dram_size += gd->bd->bi_dram[i].size;
  111. nand_size = 0;
  112. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  113. nand_size += get_nand_dev_by_index(i)->size;
  114. lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
  115. dram_size >> 20,
  116. nand_size >> 20);
  117. }
  118. #endif /* CONFIG_LCD_INFO */
  119. #endif /* CONFIG_LCD */
  120. #ifdef CONFIG_KS8851_MLL
  121. void at91sam9n12ek_ks8851_hw_init(void)
  122. {
  123. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  124. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  125. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  126. &smc->cs[2].setup);
  127. writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
  128. AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
  129. &smc->cs[2].pulse);
  130. writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
  131. &smc->cs[2].cycle);
  132. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  133. AT91_SMC_MODE_EXNW_DISABLE |
  134. AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
  135. AT91_SMC_MODE_TDF_CYCLE(1),
  136. &smc->cs[2].mode);
  137. /* Configure NCS2 PIN */
  138. at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
  139. }
  140. #endif
  141. #ifdef CONFIG_USB_ATMEL
  142. void at91sam9n12ek_usb_hw_init(void)
  143. {
  144. at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
  145. }
  146. #endif
  147. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  148. void board_debug_uart_init(void)
  149. {
  150. at91_seriald_hw_init();
  151. }
  152. #endif
  153. #ifdef CONFIG_BOARD_EARLY_INIT_F
  154. int board_early_init_f(void)
  155. {
  156. #ifdef CONFIG_DEBUG_UART
  157. debug_uart_init();
  158. #endif
  159. return 0;
  160. }
  161. #endif
  162. int board_init(void)
  163. {
  164. /* adress of boot parameters */
  165. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  166. #ifdef CONFIG_NAND_ATMEL
  167. at91sam9n12ek_nand_hw_init();
  168. #endif
  169. #ifdef CONFIG_LCD
  170. at91_lcd_hw_init();
  171. #endif
  172. #ifdef CONFIG_KS8851_MLL
  173. at91sam9n12ek_ks8851_hw_init();
  174. #endif
  175. #ifdef CONFIG_USB_ATMEL
  176. at91sam9n12ek_usb_hw_init();
  177. #endif
  178. return 0;
  179. }
  180. #ifdef CONFIG_KS8851_MLL
  181. int board_eth_init(struct bd_info *bis)
  182. {
  183. return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
  184. }
  185. #endif
  186. int dram_init(void)
  187. {
  188. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  189. CONFIG_SYS_SDRAM_SIZE);
  190. return 0;
  191. }
  192. #if defined(CONFIG_SPL_BUILD)
  193. #include <spl.h>
  194. #include <nand.h>
  195. void at91_spl_board_init(void)
  196. {
  197. #ifdef CONFIG_SD_BOOT
  198. at91_mci_hw_init();
  199. #elif CONFIG_NAND_BOOT
  200. at91sam9n12ek_nand_hw_init();
  201. #elif CONFIG_SPI_BOOT
  202. at91_spi0_hw_init(1 << 4);
  203. #endif
  204. }
  205. #include <asm/arch/atmel_mpddrc.h>
  206. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  207. {
  208. ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  209. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  210. ATMEL_MPDDRC_CR_NR_ROW_13 |
  211. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  212. ATMEL_MPDDRC_CR_NB_8BANKS |
  213. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
  214. ddr2->rtr = 0x411;
  215. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  216. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  217. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  218. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  219. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  220. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  221. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  222. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  223. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  224. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  225. 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  226. 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  227. ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  228. 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  229. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  230. 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  231. }
  232. void mem_init(void)
  233. {
  234. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  235. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  236. struct atmel_mpddrc_config ddr2;
  237. unsigned long csa;
  238. ddr2_conf(&ddr2);
  239. /* enable DDR2 clock */
  240. writel(AT91_PMC_DDR, &pmc->scer);
  241. /* Chip select 1 is for DDR2/SDRAM */
  242. csa = readl(&matrix->ebicsa);
  243. csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
  244. csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
  245. csa |= AT91_MATRIX_EBI_DBPD_OFF;
  246. csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  247. writel(csa, &matrix->ebicsa);
  248. /* DDRAM2 Controller initialize */
  249. ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
  250. }
  251. #endif