at91sam9261ek.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. */
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <init.h>
  10. #include <vsprintf.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/at91sam9261.h>
  13. #include <asm/arch/at91sam9261_matrix.h>
  14. #include <asm/arch/at91sam9_smc.h>
  15. #include <asm/arch/at91_common.h>
  16. #include <asm/arch/at91_rstc.h>
  17. #include <asm/arch/clk.h>
  18. #include <asm/arch/gpio.h>
  19. #include <lcd.h>
  20. #include <atmel_lcdc.h>
  21. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  22. #include <net.h>
  23. #include <netdev.h>
  24. #endif
  25. #include <asm/mach-types.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* ------------------------------------------------------------------------- */
  28. /*
  29. * Miscelaneous platform dependent initialisations
  30. */
  31. #ifdef CONFIG_CMD_NAND
  32. static void at91sam9261ek_nand_hw_init(void)
  33. {
  34. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  35. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  36. unsigned long csa;
  37. /* Enable CS3 */
  38. csa = readl(&matrix->ebicsa);
  39. csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  40. writel(csa, &matrix->ebicsa);
  41. /* Configure SMC CS3 for NAND/SmartMedia */
  42. #ifdef CONFIG_AT91SAM9G10EK
  43. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  44. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  45. &smc->cs[3].setup);
  46. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
  47. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
  48. &smc->cs[3].pulse);
  49. writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  50. &smc->cs[3].cycle);
  51. #else
  52. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  53. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  54. &smc->cs[3].setup);
  55. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  56. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  57. &smc->cs[3].pulse);
  58. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  59. &smc->cs[3].cycle);
  60. #endif
  61. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  62. AT91_SMC_MODE_EXNW_DISABLE |
  63. #ifdef CONFIG_SYS_NAND_DBW_16
  64. AT91_SMC_MODE_DBW_16 |
  65. #else /* CONFIG_SYS_NAND_DBW_8 */
  66. AT91_SMC_MODE_DBW_8 |
  67. #endif
  68. AT91_SMC_MODE_TDF_CYCLE(2),
  69. &smc->cs[3].mode);
  70. at91_periph_clk_enable(ATMEL_ID_PIOC);
  71. /* Configure RDY/BSY */
  72. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  73. /* Enable NandFlash */
  74. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  75. at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
  76. at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
  77. }
  78. #endif
  79. #ifdef CONFIG_DRIVER_DM9000
  80. static void at91sam9261ek_dm9000_hw_init(void)
  81. {
  82. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  83. /* Configure SMC CS2 for DM9000 */
  84. #ifdef CONFIG_AT91SAM9G10EK
  85. writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
  86. AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
  87. &smc->cs[2].setup);
  88. writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
  89. AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
  90. &smc->cs[2].pulse);
  91. writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
  92. &smc->cs[2].cycle);
  93. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  94. AT91_SMC_MODE_EXNW_DISABLE |
  95. AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
  96. AT91_SMC_MODE_TDF_CYCLE(1),
  97. &smc->cs[2].mode);
  98. #else
  99. writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
  100. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  101. &smc->cs[2].setup);
  102. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
  103. AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
  104. &smc->cs[2].pulse);
  105. writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
  106. &smc->cs[2].cycle);
  107. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  108. AT91_SMC_MODE_EXNW_DISABLE |
  109. AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
  110. AT91_SMC_MODE_TDF_CYCLE(1),
  111. &smc->cs[2].mode);
  112. #endif
  113. /* Configure Reset signal as output */
  114. at91_set_gpio_output(AT91_PIN_PC10, 0);
  115. /* Configure Interrupt pin as input, no pull-up */
  116. at91_set_gpio_input(AT91_PIN_PC11, 0);
  117. }
  118. #endif
  119. #ifdef CONFIG_LCD
  120. vidinfo_t panel_info = {
  121. .vl_col = 240,
  122. .vl_row = 320,
  123. .vl_clk = 4965000,
  124. .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
  125. ATMEL_LCDC_INVFRAME_INVERTED,
  126. .vl_bpix = 3,
  127. .vl_tft = 1,
  128. .vl_hsync_len = 5,
  129. .vl_left_margin = 1,
  130. .vl_right_margin = 33,
  131. .vl_vsync_len = 1,
  132. .vl_upper_margin = 1,
  133. .vl_lower_margin = 0,
  134. .mmio = ATMEL_BASE_LCDC,
  135. };
  136. void lcd_enable(void)
  137. {
  138. at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
  139. }
  140. void lcd_disable(void)
  141. {
  142. at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
  143. }
  144. static void at91sam9261ek_lcd_hw_init(void)
  145. {
  146. at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
  147. at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
  148. at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
  149. at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
  150. at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
  151. at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
  152. at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
  153. at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
  154. at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
  155. at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
  156. at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
  157. at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
  158. at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
  159. at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
  160. at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
  161. at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
  162. at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
  163. at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
  164. at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
  165. at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
  166. at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
  167. at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
  168. at91_system_clk_enable(AT91_PMC_HCK1);
  169. /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
  170. #ifdef CONFIG_AT91SAM9261EK
  171. gd->fb_base = ATMEL_BASE_SRAM;
  172. #endif
  173. }
  174. #ifdef CONFIG_LCD_INFO
  175. #include <nand.h>
  176. #include <version.h>
  177. void lcd_show_board_info(void)
  178. {
  179. ulong dram_size, nand_size;
  180. int i;
  181. char temp[32];
  182. lcd_printf ("%s\n", U_BOOT_VERSION);
  183. lcd_printf ("(C) 2008 ATMEL Corp\n");
  184. lcd_printf ("at91support@atmel.com\n");
  185. lcd_printf ("%s CPU at %s MHz\n",
  186. ATMEL_CPU_NAME,
  187. strmhz(temp, get_cpu_clk_rate()));
  188. dram_size = 0;
  189. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  190. dram_size += gd->bd->bi_dram[i].size;
  191. nand_size = 0;
  192. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  193. nand_size += get_nand_dev_by_index(i)->size;
  194. lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
  195. dram_size >> 20,
  196. nand_size >> 20 );
  197. }
  198. #endif /* CONFIG_LCD_INFO */
  199. #endif
  200. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  201. void board_debug_uart_init(void)
  202. {
  203. at91_seriald_hw_init();
  204. }
  205. #endif
  206. #ifdef CONFIG_BOARD_EARLY_INIT_F
  207. int board_early_init_f(void)
  208. {
  209. #ifdef CONFIG_DEBUG_UART
  210. debug_uart_init();
  211. #endif
  212. return 0;
  213. }
  214. #endif
  215. int board_init(void)
  216. {
  217. #ifdef CONFIG_AT91SAM9G10EK
  218. /* arch number of AT91SAM9G10EK-Board */
  219. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
  220. #else
  221. /* arch number of AT91SAM9261EK-Board */
  222. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
  223. #endif
  224. /* adress of boot parameters */
  225. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  226. #ifdef CONFIG_CMD_NAND
  227. at91sam9261ek_nand_hw_init();
  228. #endif
  229. #ifdef CONFIG_DRIVER_DM9000
  230. at91sam9261ek_dm9000_hw_init();
  231. #endif
  232. #ifdef CONFIG_LCD
  233. at91sam9261ek_lcd_hw_init();
  234. #endif
  235. return 0;
  236. }
  237. #ifdef CONFIG_DRIVER_DM9000
  238. int board_eth_init(struct bd_info *bis)
  239. {
  240. return dm9000_initialize(bis);
  241. }
  242. #endif
  243. int dram_init(void)
  244. {
  245. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  246. CONFIG_SYS_SDRAM_SIZE);
  247. return 0;
  248. }
  249. #ifdef CONFIG_RESET_PHY_R
  250. void reset_phy(void)
  251. {
  252. #ifdef CONFIG_DRIVER_DM9000
  253. /*
  254. * Initialize ethernet HW addr prior to starting Linux,
  255. * needed for nfsroot
  256. */
  257. eth_init();
  258. #endif
  259. }
  260. #endif