vexpress64.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * David Feng <fenghua@phytium.com.cn>
  5. * Sharma Bhupesh <bhupesh.sharma@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <malloc.h>
  12. #include <errno.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <asm/io.h>
  16. #include <linux/compiler.h>
  17. #include <dm/platform_data/serial_pl01x.h>
  18. #include "pcie.h"
  19. #include <asm/armv8/mmu.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static const struct pl01x_serial_platdata serial_platdata = {
  22. .base = V2M_UART0,
  23. .type = TYPE_PL011,
  24. .clock = CONFIG_PL011_CLOCK,
  25. };
  26. U_BOOT_DEVICE(vexpress_serials) = {
  27. .name = "serial_pl01x",
  28. .platdata = &serial_platdata,
  29. };
  30. static struct mm_region vexpress64_mem_map[] = {
  31. {
  32. .virt = 0x0UL,
  33. .phys = 0x0UL,
  34. .size = 0x80000000UL,
  35. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  36. PTE_BLOCK_NON_SHARE |
  37. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  38. }, {
  39. .virt = 0x80000000UL,
  40. .phys = 0x80000000UL,
  41. .size = 0xff80000000UL,
  42. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  43. PTE_BLOCK_INNER_SHARE
  44. }, {
  45. /* List terminator */
  46. 0,
  47. }
  48. };
  49. struct mm_region *mem_map = vexpress64_mem_map;
  50. /* This function gets replaced by platforms supporting PCIe.
  51. * The replacement function, eg. on Juno, initialises the PCIe bus.
  52. */
  53. __weak void vexpress64_pcie_init(void)
  54. {
  55. }
  56. int board_init(void)
  57. {
  58. vexpress64_pcie_init();
  59. return 0;
  60. }
  61. int dram_init(void)
  62. {
  63. gd->ram_size = PHYS_SDRAM_1_SIZE;
  64. return 0;
  65. }
  66. int dram_init_banksize(void)
  67. {
  68. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  69. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  70. #ifdef PHYS_SDRAM_2
  71. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  72. gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  73. #endif
  74. return 0;
  75. }
  76. #ifdef CONFIG_OF_BOARD
  77. #define JUNO_FLASH_SEC_SIZE (256 * 1024)
  78. static phys_addr_t find_dtb_in_nor_flash(const char *partname)
  79. {
  80. phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
  81. int i;
  82. for (i = 0;
  83. i < CONFIG_SYS_MAX_FLASH_SECT;
  84. i++, sector += JUNO_FLASH_SEC_SIZE) {
  85. int len = strlen(partname) + 1;
  86. int offs;
  87. phys_addr_t imginfo;
  88. u32 reg;
  89. reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
  90. /* This makes up the string "HSLFTOOF" flash footer */
  91. if (reg != 0x464F4F54U)
  92. continue;
  93. reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
  94. if (reg != 0x464C5348U)
  95. continue;
  96. for (offs = 0; offs < 32; offs += 4, len -= 4) {
  97. reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
  98. if (strncmp(partname + offs, (char *)&reg,
  99. len > 4 ? 4 : len))
  100. break;
  101. if (len > 4)
  102. continue;
  103. reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
  104. imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
  105. reg = readl(imginfo + 0x54);
  106. return CONFIG_SYS_FLASH_BASE +
  107. reg * JUNO_FLASH_SEC_SIZE;
  108. }
  109. }
  110. printf("No DTB found\n");
  111. return ~0;
  112. }
  113. void *board_fdt_blob_setup(void)
  114. {
  115. phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
  116. if (fdt_rom_addr == ~0UL)
  117. return NULL;
  118. return (void *)fdt_rom_addr;
  119. }
  120. #endif
  121. /* Actual reset is done via PSCI. */
  122. void reset_cpu(ulong addr)
  123. {
  124. }
  125. /*
  126. * Board specific ethernet initialization routine.
  127. */
  128. int board_eth_init(struct bd_info *bis)
  129. {
  130. int rc = 0;
  131. #ifndef CONFIG_DM_ETH
  132. #ifdef CONFIG_SMC91111
  133. rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
  134. #endif
  135. #ifdef CONFIG_SMC911X
  136. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  137. #endif
  138. #endif
  139. return rc;
  140. }