pcie.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) ARM Ltd 2015
  4. *
  5. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <linux/bitops.h>
  12. #include <pci_ids.h>
  13. #include <linux/delay.h>
  14. #include "pcie.h"
  15. /* XpressRICH3 support */
  16. #define XR3_CONFIG_BASE 0x7ff30000
  17. #define XR3_RESET_BASE 0x7ff20000
  18. #define XR3_PCI_ECAM_START 0x40000000
  19. #define XR3_PCI_ECAM_SIZE 28 /* as power of 2 = 0x10000000 */
  20. #define XR3_PCI_IOSPACE_START 0x5f800000
  21. #define XR3_PCI_IOSPACE_SIZE 23 /* as power of 2 = 0x800000 */
  22. #define XR3_PCI_MEMSPACE_START 0x50000000
  23. #define XR3_PCI_MEMSPACE_SIZE 27 /* as power of 2 = 0x8000000 */
  24. #define XR3_PCI_MEMSPACE64_START 0x4000000000
  25. #define XR3_PCI_MEMSPACE64_SIZE 33 /* as power of 2 = 0x200000000 */
  26. #define JUNO_V2M_MSI_START 0x2c1c0000
  27. #define JUNO_V2M_MSI_SIZE 12 /* as power of 2 = 4096 */
  28. #define XR3PCI_BASIC_STATUS 0x18
  29. #define XR3PCI_BS_GEN_MASK (0xf << 8)
  30. #define XR3PCI_BS_LINK_MASK 0xff
  31. #define XR3PCI_VIRTCHAN_CREDITS 0x90
  32. #define XR3PCI_BRIDGE_PCI_IDS 0x9c
  33. #define XR3PCI_PEX_SPC2 0xd8
  34. #define XR3PCI_ATR_PCIE_WIN0 0x600
  35. #define XR3PCI_ATR_PCIE_WIN1 0x700
  36. #define XR3PCI_ATR_AXI4_SLV0 0x800
  37. #define XR3PCI_ATR_TABLE_SIZE 0x20
  38. #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
  39. #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
  40. #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
  41. #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
  42. #define XR3PCI_ATR_TRSL_PARAM 0x10
  43. /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
  44. #define XR3PCI_ATR_TRSLID_AXIDEVICE (0x420004)
  45. #define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */
  46. #define XR3PCI_ATR_TRSLID_PCIE_CONF (0x000001)
  47. #define XR3PCI_ATR_TRSLID_PCIE_IO (0x020000)
  48. #define XR3PCI_ATR_TRSLID_PCIE_MEMORY (0x000000)
  49. #define XR3PCI_ECAM_OFFSET(b, d, o) (((b) << 20) | \
  50. (PCI_SLOT(d) << 15) | \
  51. (PCI_FUNC(d) << 12) | o)
  52. #define JUNO_RESET_CTRL 0x1004
  53. #define JUNO_RESET_CTRL_PHY BIT(0)
  54. #define JUNO_RESET_CTRL_RC BIT(1)
  55. #define JUNO_RESET_STATUS 0x1008
  56. #define JUNO_RESET_STATUS_PLL BIT(0)
  57. #define JUNO_RESET_STATUS_PHY BIT(1)
  58. #define JUNO_RESET_STATUS_RC BIT(2)
  59. #define JUNO_RESET_STATUS_MASK (JUNO_RESET_STATUS_PLL | \
  60. JUNO_RESET_STATUS_PHY | \
  61. JUNO_RESET_STATUS_RC)
  62. static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
  63. unsigned long trsl_addr, int window_size,
  64. int trsl_param)
  65. {
  66. /* X3PCI_ATR_SRC_ADDR_LOW:
  67. - bit 0: enable entry,
  68. - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
  69. - bits 7-11: reserved
  70. - bits 12-31: start of source address
  71. */
  72. writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1,
  73. base + XR3PCI_ATR_SRC_ADDR_LOW);
  74. writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH);
  75. writel((u32)(trsl_addr & 0xfffff000), base + XR3PCI_ATR_TRSL_ADDR_LOW);
  76. writel((u32)(trsl_addr >> 32), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
  77. writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
  78. debug("ATR entry: 0x%010lx %s 0x%010lx [0x%010llx] (param: 0x%06x)\n",
  79. src_addr, (trsl_param & 0x400000) ? "<-" : "->", trsl_addr,
  80. ((u64)1) << window_size, trsl_param);
  81. }
  82. static void xr3pci_setup_atr(void)
  83. {
  84. /* setup PCIe to CPU address translation tables */
  85. unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
  86. /* forward all writes from PCIe to GIC V2M (used for MSI) */
  87. xr3pci_set_atr_entry(base, JUNO_V2M_MSI_START, JUNO_V2M_MSI_START,
  88. JUNO_V2M_MSI_SIZE, XR3PCI_ATR_TRSLID_AXIDEVICE);
  89. base += XR3PCI_ATR_TABLE_SIZE;
  90. /* PCIe devices can write anywhere in memory */
  91. xr3pci_set_atr_entry(base, PHYS_SDRAM_1, PHYS_SDRAM_1,
  92. 31 /* grant access to all RAM under 4GB */,
  93. XR3PCI_ATR_TRSLID_AXIMEMORY);
  94. base += XR3PCI_ATR_TABLE_SIZE;
  95. xr3pci_set_atr_entry(base, PHYS_SDRAM_2, PHYS_SDRAM_2,
  96. XR3_PCI_MEMSPACE64_SIZE,
  97. XR3PCI_ATR_TRSLID_AXIMEMORY);
  98. /* setup CPU to PCIe address translation table */
  99. base = XR3_CONFIG_BASE + XR3PCI_ATR_AXI4_SLV0;
  100. /* setup ECAM space to bus configuration interface */
  101. xr3pci_set_atr_entry(base, XR3_PCI_ECAM_START, 0, XR3_PCI_ECAM_SIZE,
  102. XR3PCI_ATR_TRSLID_PCIE_CONF);
  103. base += XR3PCI_ATR_TABLE_SIZE;
  104. /* setup IO space translation */
  105. xr3pci_set_atr_entry(base, XR3_PCI_IOSPACE_START, 0,
  106. XR3_PCI_IOSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_IO);
  107. base += XR3PCI_ATR_TABLE_SIZE;
  108. /* setup 32bit MEM space translation */
  109. xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE_START, XR3_PCI_MEMSPACE_START,
  110. XR3_PCI_MEMSPACE_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
  111. base += XR3PCI_ATR_TABLE_SIZE;
  112. /* setup 64bit MEM space translation */
  113. xr3pci_set_atr_entry(base, XR3_PCI_MEMSPACE64_START, XR3_PCI_MEMSPACE64_START,
  114. XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
  115. }
  116. static void xr3pci_init(void)
  117. {
  118. u32 val;
  119. int timeout = 200;
  120. /* Initialise the XpressRICH3 PCIe host bridge */
  121. /* add credits */
  122. writel(0x00f0b818, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS);
  123. writel(0x1, XR3_CONFIG_BASE + XR3PCI_VIRTCHAN_CREDITS + 4);
  124. /* allow ECRC */
  125. writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2);
  126. /* setup the correct class code for the host bridge */
  127. writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS);
  128. /* reset phy and root complex */
  129. writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC,
  130. XR3_RESET_BASE + JUNO_RESET_CTRL);
  131. do {
  132. mdelay(1);
  133. val = readl(XR3_RESET_BASE + JUNO_RESET_STATUS);
  134. } while (--timeout &&
  135. (val & JUNO_RESET_STATUS_MASK) != JUNO_RESET_STATUS_MASK);
  136. if (!timeout) {
  137. printf("PCI XR3 Root complex reset timed out\n");
  138. return;
  139. }
  140. /* Wait for the link to train */
  141. mdelay(20);
  142. timeout = 20;
  143. do {
  144. mdelay(1);
  145. val = readl(XR3_CONFIG_BASE + XR3PCI_BASIC_STATUS);
  146. } while (--timeout && !(val & XR3PCI_BS_LINK_MASK));
  147. if (!(val & XR3PCI_BS_LINK_MASK)) {
  148. printf("Failed to negotiate a link!\n");
  149. return;
  150. }
  151. printf("PCIe XR3 Host Bridge enabled: x%d link (Gen %d)\n",
  152. val & XR3PCI_BS_LINK_MASK, (val & XR3PCI_BS_GEN_MASK) >> 8);
  153. xr3pci_setup_atr();
  154. }
  155. void vexpress64_pcie_init(void)
  156. {
  157. /* Initialise and configure the PCIe host bridge. */
  158. xr3pci_init();
  159. /* Register the now ECAM complaint PCIe host controller with U-Boot. */
  160. pci_init();
  161. }