vexpress_common.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  9. *
  10. * (C) Copyright 2003
  11. * Texas Instruments, <www.ti.com>
  12. * Kshitij Gupta <Kshitij@ti.com>
  13. *
  14. * (C) Copyright 2004
  15. * ARM Ltd.
  16. * Philippe Robin, <philippe.robin@arm.com>
  17. */
  18. #include <common.h>
  19. #include <bootstage.h>
  20. #include <cpu_func.h>
  21. #include <init.h>
  22. #include <malloc.h>
  23. #include <errno.h>
  24. #include <net.h>
  25. #include <netdev.h>
  26. #include <asm/io.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/arch/systimer.h>
  29. #include <asm/arch/sysctrl.h>
  30. #include <asm/arch/wdt.h>
  31. #include "../drivers/mmc/arm_pl180_mmci.h"
  32. static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
  33. static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
  34. static void flash__init(void);
  35. static void vexpress_timer_init(void);
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #if defined(CONFIG_SHOW_BOOT_PROGRESS)
  38. void show_boot_progress(int progress)
  39. {
  40. printf("Boot reached stage %d\n", progress);
  41. }
  42. #endif
  43. static inline void delay(ulong loops)
  44. {
  45. __asm__ volatile ("1:\n"
  46. "subs %0, %1, #1\n"
  47. "bne 1b" : "=r" (loops) : "0" (loops));
  48. }
  49. int board_init(void)
  50. {
  51. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  52. gd->bd->bi_arch_number = MACH_TYPE_VEXPRESS;
  53. gd->flags = 0;
  54. icache_enable();
  55. flash__init();
  56. vexpress_timer_init();
  57. return 0;
  58. }
  59. int board_eth_init(struct bd_info *bis)
  60. {
  61. int rc = 0;
  62. #ifdef CONFIG_SMC911X
  63. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  64. #endif
  65. return rc;
  66. }
  67. int cpu_mmc_init(struct bd_info *bis)
  68. {
  69. int rc = 0;
  70. (void) bis;
  71. #ifdef CONFIG_ARM_PL180_MMCI
  72. struct pl180_mmc_host *host;
  73. struct mmc *mmc;
  74. host = malloc(sizeof(struct pl180_mmc_host));
  75. if (!host)
  76. return -ENOMEM;
  77. memset(host, 0, sizeof(*host));
  78. strcpy(host->name, "MMC");
  79. host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
  80. host->pwr_init = INIT_PWR;
  81. host->clkdiv_init = SDI_CLKCR_CLKDIV_INIT_V1 | SDI_CLKCR_CLKEN;
  82. host->voltages = VOLTAGE_WINDOW_MMC;
  83. host->caps = 0;
  84. host->clock_in = ARM_MCLK;
  85. host->clock_min = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT_V1 + 1));
  86. host->clock_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
  87. rc = arm_pl180_mmci_init(host, &mmc);
  88. #endif
  89. return rc;
  90. }
  91. static void flash__init(void)
  92. {
  93. /* Setup the sytem control register to allow writing to flash */
  94. writel(readl(&sysctrl_base->scflashctrl) | VEXPRESS_FLASHPROG_FLVPPEN,
  95. &sysctrl_base->scflashctrl);
  96. }
  97. int dram_init(void)
  98. {
  99. gd->ram_size =
  100. get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE);
  101. return 0;
  102. }
  103. int dram_init_banksize(void)
  104. {
  105. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  106. gd->bd->bi_dram[0].size =
  107. get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  108. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  109. gd->bd->bi_dram[1].size =
  110. get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  111. return 0;
  112. }
  113. /*
  114. * Start timer:
  115. * Setup a 32 bit timer, running at 1KHz
  116. * Versatile Express Motherboard provides 1 MHz timer
  117. */
  118. static void vexpress_timer_init(void)
  119. {
  120. /*
  121. * Set clock frequency in system controller:
  122. * VEXPRESS_REFCLK is 32KHz
  123. * VEXPRESS_TIMCLK is 1MHz
  124. */
  125. writel(SP810_TIMER0_ENSEL | SP810_TIMER1_ENSEL |
  126. SP810_TIMER2_ENSEL | SP810_TIMER3_ENSEL |
  127. readl(&sysctrl_base->scctrl), &sysctrl_base->scctrl);
  128. /*
  129. * Set Timer0 to be:
  130. * Enabled, free running, no interrupt, 32-bit, wrapping
  131. */
  132. writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
  133. writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
  134. writel(SYSTIMER_EN | SYSTIMER_32BIT |
  135. readl(&systimer_base->timer0control),
  136. &systimer_base->timer0control);
  137. }
  138. int v2m_cfg_write(u32 devfn, u32 data)
  139. {
  140. /* Configuration interface broken? */
  141. u32 val;
  142. devfn |= SYS_CFG_START | SYS_CFG_WRITE;
  143. val = readl(V2M_SYS_CFGSTAT);
  144. writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
  145. writel(data, V2M_SYS_CFGDATA);
  146. writel(devfn, V2M_SYS_CFGCTRL);
  147. do {
  148. val = readl(V2M_SYS_CFGSTAT);
  149. } while (val == 0);
  150. return !!(val & SYS_CFG_ERR);
  151. }
  152. /* Use the ARM Watchdog System to cause reset */
  153. void reset_cpu(ulong addr)
  154. {
  155. if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
  156. printf("Unable to reboot\n");
  157. }
  158. void lowlevel_init(void)
  159. {
  160. }
  161. ulong get_board_rev(void){
  162. return readl((u32 *)SYS_ID);
  163. }
  164. #ifdef CONFIG_ARMV7_NONSEC
  165. /* Setting the address at which secondary cores start from.
  166. * Versatile Express uses one address for all cores, so ignore corenr
  167. */
  168. void smp_set_core_boot_addr(unsigned long addr, int corenr)
  169. {
  170. /* The SYSFLAGS register on VExpress needs to be cleared first
  171. * by writing to the next address, since any writes to the address
  172. * at offset 0 will only be ORed in
  173. */
  174. writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
  175. writel(addr, CONFIG_SYSFLAGS_ADDR);
  176. }
  177. #endif