integrator.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  9. *
  10. * (C) Copyright 2003
  11. * Texas Instruments, <www.ti.com>
  12. * Kshitij Gupta <Kshitij@ti.com>
  13. *
  14. * (C) Copyright 2004
  15. * ARM Ltd.
  16. * Philippe Robin, <philippe.robin@arm.com>
  17. */
  18. #include <common.h>
  19. #include <bootstage.h>
  20. #include <cpu_func.h>
  21. #include <dm.h>
  22. #include <env.h>
  23. #include <init.h>
  24. #include <net.h>
  25. #include <netdev.h>
  26. #include <asm/io.h>
  27. #include <dm/platform_data/serial_pl01x.h>
  28. #include "arm-ebi.h"
  29. #include "integrator-sc.h"
  30. #include <asm/mach-types.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. static const struct pl01x_serial_platdata serial_platdata = {
  33. .base = 0x16000000,
  34. #ifdef CONFIG_ARCH_CINTEGRATOR
  35. .type = TYPE_PL011,
  36. .clock = 14745600,
  37. #else
  38. .type = TYPE_PL010,
  39. .clock = 0, /* Not used for PL010 */
  40. #endif
  41. };
  42. U_BOOT_DEVICE(integrator_serials) = {
  43. .name = "serial_pl01x",
  44. .platdata = &serial_platdata,
  45. };
  46. void peripheral_power_enable (void);
  47. #if defined(CONFIG_SHOW_BOOT_PROGRESS)
  48. void show_boot_progress(int progress)
  49. {
  50. printf("Boot reached stage %d\n", progress);
  51. }
  52. #endif
  53. #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
  54. /*
  55. * Miscellaneous platform dependent initialisations
  56. */
  57. int board_init (void)
  58. {
  59. u32 val;
  60. /* arch number of Integrator Board */
  61. #ifdef CONFIG_ARCH_CINTEGRATOR
  62. gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
  63. #else
  64. gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
  65. #endif
  66. /* adress of boot parameters */
  67. gd->bd->bi_boot_params = 0x00000100;
  68. #ifdef CONFIG_CM_REMAP
  69. extern void cm_remap(void);
  70. cm_remap(); /* remaps writeable memory to 0x00000000 */
  71. #endif
  72. #ifdef CONFIG_ARCH_CINTEGRATOR
  73. /*
  74. * Flash protection on the Integrator/CP is in a simple register
  75. */
  76. val = readl(CP_FLASHPROG);
  77. val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
  78. writel(val, CP_FLASHPROG);
  79. #else
  80. /*
  81. * The Integrator/AP has some special protection mechanisms
  82. * for the external memories, first the External Bus Interface (EBI)
  83. * then the system controller (SC).
  84. *
  85. * The system comes up with the flash memory non-writable and
  86. * configuration locked. If we want U-Boot to be used for flash
  87. * access we cannot have the flash memory locked.
  88. */
  89. writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
  90. val = readl(EBI_BASE + EBI_CSR1_REG);
  91. val &= EBI_CSR_WREN_MASK;
  92. val |= EBI_CSR_WREN_ENABLE;
  93. writel(val, EBI_BASE + EBI_CSR1_REG);
  94. writel(0, EBI_BASE + EBI_LOCK_REG);
  95. /*
  96. * Set up the system controller to remove write protection from
  97. * the flash memory and enable Vpp
  98. */
  99. writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
  100. #endif
  101. icache_enable();
  102. return 0;
  103. }
  104. int misc_init_r (void)
  105. {
  106. env_set("verify", "n");
  107. return (0);
  108. }
  109. /*
  110. * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
  111. * from there, which means we cannot test the RAM underneath the ROM at this
  112. * point. It will be unmapped later on, when we are executing from the
  113. * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
  114. * RAM on higher addresses works fine.
  115. */
  116. #define REMAPPED_FLASH_SZ 0x40000
  117. int dram_init (void)
  118. {
  119. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  120. #ifdef CONFIG_CM_SPD_DETECT
  121. {
  122. extern void dram_query(void);
  123. u32 cm_reg_sdram;
  124. u32 sdram_shift;
  125. dram_query(); /* Assembler accesses to CM registers */
  126. /* Queries the SPD values */
  127. /* Obtain the SDRAM size from the CM SDRAM register */
  128. cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
  129. /* Register SDRAM size
  130. *
  131. * 0xXXXXXXbbb000bb 16 MB
  132. * 0xXXXXXXbbb001bb 32 MB
  133. * 0xXXXXXXbbb010bb 64 MB
  134. * 0xXXXXXXbbb011bb 128 MB
  135. * 0xXXXXXXbbb100bb 256 MB
  136. *
  137. */
  138. sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
  139. gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
  140. REMAPPED_FLASH_SZ,
  141. 0x01000000 << sdram_shift);
  142. }
  143. #else
  144. gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
  145. REMAPPED_FLASH_SZ,
  146. PHYS_SDRAM_1_SIZE);
  147. #endif /* CM_SPD_DETECT */
  148. /* We only have one bank of RAM, set it to whatever was detected */
  149. gd->bd->bi_dram[0].size = gd->ram_size;
  150. return 0;
  151. }
  152. #ifdef CONFIG_CMD_NET
  153. int board_eth_init(struct bd_info *bis)
  154. {
  155. int rc = 0;
  156. #ifdef CONFIG_SMC91111
  157. rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
  158. #endif
  159. rc += pci_eth_init(bis);
  160. return rc;
  161. }
  162. #endif