dms-ba16.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Timesys Corporation
  4. * Copyright 2016 Advantech Corporation
  5. * Copyright 2012 Freescale Semiconductor, Inc.
  6. */
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/mxc_i2c.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/boot_mode.h>
  19. #include <asm/mach-imx/video.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <miiphy.h>
  23. #include <netdev.h>
  24. #include <asm/arch/mxc_hdmi.h>
  25. #include <asm/arch/crm_regs.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <i2c.h>
  29. #include <input.h>
  30. #include <pwm.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  33. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  34. PAD_CTL_HYS)
  35. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  36. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  37. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  38. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  39. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  42. PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  43. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  45. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  46. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  47. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  48. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  49. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  50. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  51. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  52. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  53. int dram_init(void)
  54. {
  55. gd->ram_size = imx_ddr_size();
  56. return 0;
  57. }
  58. static iomux_v3_cfg_t const uart3_pads[] = {
  59. MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  60. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  61. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  62. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. };
  64. static iomux_v3_cfg_t const uart4_pads[] = {
  65. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  66. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  67. };
  68. static iomux_v3_cfg_t const enet_pads[] = {
  69. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  78. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  79. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  80. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  81. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  82. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  83. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  84. /* AR8033 PHY Reset */
  85. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  86. };
  87. static void setup_iomux_enet(void)
  88. {
  89. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  90. /* Reset AR8033 PHY */
  91. gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
  92. mdelay(10);
  93. gpio_set_value(IMX_GPIO_NR(1, 28), 1);
  94. mdelay(1);
  95. }
  96. static iomux_v3_cfg_t const usdhc2_pads[] = {
  97. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  102. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  104. };
  105. static iomux_v3_cfg_t const usdhc3_pads[] = {
  106. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. };
  118. static iomux_v3_cfg_t const usdhc4_pads[] = {
  119. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126. MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127. MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128. MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  130. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  131. };
  132. static iomux_v3_cfg_t const ecspi1_pads[] = {
  133. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  134. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  135. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  136. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  137. };
  138. static struct i2c_pads_info i2c_pad_info1 = {
  139. .scl = {
  140. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
  141. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
  142. .gp = IMX_GPIO_NR(5, 27)
  143. },
  144. .sda = {
  145. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
  146. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
  147. .gp = IMX_GPIO_NR(5, 26)
  148. }
  149. };
  150. static struct i2c_pads_info i2c_pad_info2 = {
  151. .scl = {
  152. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  153. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  154. .gp = IMX_GPIO_NR(4, 12)
  155. },
  156. .sda = {
  157. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  158. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  159. .gp = IMX_GPIO_NR(4, 13)
  160. }
  161. };
  162. static struct i2c_pads_info i2c_pad_info3 = {
  163. .scl = {
  164. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
  165. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
  166. .gp = IMX_GPIO_NR(1, 3)
  167. },
  168. .sda = {
  169. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
  170. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
  171. .gp = IMX_GPIO_NR(1, 6)
  172. }
  173. };
  174. #ifdef CONFIG_MXC_SPI
  175. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  176. {
  177. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
  178. }
  179. static void setup_spi(void)
  180. {
  181. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  182. }
  183. #endif
  184. static iomux_v3_cfg_t const pcie_pads[] = {
  185. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  186. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  187. };
  188. static void setup_pcie(void)
  189. {
  190. imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  191. }
  192. static void setup_iomux_uart(void)
  193. {
  194. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  195. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  196. }
  197. #ifdef CONFIG_FSL_ESDHC_IMX
  198. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  199. {USDHC2_BASE_ADDR},
  200. {USDHC3_BASE_ADDR},
  201. {USDHC4_BASE_ADDR},
  202. };
  203. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  204. #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
  205. int board_mmc_getcd(struct mmc *mmc)
  206. {
  207. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  208. int ret = 0;
  209. switch (cfg->esdhc_base) {
  210. case USDHC2_BASE_ADDR:
  211. ret = !gpio_get_value(USDHC2_CD_GPIO);
  212. break;
  213. case USDHC3_BASE_ADDR:
  214. ret = 1; /* eMMC is always present */
  215. break;
  216. case USDHC4_BASE_ADDR:
  217. ret = !gpio_get_value(USDHC4_CD_GPIO);
  218. break;
  219. }
  220. return ret;
  221. }
  222. int board_mmc_init(struct bd_info *bis)
  223. {
  224. int ret;
  225. int i;
  226. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  227. switch (i) {
  228. case 0:
  229. imx_iomux_v3_setup_multiple_pads(
  230. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  231. gpio_direction_input(USDHC2_CD_GPIO);
  232. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  233. break;
  234. case 1:
  235. imx_iomux_v3_setup_multiple_pads(
  236. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  237. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  238. break;
  239. case 2:
  240. imx_iomux_v3_setup_multiple_pads(
  241. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  242. gpio_direction_input(USDHC4_CD_GPIO);
  243. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  244. break;
  245. default:
  246. printf("Warning: you configured more USDHC controllers\n"
  247. "(%d) then supported by the board (%d)\n",
  248. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  249. return -EINVAL;
  250. }
  251. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  252. if (ret)
  253. return ret;
  254. }
  255. return 0;
  256. }
  257. #endif
  258. static int mx6_rgmii_rework(struct phy_device *phydev)
  259. {
  260. /* set device address 0x7 */
  261. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  262. /* offset 0x8016: CLK_25M Clock Select */
  263. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  264. /* enable register write, no post increment, address 0x7 */
  265. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  266. /* set to 125 MHz from local PLL source */
  267. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  268. /* set debug port address: SerDes Test and System Mode Control */
  269. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  270. /* enable rgmii tx clock delay */
  271. /* set the reserved bits to avoid board specific voltage peak issue*/
  272. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  273. return 0;
  274. }
  275. int board_phy_config(struct phy_device *phydev)
  276. {
  277. mx6_rgmii_rework(phydev);
  278. if (phydev->drv->config)
  279. phydev->drv->config(phydev);
  280. return 0;
  281. }
  282. #if defined(CONFIG_VIDEO_IPUV3)
  283. static iomux_v3_cfg_t const backlight_pads[] = {
  284. /* Power for LVDS Display */
  285. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  286. #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
  287. /* Backlight enable for LVDS display */
  288. MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  289. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
  290. /* backlight PWM brightness control */
  291. MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  292. };
  293. static void do_enable_hdmi(struct display_info_t const *dev)
  294. {
  295. imx_enable_hdmi_phy();
  296. }
  297. int board_cfb_skip(void)
  298. {
  299. gpio_direction_output(LVDS_POWER_GP, 1);
  300. return 0;
  301. }
  302. static int detect_baseboard(struct display_info_t const *dev)
  303. {
  304. return 0 == dev->addr;
  305. }
  306. struct display_info_t const displays[] = {{
  307. .bus = -1,
  308. .addr = 0,
  309. .pixfmt = IPU_PIX_FMT_RGB24,
  310. .detect = detect_baseboard,
  311. .enable = NULL,
  312. .mode = {
  313. .name = "SHARP-LQ156M1LG21",
  314. .refresh = 60,
  315. .xres = 1920,
  316. .yres = 1080,
  317. .pixclock = 7851,
  318. .left_margin = 100,
  319. .right_margin = 40,
  320. .upper_margin = 30,
  321. .lower_margin = 3,
  322. .hsync_len = 10,
  323. .vsync_len = 2,
  324. .sync = FB_SYNC_EXT,
  325. .vmode = FB_VMODE_NONINTERLACED
  326. } }, {
  327. .bus = -1,
  328. .addr = 3,
  329. .pixfmt = IPU_PIX_FMT_RGB24,
  330. .detect = detect_hdmi,
  331. .enable = do_enable_hdmi,
  332. .mode = {
  333. .name = "HDMI",
  334. .refresh = 60,
  335. .xres = 1024,
  336. .yres = 768,
  337. .pixclock = 15385,
  338. .left_margin = 220,
  339. .right_margin = 40,
  340. .upper_margin = 21,
  341. .lower_margin = 7,
  342. .hsync_len = 60,
  343. .vsync_len = 10,
  344. .sync = FB_SYNC_EXT,
  345. .vmode = FB_VMODE_NONINTERLACED
  346. } } };
  347. size_t display_count = ARRAY_SIZE(displays);
  348. static void setup_display(void)
  349. {
  350. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  351. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  352. clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  353. imx_setup_hdmi();
  354. /* Set LDB_DI0 as clock source for IPU_DI0 */
  355. clrsetbits_le32(&mxc_ccm->chsccdr,
  356. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  357. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  358. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  359. /* Turn on IPU LDB DI0 clocks */
  360. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  361. enable_ipu_clock();
  362. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  363. IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  364. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  365. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  366. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  367. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  368. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  369. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  370. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  371. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
  372. &iomux->gpr[2]);
  373. clrsetbits_le32(&iomux->gpr[3],
  374. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  375. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  376. IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
  377. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  378. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
  379. /* backlights off until needed */
  380. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  381. ARRAY_SIZE(backlight_pads));
  382. gpio_direction_input(LVDS_POWER_GP);
  383. gpio_direction_input(LVDS_BACKLIGHT_GP);
  384. }
  385. #endif /* CONFIG_VIDEO_IPUV3 */
  386. /*
  387. * Do not overwrite the console
  388. * Use always serial for U-Boot console
  389. */
  390. int overwrite_console(void)
  391. {
  392. return 1;
  393. }
  394. int board_eth_init(struct bd_info *bis)
  395. {
  396. setup_iomux_enet();
  397. setup_pcie();
  398. return cpu_eth_init(bis);
  399. }
  400. static iomux_v3_cfg_t const misc_pads[] = {
  401. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  402. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
  403. MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
  404. MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
  405. MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
  406. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
  407. MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
  408. };
  409. #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
  410. #define WIFI_EN IMX_GPIO_NR(6, 14)
  411. int setup_ba16_sata(void)
  412. {
  413. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  414. int ret;
  415. ret = enable_sata_clock();
  416. if (ret)
  417. return ret;
  418. clrsetbits_le32(&iomuxc_regs->gpr[13],
  419. IOMUXC_GPR13_SATA_MASK,
  420. IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
  421. |IOMUXC_GPR13_SATA_PHY_7_SATA2M
  422. |IOMUXC_GPR13_SATA_SPEED_3G
  423. |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
  424. |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
  425. |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
  426. |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
  427. |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
  428. |IOMUXC_GPR13_SATA_PHY_1_SLOW);
  429. return 0;
  430. }
  431. int board_early_init_f(void)
  432. {
  433. imx_iomux_v3_setup_multiple_pads(misc_pads,
  434. ARRAY_SIZE(misc_pads));
  435. setup_iomux_uart();
  436. #if defined(CONFIG_VIDEO_IPUV3)
  437. /* Set LDB clock to PLL2 PFD0 */
  438. select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
  439. #endif
  440. return 0;
  441. }
  442. int board_init(void)
  443. {
  444. gpio_direction_output(SUS_S3_OUT, 1);
  445. gpio_direction_output(WIFI_EN, 1);
  446. #if defined(CONFIG_VIDEO_IPUV3)
  447. setup_display();
  448. #endif
  449. /* address of boot parameters */
  450. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  451. #ifdef CONFIG_MXC_SPI
  452. setup_spi();
  453. #endif
  454. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  455. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  456. setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  457. return 0;
  458. }
  459. #ifdef CONFIG_CMD_BMODE
  460. static const struct boot_mode board_boot_modes[] = {
  461. /* 4 bit bus width */
  462. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  463. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  464. {NULL, 0},
  465. };
  466. #endif
  467. void pmic_init(void)
  468. {
  469. #define DA9063_ADDR 0x58
  470. #define BCORE2_CONF 0x9D
  471. #define BCORE1_CONF 0x9E
  472. #define BPRO_CONF 0x9F
  473. #define BIO_CONF 0xA0
  474. #define BMEM_CONF 0xA1
  475. #define BPERI_CONF 0xA2
  476. #define MODE_BIT_H 7
  477. #define MODE_BIT_L 6
  478. uchar val;
  479. i2c_set_bus_num(2);
  480. i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
  481. val |= (1 << MODE_BIT_H);
  482. val &= ~(1 << MODE_BIT_L);
  483. i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
  484. i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
  485. val |= (1 << MODE_BIT_H);
  486. val &= ~(1 << MODE_BIT_L);
  487. i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
  488. i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
  489. val |= (1 << MODE_BIT_H);
  490. val &= ~(1 << MODE_BIT_L);
  491. i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
  492. i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
  493. val |= (1 << MODE_BIT_H);
  494. val &= ~(1 << MODE_BIT_L);
  495. i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
  496. i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
  497. val |= (1 << MODE_BIT_H);
  498. val &= ~(1 << MODE_BIT_L);
  499. i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
  500. i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
  501. val |= (1 << MODE_BIT_H);
  502. val &= ~(1 << MODE_BIT_L);
  503. i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
  504. }
  505. int board_late_init(void)
  506. {
  507. #ifdef CONFIG_CMD_BMODE
  508. add_board_boot_modes(board_boot_modes);
  509. #endif
  510. #if defined(CONFIG_VIDEO_IPUV3)
  511. /*
  512. * We need at least 200ms between power on and backlight on
  513. * as per specifications from CHI MEI
  514. */
  515. mdelay(250);
  516. /* enable backlight PWM 1 */
  517. pwm_init(0, 0, 0);
  518. /* duty cycle 5000000ns, period: 5000000ns */
  519. pwm_config(0, 5000000, 5000000);
  520. /* Backlight Power */
  521. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  522. pwm_enable(0);
  523. #endif
  524. #ifdef CONFIG_SATA
  525. setup_ba16_sata();
  526. #endif
  527. /* board specific pmic init */
  528. pmic_init();
  529. return 0;
  530. }
  531. int checkboard(void)
  532. {
  533. printf("BOARD: %s\n", CONFIG_BOARD_NAME);
  534. return 0;
  535. }