gplugd.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011
  4. * eInfochips Ltd. <www.einfochips.com>
  5. * Written-by: Ajay Bhargav <contact@8051projects.net>
  6. *
  7. * Based on Aspenite:
  8. * (C) Copyright 2010
  9. * Marvell Semiconductor <www.marvell.com>
  10. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  11. * Contributor: Mahavir Jain <mjain@marvell.com>
  12. */
  13. #include <common.h>
  14. #include <init.h>
  15. #include <log.h>
  16. #include <mvmfp.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/mfp.h>
  19. #include <asm/arch/armada100.h>
  20. #include <asm/gpio.h>
  21. #include <miiphy.h>
  22. #include <asm/mach-types.h>
  23. #include <linux/delay.h>
  24. #ifdef CONFIG_ARMADA100_FEC
  25. #include <net.h>
  26. #include <netdev.h>
  27. #endif /* CONFIG_ARMADA100_FEC */
  28. DECLARE_GLOBAL_DATA_PTR;
  29. int board_early_init_f(void)
  30. {
  31. u32 mfp_cfg[] = {
  32. /* I2C */
  33. MFP105_CI2C_SDA,
  34. MFP106_CI2C_SCL,
  35. /* Enable Console on UART3 */
  36. MFPO8_UART3_TXD,
  37. MFPO9_UART3_RXD,
  38. /* Ethernet PHY Interface */
  39. MFP086_ETH_TXCLK,
  40. MFP087_ETH_TXEN,
  41. MFP088_ETH_TXDQ3,
  42. MFP089_ETH_TXDQ2,
  43. MFP090_ETH_TXDQ1,
  44. MFP091_ETH_TXDQ0,
  45. MFP092_ETH_CRS,
  46. MFP093_ETH_COL,
  47. MFP094_ETH_RXCLK,
  48. MFP095_ETH_RXER,
  49. MFP096_ETH_RXDQ3,
  50. MFP097_ETH_RXDQ2,
  51. MFP098_ETH_RXDQ1,
  52. MFP099_ETH_RXDQ0,
  53. MFP100_ETH_MDC,
  54. MFP101_ETH_MDIO,
  55. MFP103_ETH_RXDV,
  56. /* SSP2 */
  57. MFP107_SSP2_RXD,
  58. MFP108_SSP2_TXD,
  59. MFP110_SSP2_CS,
  60. MFP111_SSP2_CLK,
  61. MFP_EOC /*End of configuration*/
  62. };
  63. /* configure MFP's */
  64. mfp_config(mfp_cfg);
  65. return 0;
  66. }
  67. int board_init(void)
  68. {
  69. struct armd1apb2_registers *apb2_regs =
  70. (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
  71. /* arch number of Board */
  72. gd->bd->bi_arch_number = MACH_TYPE_GPLUGD;
  73. /* adress of boot parameters */
  74. gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
  75. /* Assert PHY_RST# */
  76. gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
  77. udelay(10);
  78. /* Deassert PHY_RST# */
  79. gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
  80. /* Enable SSP2 clock */
  81. writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
  82. return 0;
  83. }
  84. #ifdef CONFIG_ARMADA100_FEC
  85. int board_eth_init(struct bd_info *bis)
  86. {
  87. struct armd1apmu_registers *apmu_regs =
  88. (struct armd1apmu_registers *)ARMD1_APMU_BASE;
  89. /* Enable clock of ethernet controller */
  90. writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
  91. return armada100_fec_register(ARMD1_FEC_BASE);
  92. }
  93. #ifdef CONFIG_RESET_PHY_R
  94. /* Configure and initialize PHY chip 88E3015 */
  95. void reset_phy(void)
  96. {
  97. u16 phy_adr;
  98. const char *name = "armd-fec0";
  99. if (miiphy_set_current_dev(name))
  100. return;
  101. /* command to read PHY dev address */
  102. if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
  103. printf("Err..%s could not read PHY dev address\n", __func__);
  104. return;
  105. }
  106. /* Set Ethernet LED in TX blink mode */
  107. miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
  108. miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
  109. /* reset the phy */
  110. miiphy_reset(name, phy_adr);
  111. debug("88E3015 Initialized on %s\n", name);
  112. }
  113. #endif /* CONFIG_RESET_PHY_R */
  114. #endif /* CONFIG_ARMADA100_FEC */